siliconcompiler 0.35.4__py3-none-any.whl → 0.36.0__py3-none-any.whl

siliconcompiler/tools/keplerformal/lec.py

@@ -0,0 +1,112 @@
+import os.path
+
+from siliconcompiler import Task
+from siliconcompiler.utils import sc_open
+
+
+class LECTask(Task):
+    """LEC task using Kepler-formal for logical equivalence checking."""
+    def tool(self) -> str:
+        return "kepler-formal"
+
+    def task(self) -> str:
+        return "lec"
+
+    def setup(self) -> None:
+        super().setup()
+
+        self.set_exe("kepler-formal")
+
+        # Log file handled by kepler-formal config
+        self.set_logdestination("stdout", "none")
+        self.set_logdestination("stderr", "none")
+
+        if f"{self.design_topmodule}.lec.vg" in self.get_files_from_input_nodes():
+            inputnodes = self.get_files_from_input_nodes()[f"{self.design_topmodule}.lec.vg"]
+            if len(inputnodes) != 2:
+                raise ValueError("LEC requires exactly two input netlists for comparison.")
+            for node in inputnodes:
+                self.add_input_file(
+                    self.compute_input_file_node_name(f"{self.design_topmodule}.lec.vg", *node))
+
+        scenarios = self.project.constraint.timing.get_scenario()
+        if not scenarios:
+            raise ValueError("LEC requires at least one timing scenario to determine "
+                             "library corners.")
+        scenario = list(scenarios.values())[0]
+        libcorners = scenario.get_libcorner(self.step, self.index)
+        delay_model = self.project.get("asic", "delaymodel")
+        for asiclib in self.project.get("asic", "asiclib"):
+            lib = self.project.get("library", asiclib, field="schema")
+            for corner in libcorners:
+                if not lib.valid("asic", "libcornerfileset", corner, delay_model):
+                    continue
+                self.add_required_key(lib, "asic", "libcornerfileset", corner, delay_model)
+                for fileset in lib.get("asic", "libcornerfileset", corner, delay_model):
+                    self.add_required_key(lib, "fileset", fileset, "file", "liberty")
+
+    def __config_file(self) -> str:
+        return "lec.yaml"
+
+    def pre_process(self):
+        super().pre_process()
+
+        with open(self.__config_file(), "w") as f:
+            f.write("format: verilog\n")
+            f.write("input_paths:\n")
+            for node in self.get_files_from_input_nodes()[f"{self.design_topmodule}.lec.vg"]:
+                filename = self.compute_input_file_node_name(f"{self.design_topmodule}.lec.vg",
+                                                             *node)
+                f.write(f"  - inputs/{filename}\n")
+            f.write("liberty_files:\n")
+
+            scenario = list(self.project.constraint.timing.get_scenario().values())[0]
+            libcorners = scenario.get_libcorner(self.step, self.index)
+            delay_model = self.project.get("asic", "delaymodel")
+            for asiclib in self.project.get("asic", "asiclib"):
+                lib = self.project.get("library", asiclib, field="schema")
+                for corner in libcorners:
+                    if not lib.valid("asic", "libcornerfileset", corner, delay_model):
+                        continue
+                    for fileset in lib.get("asic", "libcornerfileset", corner, delay_model):
+                        for file in lib.get_file(fileset=fileset, filetype="liberty"):
+                            f.write(f"  - {file}\n")
+            f.write(f"log_file: {self.get_logpath('exe')}\n")
+
+    def runtime_options(self):
+        options = super().runtime_options()
+        options.append("--config")
+        options.append(self.__config_file())
+        return options
+
+    def post_process(self):
+        super().post_process()
+        # Kepler-formal writes its own log file; nothing to do here.
+        errors = 0
+        log = self.get_logpath('exe')
+        if os.path.exists(log):
+            with sc_open(log, 'r') as f:
+                for logline in f:
+                    if "Found difference " in logline:
+                        errors += 1
+
+            self.record_metric("drvs", errors, source_file=log)
+
+    @classmethod
+    def make_docs(cls):
+        from siliconcompiler import Flowgraph, Design, ASIC
+        from siliconcompiler.scheduler import SchedulerNode
+        from siliconcompiler.targets import freepdk45_demo
+        design = Design("<design>")
+        with design.active_fileset("docs"):
+            design.set_topmodule("top")
+        proj = ASIC(design)
+        proj.add_fileset("docs")
+        freepdk45_demo(proj)
+        flow = Flowgraph("docsflow")
+        flow.node("<step>", cls(), index="<index>")
+        proj.set_flow(flow)
+
+        node = SchedulerNode(proj, "<step>", "<index>")
+        node.setup()
+        return node.task

siliconcompiler/tools/klayout/screenshot.py

@@ -1,3 +1,5 @@
+from typing import Optional, Union
+
 from siliconcompiler import ScreenshotTask, Task
 from siliconcompiler.tools.klayout.show import ShowTask
 
@@ -20,7 +22,70 @@ class ScreenshotParams(Task):
         self.add_parameter("show_linewidth", "int",
                            "Width of lines in detailed screenshots", defvalue=0, unit="px")
         self.add_parameter("show_oversampling", "int",
-                           "Image oversampling used in detailed screenshots'", defvalue=2)
+                           "Image oversampling used in detailed screenshots", defvalue=2)
+
+    def set_klayout_bins(self, xbins: int, ybins: int,
+                         step: Optional[str] = None, index: Optional[Union[str, int]] = None):
+        """
+        Set the number of bins for KLayout screenshotting.
+
+        Args:
+            xbins (int): Number of bins along the x-axis.
+            ybins (int): Number of bins along the y-axis.
+            step (Optional[str]): Flow step to set the parameter for. Defaults to None.
+            index (Optional[Union[str, int]]): Index to set the parameter for. Defaults to None.
+        """
+        self.set("var", "show_bins", (xbins, ybins), step=step, index=index)
+
+    def set_klayout_margin(self, margin: float,
+                           step: Optional[str] = None, index: Optional[Union[str, int]] = None):
+        """
+        Set the margin for KLayout screenshotting.
+
+        Args:
+            margin (float): Margin around the design in microns.
+            step (Optional[str]): Flow step to set the parameter for. Defaults to None.
+            index (Optional[Union[str, int]]): Index to set the parameter for. Defaults to None.
+        """
+        self.set("var", "show_margin", margin, step=step, index=index)
+
+    def set_klayout_resolution(self, xres: int, yres: int,
+                               step: Optional[str] = None, index: Optional[Union[str, int]] = None):
+        """
+        Set the resolution for KLayout screenshotting.
+
+        Args:
+            xres (int): Horizontal resolution in pixels.
+            yres (int): Vertical resolution in pixels.
+            step (Optional[str]): Flow step to set the parameter for. Defaults to None.
+            index (Optional[Union[str, int]]): Index to set the parameter for. Defaults to None.
+        """
+        self.set("var", "show_resolution", (xres, yres), step=step, index=index)
+
+    def set_klayout_linewidth(self, linewidth: int,
+                              step: Optional[str] = None, index: Optional[Union[str, int]] = None):
+        """
+        Set the linewidth for KLayout screenshotting.
+
+        Args:
+            linewidth (int): Width of lines in detailed screenshots.
+            step (Optional[str]): Flow step to set the parameter for. Defaults to None.
+            index (Optional[Union[str, int]]): Index to set the parameter for. Defaults to None.
+        """
+        self.set("var", "show_linewidth", linewidth, step=step, index=index)
+
+    def set_klayout_oversampling(self, oversampling: int,
+                                 step: Optional[str] = None,
+                                 index: Optional[Union[str, int]] = None):
+        """
+        Set the oversampling for KLayout screenshotting.
+
+        Args:
+            oversampling (int): Image oversampling used in detailed screenshots.
+            step (Optional[str]): Flow step to set the parameter for. Defaults to None.
+            index (Optional[Union[str, int]]): Index to set the parameter for. Defaults to None.
+        """
+        self.set("var", "show_oversampling", oversampling, step=step, index=index)
 
     def setup(self):
         super().setup()

siliconcompiler/tools/klayout/scripts/klayout_export.py

@@ -39,24 +39,23 @@ import sys
 import fnmatch
 
 
-def gds_export(design_name, in_def, in_files, out_file, tech, allow_missing, config_file='',
-               seal_file='',
-               timestamps=True):
+def gds_export(design_name, in_def, out_file, tech, allow_missing, timestamps=True):
     from klayout_utils import get_write_options  # noqa E402
 
     # Load def file
     main_layout = pya.Layout()
     main_layout.technology_name = tech.name
-    main_layout.read(in_def, tech.load_layout_options)
+    layout_options = tech.load_layout_options
+    main_layout.read(in_def, layout_options)
 
     # List cells
     def_cells = []
-    for def_cell in main_layout.each_cell():
-        def_cells.append(def_cell.name)
+    for cell_idx in main_layout.cell(design_name).each_child_cell():
+        def_cells.append(main_layout.cell_name(cell_idx))
 
-    def_cells.remove(design_name)
     # Remove vias
-    def_cells = sorted([cell for cell in def_cells if not cell.startswith("VIA_")])
+    via_prefix = layout_options.lefdef_config.via_cellname_prefix
+    def_cells = sorted([cell for cell in def_cells if not cell.startswith(via_prefix)])
     print(f"[INFO] Read in {len(def_cells)} cells from DEF file")
     for cell in def_cells:
         print(f"  [INFO] DEF cell: {cell}")
@@ -65,16 +64,11 @@ def gds_export(design_name, in_def, in_files, out_file, tech, allow_missing, con
         def_cells.remove(f"{design_name}_DEF_FILL")
 
     # Load in the gds to merge
-    print("[INFO] Merging GDS/OAS files...")
-    for fil in in_files:
+    for fil in layout_options.lefdef_config.macro_layout_files:
         macro_layout = pya.Layout()
         macro_layout.read(fil)
-        print(f"[INFO] Read in {fil}")
         for cell in list(def_cells):
             if macro_layout.has_cell(cell):
-                subcell = main_layout.cell(cell)
-                print(f"  [INFO] Merging in {cell}")
-                subcell.copy_tree(macro_layout.cell(cell))
                 def_cells.remove(cell)
 
     # Copy the top level only to a new layout
@@ -100,18 +94,6 @@ def gds_export(design_name, in_def, in_files, out_file, tech, allow_missing, con
         if i.name != design_name and i.parent_cells() == 0:
             print("[ERROR] Found orphan cell '{0}'".format(i.name))
 
-    if seal_file:
-        top_cell = top_only_layout.top_cell()
-
-        print("[INFO] Reading seal GDS/OAS file...")
-        print("\t{0}".format(seal_file))
-        top_only_layout.read(seal_file)
-
-        for cell in top_only_layout.top_cells():
-            if cell != top_cell:
-                print("[INFO] Merging '{0}' as child of '{1}'".format(cell.name, top_cell.name))
-                top.insert(pya.CellInstArray(cell.cell_index(), pya.Trans()))
-
     # Write out the GDS
     print("[INFO] Writing out GDS/OAS '{0}'".format(out_file))
     top_only_layout.write(out_file, get_write_options(out_file, timestamps))
@@ -125,7 +107,6 @@ def main():
 
     from klayout_utils import (
         technology,
-        get_streams,
         save_technology,
         get_schema,
         generate_metrics
@@ -155,18 +136,8 @@ def main():
 
     out_file = os.path.join('outputs', f'{design}.{sc_stream}')
 
-    in_files = []
-    libs = schema.get("asic", "asiclib")
-    for lib in libs:
-        libobj = schema.get("library", lib, field="schema")
-        for s in get_streams(schema):
-            for fileset in libobj.get("asic", "aprfileset"):
-                if libobj.valid("fileset", fileset, "file", s):
-                    in_files.extend(libobj.get("fileset", fileset, "file", s))
-                    break
-
     allow_missing = []
-    for lib in libs:
+    for lib in schema.get("asic", "asiclib"):
         if schema.valid('library', lib, 'tool', 'klayout', 'allow_missing_cell'):
             patterns = [pattern for pattern in schema.get('library', lib, 'tool', 'klayout',
                                                           'allow_missing_cell') if pattern]
@@ -179,8 +150,7 @@ def main():
 
     sc_tech = technology(design, schema)
 
-    gds_export(design, in_def, in_files, out_file, sc_tech, allow_missing,
-               config_file='', seal_file='', timestamps=sc_timestamps)
+    gds_export(design, in_def, out_file, sc_tech, allow_missing, timestamps=sc_timestamps)
 
     if sc_screenshot:
         show(schema, sc_tech, out_file, f'outputs/{design}.png', screenshot=True)

siliconcompiler/tools/klayout/scripts/klayout_show.py

@@ -25,7 +25,7 @@ def show(schema, tech, input_path, output_path, screenshot=False, report=None):
     layout_options.lefdef_config.produce_obstructions = True
 
     # Always use LEF geometry even when LEF file contains FOREIGN statement.
-    layout_options.lefdef_config.macro_resolution_mode = 1
+    layout_options.lefdef_config.macro_resolution_mode = 0
 
     tech.load_layout_options = layout_options
 
@@ -118,9 +118,9 @@ def __screenshot_montage(schema, view, xbins, ybins):
 
     app.set_config("background-color", "#000000")  # Black
 
-    design = schema.get('option', 'entrypoint')
-    if not design:
-        design = schema.get('design')
+    design_name = schema.get('option', 'design')
+    fileset = schema.get("option", "fileset")[0]
+    design = schema.get("library", design_name, "fileset", fileset, "topmodule")
 
     horizontal_resolution, vertical_resolution = schema.get(
         'tool', 'klayout', 'task', task, 'var', 'show_resolution', step=step, index=index)

siliconcompiler/tools/klayout/scripts/klayout_utils.py

@@ -76,7 +76,7 @@ def technology(design, schema):
 
     layout_options = tech.load_layout_options
 
-    layout_options.lefdef_config.macro_resolution_mode = 1
+    layout_options.lefdef_config.macro_resolution_mode = 0
     layout_options.lefdef_config.via_cellname_prefix = "VIA_"
     pathed_files = set()
     for lef_file in layout_options.lefdef_config.lef_files:
@@ -98,6 +98,18 @@ def technology(design, schema):
     for lef_file in layout_options.lefdef_config.lef_files:
         print(f"[INFO] LEF file: {lef_file}")
 
+    in_files = layout_options.lefdef_config.macro_layout_files
+    for lib in schema.get("asic", "asiclib"):
+        libobj = schema.get("library", lib, field="schema")
+        for s in get_streams(schema):
+            for fileset in libobj.get("asic", "aprfileset"):
+                if libobj.valid("fileset", fileset, "file", s):
+                    in_files.extend(libobj.get("fileset", fileset, "file", s))
+                    break
+    layout_options.lefdef_config.macro_layout_files = in_files
+    for lef_file in layout_options.lefdef_config.macro_layout_files:
+        print(f"[INFO] Layout file: {lef_file}")
+
     # Set layer properties
     layer_properties = tech.layer_properties_file
     if layer_properties:

siliconcompiler/tools/montage/tile.py

@@ -1,20 +1,11 @@
-from siliconcompiler import Task
+from typing import Optional, Union
+
+from siliconcompiler import Task, TaskSkip
 
 
 class TileTask(Task):
     '''
     Tiles input images into a single output image.
-
-    Notes:
-        Need to make ensure that /etc/ImageMagick-6/policy.xml
-        <policy domain="resource" name="memory" value="8GiB"/>
-        <policy domain="resource" name="map" value="8GiB"/>
-        <policy domain="resource" name="width" value="32KP"/>
-        <policy domain="resource" name="height" value="32KP"/>
-        <policy domain="resource" name="area" value="1GP"/>
-        <policy domain="resource" name="disk" value="8GiB"/>
-        This ensures there are enough resources available to generate
-        the final image.
     '''
 
     def __init__(self):
@@ -23,6 +14,19 @@ class TileTask(Task):
         self.add_parameter("bins", "(int,int)", "Number of bins along the (x, y)-axis",
                            defvalue=(2, 2))
 
+    def set_montage_bins(self, xbins: int, ybins: int,
+                         step: Optional[str] = None, index: Optional[Union[str, int]] = None):
+        """
+        Set the number of bins for Montage tiling.
+
+        Args:
+            xbins (int): Number of bins along the x-axis.
+            ybins (int): Number of bins along the y-axis.
+            step (Optional[str]): Flow step to set the parameter for. Defaults to None.
+            index (Optional[Union[str, int]]): Index to set the parameter for. Defaults to None.
+        """
+        self.set("var", "bins", (xbins, ybins), step=step, index=index)
+
     def tool(self):
         return "montage"
 
@@ -41,12 +45,22 @@ class TileTask(Task):
 
         xbins, ybins = self.get("var", "bins")
 
+        if f"{self.design_topmodule}.png" in self.get_files_from_input_nodes():
+            raise TaskSkip("Input provides a single image; skipping tiling.")
+
         for x in range(xbins):
             for y in range(ybins):
                 self.add_input_file(f'{self.design_topmodule}_X{x}_Y{y}.png')
 
         self.add_output_file(ext="png")
 
+        self.add_commandline_option(['-limit', 'memory', '8GiB'])
+        self.add_commandline_option(['-limit', 'map', '8GiB'])
+        self.add_commandline_option(['-limit', 'disk', '8GiB'])
+        self.add_commandline_option(['-limit', 'width', '32KP'])
+        self.add_commandline_option(['-limit', 'height', '32KP'])
+        self.add_commandline_option(['-limit', 'area', '1GP'])
+
     def runtime_options(self):
         options = super().runtime_options()
 

siliconcompiler/tools/openroad/_apr.py

@@ -374,9 +374,12 @@ class OpenROADDRTParameter(_OpenROADDRTCommonParameter):
         self.add_parameter("drt_disable_via_gen", "bool",
                            "true/false, when true turns off via generation in detailed router "
                            "and only uses the specified tech vias", defvalue=False)
-        self.add_parameter("drt_via_in_pin_bottom_layer", "str", "TODO")
-        self.add_parameter("drt_via_in_pin_top_layer", "str", "TODO")
-        self.add_parameter("drt_repair_pdn_vias", "str", "TODO")
+        self.add_parameter("drt_via_in_pin_bottom_layer", "str",
+                           "bottom layer to allow vias inside pins")
+        self.add_parameter("drt_via_in_pin_top_layer", "str",
+                           "top layer to allow vias inside pins")
+        self.add_parameter("drt_repair_pdn_vias", "str",
+                           "layer to repair PDN vias on")
 
         self.add_parameter("drt_report_interval", "int",
                            "reporting interval in steps for generating a DRC report.", defvalue=5)
@@ -635,13 +638,22 @@ class APRTask(OpenROADTask):
     def _add_pnr_outputs(self):
         self.add_output_file(ext="sdc")
         self.add_output_file(ext="vg")
+        self.add_output_file(ext="lec.vg")
         self.add_output_file(ext="def")
         self.add_output_file(ext="odb")
 
+        for lib in self.project.get("asic", "asiclib"):
+            libobj = self.project.get("library", lib, field="schema")
+            for celltype in ["decap", "tie", "filler", "tap", "endcap", "antenna", "physicalonly"]:
+                if libobj.valid("asic", "cells", celltype) and \
+                        libobj.get("asic", "cells", celltype):
+                    self.add_required_key(libobj, "asic", "cells", celltype)
+
     def _get_pex_mapping(self):
         corners = {}
-        for constraint in self.project.getkeys('constraint', 'timing'):
-            pexcorner = self.project.get('constraint', 'timing', constraint, 'pexcorner',
+        for constraint in self.project.getkeys('constraint', 'timing', 'scenario'):
+            pexcorner = self.project.get('constraint', 'timing', 'scenario',
+                                         constraint, 'pexcorner',
                                          step=self.step, index=self.index)
             if pexcorner:
                 corners[constraint] = pexcorner
@@ -649,13 +661,17 @@ class APRTask(OpenROADTask):
         return corners
 
     def _get_constraint_by_check(self, check: str) -> str:
-        for constraint in self.project.getkeys('constraint', 'timing'):
-            if check in self.project.get('constraint', 'timing', constraint, 'check',
+        for constraint in self.project.getkeys('constraint', 'timing', 'scenario'):
+            if check in self.project.get('constraint', 'timing', 'scenario',
+                                         constraint, 'check',
                                          step=self.step, index=self.index):
                 return constraint
 
         # if not specified, just pick the first constraint available
-        return self.project.getkeys('constraint', 'timing')[0]
+        scenarios = self.project.getkeys('constraint', 'timing', 'scenario')
+        if not scenarios:
+            raise ValueError("No timing scenarios defined in project constraints.")
+        return scenarios[0]
 
     def _build_pex_estimation_file(self):
         corners = self._get_pex_mapping()
@@ -761,9 +777,9 @@ class APRTask(OpenROADTask):
             ],
             "peakpower": [
                 *[f"power/{corner}.rpt"
-                  for corner in self.project.getkeys('constraint', 'timing')],
+                  for corner in self.project.getkeys('constraint', 'timing', 'scenario')],
                 *[f"images/heatmap/power_density/{corner}.png"
-                    for corner in self.project.getkeys('constraint', 'timing')]
+                    for corner in self.project.getkeys('constraint', 'timing', 'scenario')]
             ],
             "drvs": [
                 "timing/drv_violators.rpt",

siliconcompiler/tools/openroad/init_floorplan.py

@@ -149,8 +149,11 @@ class InitFloorplanTask(APRTask,
 
         # Mark requires for components, pin, and floorplan placements
         for component in self.project.constraint.component.get_component().values():
-            self.add_required_key(component, "placement")
-            self.add_required_key(component, "rotation")
+            if component.get_placement(step=self.step, index=self.index) is not None:
+                self.add_required_key(component, "placement")
+                self.add_required_key(component, "rotation")
+            if component.get_halo(step=self.step, index=self.index) is not None:
+                self.add_required_key(component, "halo")
             if component.get_partname(step=self.step, index=self.index):
                 self.add_required_key(component, "partname")
 

siliconcompiler/tools/openroad/power_grid_analysis.py

@@ -142,7 +142,7 @@ class PowerGridAnalysisTask(APRTask, OpenROADPSMParameter, OpenROADSTAParameter)
         super().setup()
         self.set_script("apr/sc_irdrop.tcl")
 
-        self.add_version(">=v2.0-26750", clobber=True)
+        self.add_version(">=v2.0-26866", clobber=True)
 
         # Output is not a standard design file, unset default expectation
         self.unset("output")

siliconcompiler/tools/openroad/scripts/apr/sc_init_floorplan.tcl

@@ -299,6 +299,8 @@ if { [sc_cfg_exists constraint component] } {
     set x_grid [ord::dbu_to_microns $x_grid]
     set y_grid [ord::dbu_to_microns $y_grid]
 
+    set sc_placed_insts []
+
     dict for {name params} [sc_cfg_get constraint component] {
         set location [dict get $params placement]
         set rotation [sc_convert_rotation [dict get $params rotation]]
@@ -308,11 +310,27 @@ if { [sc_cfg_exists constraint component] } {
         } else {
             set cell ""
         }
+        set halo {}
         if { [llength [dict get $params halo]] != 0 } {
-            utl::warn FLW 1 "Halo is not supported in OpenROAD"
+            if { [llength [dict get $params halo]] == 2 } {
+                set halo [dict get $params halo]
+            } else {
+                utl::warn FLW 1 "Halo must be a list of 2 elements"
+            }
         }
 
-        set inst [[ord::get_db_block] findInst $name]
+        set stainst [get_cells -quiet $name]
+        if { $stainst != {} } {
+            if { [llength $stainst] > 1 } {
+                utl::error FLW 1 "Multiple cells found for instance $name"
+            }
+            set inst [sta::sta_to_db_inst $stainst]
+        } else {
+            set inst "NULL"
+        }
+        if { $inst == "NULL" } {
+            set inst [[ord::get_db_block] findInst $name]
+        }
         if { $inst == "NULL" } {
             utl::warn FLW 1 "Could not find instance: $name"
 
@@ -324,23 +342,40 @@ if { [sc_cfg_exists constraint component] } {
             set cell ""
         }
 
-        set x_loc [expr { round([lindex $location 0] / $x_grid) * $x_grid }]
-        set y_loc [expr { round([lindex $location 1] / $y_grid) * $y_grid }]
+        if { $inst != "NULL" } {
+            set name [$inst getName]
+        }
+
+        if { [llength $location] == 2 } {
+            # Only place if location is specified
+            set x_loc [expr { round([lindex $location 0] / $x_grid) * $x_grid }]
+            set y_loc [expr { round([lindex $location 1] / $y_grid) * $y_grid }]
+
+            set place_inst_args []
+            if { $cell != "" } {
+                lappend place_inst_args -cell $cell
+            }
 
-        set place_inst_args []
-        if { $cell != "" } {
-            lappend place_inst_args -cell $cell
+            place_inst \
+                -name $name \
+                -origin "$x_loc $y_loc" \
+                -orient $rotation \
+                -status FIRM \
+                {*}$place_inst_args
         }
 
-        place_inst \
-            -name $name \
-            -location "$x_loc $y_loc" \
-            -orient $rotation \
-            -status FIRM \
-            {*}$place_inst_args
+        if { $halo != {} } {
+            set inst [[ord::get_db_block] findInst $name]
+            odb::dbBox_create $inst \
+                [ord::microns_to_dbu [lindex $halo 0]] \
+                [ord::microns_to_dbu [lindex $halo 1]] \
+                [ord::microns_to_dbu [lindex $halo 0]] \
+                [ord::microns_to_dbu [lindex $halo 1]]
+        }
+        lappend sc_placed_insts $name
     }
 
-    sc_print_macro_information
+    sc_print_macro_information $sc_placed_insts
 }
 
 if { [sc_check_version 23008] } {

siliconcompiler/tools/openroad/scripts/apr/sc_irdrop.tcl

@@ -89,7 +89,8 @@ foreach net $nets {
     foreach corner $sc_scenarios {
         analyze_power_grid -net $net -corner $corner -allow_reuse
 
-        save_animated_gif -start "reports/${net}/${corner}.gif"
+        set gif [save_animated_gif -start "reports/${net}/${corner}.gif"]
+        set gif_log [save_animated_gif -start "reports/${net}/${corner}_log.gif"]
 
         foreach layer [[ord::get_db_tech] getLayers] {
             if { [$layer getRoutingLevel] == 0 } {
@@ -123,7 +124,7 @@ foreach net $nets {
             sc_save_image \
                 "IR drop for $net on $layer_name for $corner heatmap" \
                 reports/${net}/${corner}.${layer_name}.png \
-                true
+                $gif
 
             gui::set_heatmap IRDrop LogScale 1
             gui::set_heatmap IRDrop rebuild
@@ -131,7 +132,7 @@ foreach net $nets {
             sc_save_image \
                 "IR drop for $net on $layer_name for $corner heatmap" \
                 reports/${net}/${corner}.${layer_name}_log.png \
-                false
+                $gif_log
 
             gui::set_display_controls "Heat Maps/IR Drop" visible false
 
@@ -139,7 +140,8 @@ foreach net $nets {
                 gui::delete_label $label
             }
         }
-        save_animated_gif -end
+        save_animated_gif -end -key $gif
+        save_animated_gif -end -key $gif_log
     }
 }