siliconcompiler 0.35.3__py3-none-any.whl → 0.35.4__py3-none-any.whl

siliconcompiler/tools/openroad/scripts/apr/sc_irdrop.tcl

@@ -0,0 +1,146 @@
+###############################
+# Reading SC Schema
+###############################
+
+source ./sc_manifest.tcl
+
+###############################
+# Task Preamble
+###############################
+
+set sc_refdir [sc_cfg_tool_task_get refdir]
+source "$sc_refdir/apr/preamble.tcl"
+
+set nets []
+if { [llength [sc_cfg_tool_task_get var net]] > 0 } {
+    set nets [sc_cfg_tool_task_get var net]
+} else {
+    set nets [sc_psm_check_nets]
+}
+
+###############################
+# Assign power
+###############################
+
+foreach inst_setting [sc_cfg_tool_task_get var instance_power] {
+    lassign $inst_setting inst power
+    set pwr_mw [expr { $power * 1000 }]
+    puts "Setting power for $inst to: [format "%.3f" $pwr_mw]mW"
+
+    set_pdnsim_inst_power \
+        -inst $inst \
+        -power $power
+}
+
+###############################
+# Depopulate Terminals
+###############################
+
+if { [sc_cfg_tool_task_get var source_disconnection_rate] > 0 } {
+    expr { srand([sc_cfg_tool_task_get var source_disconnection_seed]) }
+
+    set depop_target [expr { [sc_cfg_tool_task_get var source_disconnection_rate] / 100.0 }]
+
+    foreach net $nets {
+        set count 0
+        set disabled 0
+        foreach bpin [[[ord::get_db_block] findBTerm $net] getBPins] {
+            foreach box [$bpin getBoxes] {
+                incr count
+                if { rand() < $depop_target } {
+                    incr disabled
+                    odb::dbBoolProperty_create $box PSM_DISCONNECT 1
+                }
+            }
+        }
+        set term_proc [expr { 100 * (double($disabled) / $count) }]
+        utl::info FLW 1 "$net terminals disabled $disabled / $count ([format "%.1f" $term_proc]%)"
+    }
+}
+
+###############################
+# Setup power grid analysis
+###############################
+
+set source_args []
+
+set res [sc_cfg_tool_task_get var external_resistance]
+if { $res > 0 } {
+    puts "Setting external resistance to $res ohms"
+    lappend source_args -external_resistance $res
+}
+
+if { [llength $source_args] != 0 } {
+    set_pdnsim_source_settings {*}$source_args
+}
+
+###############################
+# Analyze nets
+###############################
+
+lassign [sc_cfg_tool_task_get var heatmap_grid] heatmap_x heatmap_y
+gui::save_display_controls
+
+sc_image_setup_default
+gui::set_display_controls "Shape Types/Pin*" visible false
+
+foreach net $nets {
+    file mkdir reports/${net}
+    foreach corner $sc_scenarios {
+        analyze_power_grid -net $net -corner $corner -allow_reuse
+
+        save_animated_gif -start "reports/${net}/${corner}.gif"
+
+        foreach layer [[ord::get_db_tech] getLayers] {
+            if { [$layer getRoutingLevel] == 0 } {
+                continue
+            }
+            set layer_name [$layer getName]
+
+            gui::set_heatmap IRDrop Net $net
+            gui::set_heatmap IRDrop Corner $corner
+            gui::set_heatmap IRDrop Layer $layer_name
+            gui::set_heatmap IRDrop LogScale 0
+            gui::set_heatmap IRDrop ShowLegend 1
+            gui::set_heatmap IRDrop GridX $heatmap_x
+            gui::set_heatmap IRDrop GridY $heatmap_y
+            gui::set_display_controls "Heat Maps/IR Drop" visible true
+
+            gui::set_heatmap IRDrop rebuild
+
+            if { ![gui::get_heatmap_bool IRDrop has_data] } {
+                continue
+            }
+
+            # Save CSV
+            gui::dump_heatmap IRDrop reports/${net}/${corner}.${layer_name}.csv
+
+            set box [[ord::get_db_block] getDieArea]
+            set x [ord::dbu_to_microns [$box xMax]]
+            set y [ord::dbu_to_microns [$box yMin]]
+            set label [add_label -position "$x $y" -anchor "bottom right" -color white $layer_name]
+
+            sc_save_image \
+                "IR drop for $net on $layer_name for $corner heatmap" \
+                reports/${net}/${corner}.${layer_name}.png \
+                true
+
+            gui::set_heatmap IRDrop LogScale 1
+            gui::set_heatmap IRDrop rebuild
+
+            sc_save_image \
+                "IR drop for $net on $layer_name for $corner heatmap" \
+                reports/${net}/${corner}.${layer_name}_log.png \
+                false
+
+            gui::set_display_controls "Heat Maps/IR Drop" visible false
+
+            if { $label != "" } {
+                gui::delete_label $label
+            }
+        }
+        save_animated_gif -end
+    }
+}
+
+gui::restore_display_controls

siliconcompiler/tools/openroad/scripts/apr/sc_repair_design.tcl

@@ -52,7 +52,7 @@ sc_set_dont_use
 # Tie-off cell insertion
 ###############################
 
-set tie_separation [lindex [sc_cfg_tool_task_get {var} ifp_tie_separation] 0]
+set tie_separation [sc_cfg_tool_task_get {var} ifp_tie_separation]
 foreach tie_type "high low" {
     if { [sc_has_tie_cell $tie_type] } {
         repair_tie_fanout \

siliconcompiler/tools/openroad/scripts/apr/sc_write_data.tcl

@@ -33,12 +33,10 @@ write_abstract_lef {*}$lef_args "outputs/${sc_topmodule}.lef"
 if { [sc_cfg_tool_task_get var write_cdl] } {
     # Write CDL
     set sc_cdl_masters []
-    foreach lib "$sc_targetlibs $sc_macrolibs" {
-        #CDL files
-        if { [sc_cfg_exists library $lib output $sc_stackup cdl] } {
-            foreach cdl_file [sc_cfg_get library $lib output $sc_stackup cdl] {
-                lappend sc_cdl_masters $cdl_file
-            }
+    foreach lib $sc_logiclibs {
+        set filesets [sc_cfg_get library $lib asic aprfileset]
+        foreach cdl_file [sc_cfg_get_fileset $lib $filesets cdl] {
+            lappend sc_cdl_masters $cdl_file
         }
     }
     write_cdl -masters $sc_cdl_masters "outputs/${sc_topmodule}.cdl"

siliconcompiler/tools/openroad/scripts/common/procs.tcl

@@ -14,7 +14,7 @@ proc sc_global_placement_density { args } {
 
     set density_args []
     if { ![info exists flags(-exclude_padding)] } {
-        set gpl_padding [lindex [sc_cfg_tool_task_get var pad_global_place] 0]
+        set gpl_padding [sc_cfg_tool_task_get var pad_global_place]
 
         lappend density_args -pad_left $gpl_padding
         lappend density_args -pad_right $gpl_padding

siliconcompiler/tools/openroad/scripts/common/reports.tcl

@@ -8,7 +8,7 @@ file mkdir reports/power
 file mkdir reports/markers
 
 set fields "{capacitance slew input_pins hierarcial_pins net fanout}"
-set sta_top_n_paths [lindex [sc_cfg_tool_task_get var sta_top_n_paths] 0]
+set sta_top_n_paths [sc_cfg_tool_task_get var sta_top_n_paths]
 set PREFIX "SC_METRIC:"
 
 if { [sc_cfg_tool_task_check_in_list setup var reports] } {

siliconcompiler/tools/openroad/scripts/rcx/sc_rcx_bench.tcl

@@ -1,10 +1,8 @@
 #https://github.com/The-OpenROAD-Project/OpenROAD/blob/9b52b1d9cfb532f9872739ffe482afb5ac9def92/src/rcx/calibration/script/generate_rules.tcl
 
-set openroad_bench_length \
-    [lindex [sc_cfg_tool_task_get {var} bench_length] 0]
+set openroad_bench_length [sc_cfg_tool_task_get {var} bench_length]
 
-set sc_maxmetal \
-    [sc_get_layer_name [lindex [sc_cfg_tool_task_get {var} max_layer] 0]]
+set sc_maxmetal [sc_get_layer_name [sc_cfg_tool_task_get {var} max_layer]]
 set openroad_top_metal_number [[[ord::get_db_tech] findLayer $sc_maxmetal] getRoutingLevel]
 
 # Creates the patterns and

siliconcompiler/tools/opensta/__init__.py

@@ -37,7 +37,7 @@ class OpenSTATask(Task):
         self.set_threads()
 
         self.add_regex("warnings", r'^\[WARNING|^Warning')
-        self.add_regex("errors", r'^\[ERROR')
+        self.add_regex("errors", r'^\[ERROR|^Error')
 
     def runtime_options(self):
         options = super().runtime_options()

siliconcompiler/tools/opensta/scripts/sc_timing.tcl

@@ -12,7 +12,7 @@ set sc_topmodulelib [sc_cfg_get option design]
 set sc_filesets [sc_cfg_get option fileset]
 
 # APR Parameters
-set sc_timing_mode [lindex [sc_cfg_tool_task_get var timing_mode] 0]
+set sc_timing_mode [sc_cfg_tool_task_get var timing_mode]
 
 set sc_mainlib []
 set sc_logiclibs []
@@ -24,7 +24,10 @@ if { $opensta_timing_mode == "asic" } {
     set sc_delaymodel [sc_cfg_get asic delaymodel]
 
     foreach corner [dict keys [sc_cfg_get constraint timing]] {
-        if { [sc_cfg_get constraint timing $corner mode] == $sc_timing_mode } {
+        if {
+            $sc_timing_mode == {} ||
+            [sc_cfg_get constraint timing $corner mode] == $sc_timing_mode
+        } {
             lappend sc_scenarios $corner
         }
     }
@@ -111,14 +114,16 @@ if { [file exists "inputs/${sc_topmodule}.sdc"] } {
         lappend sdc_files $sdc
     }
 
-    set sdcfileset [sc_cfg_get constraint timing $corner sdcfileset]
-    foreach corner $sc_scenarios {
-        foreach sdc [sc_cfg_get_fileset $sc_topmodulelib $sdcfileset sdc] {
-            if { [lsearch -exact $sdc_files $sdc] == -1 } {
-                # read step constraint if exists
-                puts "Reading mode (${sc_timing_mode}) SDC: ${sdc}"
-                lappend sdc_files $sdc
-                read_sdc $sdc
+    if { $sc_timing_mode != {} } {
+        foreach corner $sc_scenarios {
+            set sdcfileset [sc_cfg_get constraint timing $corner sdcfileset]
+            foreach sdc [sc_cfg_get_fileset $sc_topmodulelib $sdcfileset sdc] {
+                if { [lsearch -exact $sdc_files $sdc] == -1 } {
+                    # read step constraint if exists
+                    puts "Reading mode (${sc_timing_mode}) SDC: ${sdc}"
+                    lappend sdc_files $sdc
+                    read_sdc $sdc
+                }
             }
         }
     }
@@ -137,7 +142,7 @@ if { [llength [sta::path_group_names]] == 0 } {
 
     if {
         [llength [all_clocks]] == 1 ||
-        [lindex [sc_cfg_tool_task_get var unique_path_groups_per_clock] 0] == "false"
+        ![sc_cfg_tool_task_get var unique_path_groups_per_clock]
     } {
         sc_path_group -name in2reg -from [all_inputs -no_clocks] -to [all_registers]
         sc_path_group -name reg2reg -from [all_registers] -to [all_registers]
@@ -195,7 +200,7 @@ if { $opensta_timing_mode == "asic" } {
 # Report Metrics
 ###############################
 
-set opensta_top_n_paths [lindex [sc_cfg_tool_task_get var top_n_paths] 0]
+set opensta_top_n_paths [sc_cfg_tool_task_get var top_n_paths]
 
 set fields "{capacitance slew input_pins hierarcial_pins net fanout}"
 set PREFIX "SC_METRIC:"

siliconcompiler/tools/vivado/scripts/sc_bitstream.tcl

@@ -1,2 +1,13 @@
 open_checkpoint "inputs/${sc_topmodule}.dcp"
+
+foreach sc_pre_script [sc_cfg_tool_task_get prescript] {
+    puts "Sourcing pre script: ${sc_pre_script}"
+    source $sc_pre_script
+}
+
 write_bitstream -force -file "outputs/${sc_topmodule}.bit"
+
+foreach sc_post_script [sc_cfg_tool_task_get postscript] {
+    puts "Sourcing post script: ${sc_post_script}"
+    source $sc_post_script
+}

siliconcompiler/tools/vivado/scripts/sc_place.tcl

@@ -1,2 +1,13 @@
 open_checkpoint "inputs/${sc_topmodule}.dcp"
+
+foreach sc_pre_script [sc_cfg_tool_task_get prescript] {
+    puts "Sourcing pre script: ${sc_pre_script}"
+    source $sc_pre_script
+}
+
 place_design
+
+foreach sc_post_script [sc_cfg_tool_task_get postscript] {
+    puts "Sourcing post script: ${sc_post_script}"
+    source $sc_post_script
+}

siliconcompiler/tools/vivado/scripts/sc_route.tcl

@@ -1,4 +1,15 @@
 open_checkpoint "inputs/${sc_topmodule}.dcp"
+
+foreach sc_pre_script [sc_cfg_tool_task_get prescript] {
+    puts "Sourcing pre script: ${sc_pre_script}"
+    source $sc_pre_script
+}
+
 phys_opt_design
 power_opt_design
 route_design
+
+foreach sc_post_script [sc_cfg_tool_task_get postscript] {
+    puts "Sourcing post script: ${sc_post_script}"
+    source $sc_post_script
+}

siliconcompiler/tools/vivado/scripts/sc_syn_fpga.tcl

@@ -3,6 +3,11 @@ create_project $sc_topmodule -force
 set_property part $sc_partname [current_project]
 set_property target_language Verilog [current_project]
 
+foreach sc_pre_script [sc_cfg_tool_task_get prescript] {
+    puts "Sourcing pre script: ${sc_pre_script}"
+    source $sc_pre_script
+}
+
 # add imported files
 if { [string equal [get_filesets -quiet sources_1] ""] } {
     create_fileset -srcset sources_1
@@ -28,3 +33,8 @@ if { $synth_mode != "none" } {
 synth_design -top $sc_topmodule {*}$synth_args
 
 opt_design
+
+foreach sc_post_script [sc_cfg_tool_task_get postscript] {
+    puts "Sourcing post script: ${sc_post_script}"
+    source $sc_post_script
+}

siliconcompiler/tools/vpr/__init__.py

@@ -272,8 +272,17 @@ class VPRTask(Task):
             if lib.has_file(fileset=fileset, filetype="sdc"):
                 self.add_required_key(lib, "fileset", fileset, "file", "sdc")
                 self.set("var", "enable_timing_analysis", True)
+
+        fpga = self.project.get("library", self.project.get("fpga", "device"), field="schema")
+        self.add_required_key(fpga, "tool", "vpr", "devicecode")
+        self.add_required_key(fpga, "tool", "vpr", "clock_model")
+        self.add_required_key(fpga, "tool", "vpr", "archfile")
+        self.add_required_key(fpga, "tool", "vpr", "graphfile")
+        self.add_required_key(fpga, "tool", "vpr", "channelwidth")
         if self.get("var", "router_lookahead"):
             self.add_required_key("var", "router_lookahead")
+        else:
+            self.add_required_key(fpga, "tool", "vpr", "router_lookahead")
 
     def runtime_options(self):
         options = super().runtime_options()
@@ -520,3 +529,22 @@ class VPRTask(Task):
                 if path.match(line):
                     count += 1
         return count
+
+    @classmethod
+    def make_docs(cls):
+        from siliconcompiler import Flowgraph, Design, FPGA
+        from siliconcompiler.scheduler import SchedulerNode
+        from siliconcompiler.demos.fpga_demo import Z1000
+        design = Design("<design>")
+        with design.active_fileset("docs"):
+            design.set_topmodule("top")
+        proj = FPGA(design)
+        proj.add_fileset("docs")
+        proj.set_fpga(Z1000())
+        flow = Flowgraph("docsflow")
+        flow.node("<step>", cls(), index="<index>")
+        proj.set_flow(flow)
+
+        node = SchedulerNode(proj, "<step>", "<index>")
+        node.setup()
+        return node.task

siliconcompiler/tools/yosys/scripts/sc_screenshot.tcl

@@ -43,7 +43,7 @@ if { [file exists "inputs/$sc_design.v"] } {
     set file_type "vg"
 } elseif { [sc_cfg_tool_task_exists var show_filepath] } {
     yosys read_verilog -noblackbox -sv [sc_cfg_tool_task_get var show_filepath]
-    set file_type [lindex [sc_cfg_tool_task_get var show_filetype] 0]
+    set file_type [sc_cfg_tool_task_get var show_filetype]
 }
 
 ########################################################

siliconcompiler/tools/yosys/scripts/sc_synth_asic.tcl

@@ -80,7 +80,16 @@ if { ![file exists $input_verilog] } {
     }
 }
 
-if { [sc_cfg_tool_task_get var use_slang] && [sc_load_plugin slang] } {
+set use_slang false
+if { [sc_cfg_tool_task_get var use_slang] } {
+    if { ![sc_load_plugin slang] } {
+        puts "WARNING: Unable to load slang plugin reverting back to yosys read_verilog"
+    } else {
+        set use_slang true
+    }
+}
+
+if { $use_slang } {
     # This needs some reordering of loaded to ensure blackboxes are handled
     # before this
     set slang_params []
@@ -90,6 +99,7 @@ if { [sc_cfg_tool_task_get var use_slang] && [sc_load_plugin slang] } {
             lappend slang_params -G "${key}=${value}"
         }
     }
+    yosys slang_version
     yosys read_slang \
         -D SYNTHESIS \
         --keep-hierarchy \
@@ -272,7 +282,29 @@ if { !$flatten_design && [sc_cfg_tool_task_get var auto_flatten] } {
 }
 
 # Finish synthesis
-yosys synth {*}$synth_args -top $sc_topmodule -run fine:check
+# Unroll of synth -run fine:check
+set opt_args []
+if { [sc_cfg_tool_task_get var opt_undriven] } {
+    lappend opt_args -undriven
+}
+yosys opt -fast -mux_undef -mux_bool -fine {*}$opt_args
+yosys memory_map
+yosys opt -mux_undef -mux_bool -fine {*}$opt_args
+
+set tech_map_args []
+lappend tech_map_args "-map" "+/techmap.v"
+foreach extra_map [sc_cfg_tool_task_get var synth_extra_map] {
+    lappend tech_map_args "-map" $extra_map
+}
+yosys techmap {*}$tech_map_args
+
+yosys opt -fast
+yosys abc -fast
+yosys opt -fast
+
+yosys hierarchy -check
+yosys stat
+yosys check
 
 # Logic locking
 if { [sc_cfg_tool_task_get var lock_design] } {
@@ -440,7 +472,11 @@ yosys clean -purge
 # Recheck hierarchy to remove all unused modules
 yosys hierarchy -top $sc_topmodule
 
-yosys setundef -zero
+if { [sc_cfg_tool_task_get var tie_undef] == "high" } {
+    yosys setundef -one
+} elseif { [sc_cfg_tool_task_get var tie_undef] == "low" } {
+    yosys setundef -zero
+}
 
 yosys splitnets
 
@@ -453,7 +489,7 @@ if { [sc_has_tie_cell low] } {
 if { [sc_has_tie_cell high] } {
     lappend yosys_hilomap_args -hicell {*}[sc_get_tie_cell high]
 }
-if { [llength $yosys_hilomap_args] != 0 } {
+if { [sc_cfg_tool_task_get var add_tieoffs] && [llength $yosys_hilomap_args] != 0 } {
     yosys hilomap -singleton {*}$yosys_hilomap_args
 }
 

siliconcompiler/tools/yosys/scripts/sc_synth_fpga.tcl

@@ -30,7 +30,16 @@ if { ![file exists $input_verilog] } {
     set input_verilog "inputs/$sc_topmodule.sv"
 }
 
-if { [sc_cfg_tool_task_get var use_slang] && [sc_load_plugin slang] } {
+set use_slang false
+if { [sc_cfg_tool_task_get var use_slang] } {
+    if { ![sc_load_plugin slang] } {
+        puts "WARNING: Unable to load slang plugin reverting back to yosys read_verilog"
+    } else {
+        set use_slang true
+    }
+}
+
+if { $use_slang } {
     # This needs some reordering of loaded to ensure blackboxes are handled
     # before this
     set slang_params []
@@ -40,6 +49,7 @@ if { [sc_cfg_tool_task_get var use_slang] && [sc_load_plugin slang] } {
             lappend slang_params -G "${key}=${value}"
         }
     }
+    yosys slang_version
     yosys read_slang \
         -D SYNTHESIS \
         --keep-hierarchy \
@@ -73,9 +83,7 @@ set sc_syn_lut_size [sc_cfg_get library $sc_designlib fpga lutsize]
 # comment in syn_asic.tcl for longer explanation.
 yosys hierarchy -top $sc_topmodule
 
-if { [string match {ice*} $sc_partname] } {
-    yosys synth_ice40 -top $sc_topmodule
-} elseif {
+if {
     [sc_cfg_exists library $sc_designlib tool yosys fpga_config] &&
     [sc_cfg_get library $sc_designlib tool yosys fpga_config] != {} &&
     [sc_load_plugin wildebeest]
@@ -83,7 +91,7 @@ if { [string match {ice*} $sc_partname] } {
     set synth_fpga_args []
     if { [sc_cfg_tool_task_get var synth_opt_mode] != "none" } {
         lappend synth_fpga_args \
-            -opt [lindex [sc_cfg_tool_task_get var synth_opt_mode] 0]
+            -opt [sc_cfg_tool_task_get var synth_opt_mode]
     }
     if { [sc_cfg_tool_task_get var synth_insert_buffers] } {
         lappend synth_fpga_args -insbuf
@@ -94,6 +102,8 @@ if { [string match {ice*} $sc_partname] } {
         -show_config \
         -top $sc_topmodule \
         {*}$synth_fpga_args
+} elseif { [string match {ice*} $sc_partname] } {
+    yosys synth_ice40 -top $sc_topmodule
 } else {
     set sc_syn_feature_set [sc_cfg_get library $sc_designlib tool yosys feature_set]
 

siliconcompiler/tools/yosys/syn_asic.py

@@ -2,6 +2,8 @@ import json
 
 import os.path
 
+from typing import Optional
+
 from siliconcompiler.tools.yosys.prepareLib import process_liberty_file
 from siliconcompiler import sc_open
 from siliconcompiler import utils
@@ -177,6 +179,21 @@ class ASICSynthesis(_ASICTask, YosysTask):
             "bool",
             "true/false, flag to indicate whether to add buffers or not.",
             True)
+        self.add_parameter(
+            "tie_undef",
+            "<high,low,none>",
+            "Flag to indicate how to handle undefined signals in netlist",
+            "low")
+        self.add_parameter(
+            "add_tieoffs",
+            "bool",
+            "true/false, flag to indicate add tie high and tie low cells.",
+            True)
+        self.add_parameter(
+            "opt_undriven",
+            "bool",
+            "true/false, flag to indicate if optimizations should mark undriven nets",
+            True)
 
         self.__init_techmapping_parameter()
         self.__init_hierarchy_parameter()
@@ -297,6 +314,26 @@ class ASICSynthesis(_ASICTask, YosysTask):
             "str",
             "lock locking port name")
 
+    def set_yosys_useslang(self, enable: bool,
+                           step: Optional[str] = None, index: Optional[str] = None):
+        self.set("var", "use_slang", enable, step=step, index=index)
+
+    def set_yosys_tieundefined(self, tie: str,
+                               step: Optional[str] = None, index: Optional[str] = None):
+        self.set("var", "tie_undef", tie, step=step, index=index)
+
+    def set_yosys_addtiecells(self, enable: bool,
+                              step: Optional[str] = None, index: Optional[str] = None):
+        self.set("var", "add_tieoffs", enable, step=step, index=index)
+
+    def set_yosys_addbuffers(self, enable: bool,
+                             step: Optional[str] = None, index: Optional[str] = None):
+        self.set("var", "add_buffers", enable, step=step, index=index)
+
+    def set_yosys_optundriven(self, enable: bool,
+                              step: Optional[str] = None, index: Optional[str] = None):
+        self.set("var", "opt_undriven", enable, step=step, index=index)
+
     def task(self):
         return "syn_asic"
 
@@ -374,6 +411,11 @@ class ASICSynthesis(_ASICTask, YosysTask):
         if self.get("var", "blackbox_modules"):
             self.add_required_key("var", "blackbox_modules")
 
+        self.add_required_key("var", "use_slang")
+        self.add_required_key("var", "add_buffers")
+        self.add_required_key("var", "tie_undef")
+        self.add_required_key("var", "add_tieoffs")
+        self.add_required_key("var", "opt_undriven")
         self.add_required_key("var", "flatten")
         self.add_required_key("var", "auto_flatten")
         self.add_required_key("var", "hier_threshold")

siliconcompiler/tools/yosys/syn_fpga.py

@@ -1,5 +1,7 @@
 import json
 
+from typing import Optional
+
 from siliconcompiler import sc_open
 
 from siliconcompiler.tools.yosys import YosysTask
@@ -26,6 +28,10 @@ class FPGASynthesis(YosysTask):
             "perform buffer insertion",
             True)
 
+    def set_yosys_useslang(self, enable: bool,
+                           step: Optional[str] = None, index: Optional[str] = None):
+        self.set("var", "use_slang", enable, step=step, index=index)
+
     def task(self):
         return "syn_fpga"
 
@@ -53,6 +59,8 @@ class FPGASynthesis(YosysTask):
         self.add_output_file(ext="netlist.json")
         self.add_output_file(ext="blif")
 
+        self.add_required_key("var", "use_slang")
+
     def post_process(self):
         super().post_process()