siliconcompiler 0.35.3__py3-none-any.whl → 0.35.4__py3-none-any.whl

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (68) hide show
  1. siliconcompiler/_metadata.py +1 -1
  2. siliconcompiler/apps/sc_issue.py +18 -2
  3. siliconcompiler/checklist.py +2 -1
  4. siliconcompiler/constraints/asic_component.py +49 -11
  5. siliconcompiler/constraints/asic_floorplan.py +23 -21
  6. siliconcompiler/constraints/asic_pins.py +55 -17
  7. siliconcompiler/constraints/asic_timing.py +53 -22
  8. siliconcompiler/constraints/fpga_timing.py +5 -6
  9. siliconcompiler/data/templates/replay/replay.sh.j2 +27 -14
  10. siliconcompiler/package/__init__.py +17 -6
  11. siliconcompiler/project.py +9 -1
  12. siliconcompiler/scheduler/docker.py +24 -25
  13. siliconcompiler/scheduler/scheduler.py +82 -68
  14. siliconcompiler/scheduler/schedulernode.py +133 -20
  15. siliconcompiler/scheduler/slurm.py +113 -29
  16. siliconcompiler/scheduler/taskscheduler.py +0 -7
  17. siliconcompiler/schema/editableschema.py +29 -0
  18. siliconcompiler/schema/parametervalue.py +14 -2
  19. siliconcompiler/schema_support/option.py +82 -1
  20. siliconcompiler/schema_support/pathschema.py +7 -13
  21. siliconcompiler/tool.py +47 -25
  22. siliconcompiler/tools/klayout/__init__.py +3 -0
  23. siliconcompiler/tools/klayout/scripts/klayout_convert_drc_db.py +1 -0
  24. siliconcompiler/tools/klayout/scripts/klayout_export.py +1 -0
  25. siliconcompiler/tools/klayout/scripts/klayout_operations.py +1 -0
  26. siliconcompiler/tools/klayout/scripts/klayout_show.py +1 -0
  27. siliconcompiler/tools/klayout/scripts/klayout_utils.py +3 -4
  28. siliconcompiler/tools/openroad/__init__.py +27 -1
  29. siliconcompiler/tools/openroad/_apr.py +81 -4
  30. siliconcompiler/tools/openroad/clock_tree_synthesis.py +1 -0
  31. siliconcompiler/tools/openroad/global_placement.py +1 -0
  32. siliconcompiler/tools/openroad/init_floorplan.py +116 -7
  33. siliconcompiler/tools/openroad/power_grid_analysis.py +174 -0
  34. siliconcompiler/tools/openroad/repair_design.py +1 -0
  35. siliconcompiler/tools/openroad/repair_timing.py +1 -0
  36. siliconcompiler/tools/openroad/scripts/apr/preamble.tcl +1 -1
  37. siliconcompiler/tools/openroad/scripts/apr/sc_init_floorplan.tcl +42 -4
  38. siliconcompiler/tools/openroad/scripts/apr/sc_irdrop.tcl +146 -0
  39. siliconcompiler/tools/openroad/scripts/apr/sc_repair_design.tcl +1 -1
  40. siliconcompiler/tools/openroad/scripts/apr/sc_write_data.tcl +4 -6
  41. siliconcompiler/tools/openroad/scripts/common/procs.tcl +1 -1
  42. siliconcompiler/tools/openroad/scripts/common/reports.tcl +1 -1
  43. siliconcompiler/tools/openroad/scripts/rcx/sc_rcx_bench.tcl +2 -4
  44. siliconcompiler/tools/opensta/__init__.py +1 -1
  45. siliconcompiler/tools/opensta/scripts/sc_timing.tcl +17 -12
  46. siliconcompiler/tools/vivado/scripts/sc_bitstream.tcl +11 -0
  47. siliconcompiler/tools/vivado/scripts/sc_place.tcl +11 -0
  48. siliconcompiler/tools/vivado/scripts/sc_route.tcl +11 -0
  49. siliconcompiler/tools/vivado/scripts/sc_syn_fpga.tcl +10 -0
  50. siliconcompiler/tools/vpr/__init__.py +28 -0
  51. siliconcompiler/tools/yosys/scripts/sc_screenshot.tcl +1 -1
  52. siliconcompiler/tools/yosys/scripts/sc_synth_asic.tcl +40 -4
  53. siliconcompiler/tools/yosys/scripts/sc_synth_fpga.tcl +15 -5
  54. siliconcompiler/tools/yosys/syn_asic.py +42 -0
  55. siliconcompiler/tools/yosys/syn_fpga.py +8 -0
  56. siliconcompiler/toolscripts/_tools.json +6 -6
  57. siliconcompiler/utils/__init__.py +243 -51
  58. siliconcompiler/utils/curation.py +89 -56
  59. siliconcompiler/utils/issue.py +6 -1
  60. siliconcompiler/utils/multiprocessing.py +35 -2
  61. siliconcompiler/utils/paths.py +21 -0
  62. siliconcompiler/utils/settings.py +141 -0
  63. {siliconcompiler-0.35.3.dist-info → siliconcompiler-0.35.4.dist-info}/METADATA +4 -3
  64. {siliconcompiler-0.35.3.dist-info → siliconcompiler-0.35.4.dist-info}/RECORD +68 -65
  65. {siliconcompiler-0.35.3.dist-info → siliconcompiler-0.35.4.dist-info}/WHEEL +0 -0
  66. {siliconcompiler-0.35.3.dist-info → siliconcompiler-0.35.4.dist-info}/entry_points.txt +0 -0
  67. {siliconcompiler-0.35.3.dist-info → siliconcompiler-0.35.4.dist-info}/licenses/LICENSE +0 -0
  68. {siliconcompiler-0.35.3.dist-info → siliconcompiler-0.35.4.dist-info}/top_level.txt +0 -0
@@ -1,5 +1,5 @@
1
1
  # Version number following semver standard.
2
- version = '0.35.3'
2
+ version = '0.35.4'
3
3
 
4
4
  # Default server address for remote runs, if unspecified.
5
5
  default_server = 'https://server.siliconcompiler.com'
@@ -72,6 +72,21 @@ To run a testcase, use:
72
72
  if not issue.get("cmdarg", "run"):
73
73
  project: Project = Project.from_manifest(filepath=issue.get("cmdarg", "cfg"))
74
74
 
75
+ # Determine abs path for build dir
76
+ builddir = project.option.get_builddir()
77
+ if isinstance(builddir, str) and not os.path.isabs(builddir):
78
+ builddirname = os.path.basename(builddir)
79
+ fullpath = os.path.dirname(os.path.abspath(issue.get("cmdarg", "cfg")))
80
+ while True:
81
+ if os.path.basename(fullpath) == builddirname:
82
+ project.option.set_builddir(fullpath)
83
+ break
84
+ parent = os.path.dirname(fullpath)
85
+ if parent == fullpath:
86
+ # Reached filesystem root without finding a match
87
+ break
88
+ fullpath = parent
89
+
75
90
  if issue.get("arg", "step"):
76
91
  project.set("arg", "step", issue.get("arg", "step"))
77
92
  if issue.get("arg", "index"):
@@ -143,8 +158,9 @@ To run a testcase, use:
143
158
 
144
159
  # Modify run environment to point to extracted files
145
160
  builddir_key = ['option', 'builddir']
146
- new_builddir = f"{test_dir}/{project.get(*builddir_key)}"
147
- project.logger.info(f"Changing {builddir_key} to '{new_builddir}'")
161
+ new_builddir = os.path.abspath(
162
+ os.path.join(test_dir, f"{os.path.basename(project.get(*builddir_key))}"))
163
+ project.logger.info(f"Changing [{','.join(builddir_key)}] to '{new_builddir}'")
148
164
  project.set(*builddir_key, new_builddir)
149
165
 
150
166
  # Run task
@@ -6,6 +6,7 @@ from typing import Tuple, List, Optional, Union, Dict, Iterable
6
6
  from siliconcompiler.schema import NamedSchema, EditableSchema, Parameter, Scope, BaseSchema
7
7
  from siliconcompiler.schema.utils import trim
8
8
  from siliconcompiler import NodeStatus, utils
9
+ from siliconcompiler.utils.paths import cwdirsafe
9
10
 
10
11
 
11
12
  class Criteria(NamedSchema):
@@ -328,7 +329,7 @@ class Checklist(NamedSchema):
328
329
 
329
330
  schema_root = self._parent(root=True)
330
331
  logger = getattr(schema_root, "logger", None)
331
- cwd = getattr(schema_root, "_Project__cwd", os.getcwd())
332
+ cwd = cwdirsafe(schema_root)
332
333
 
333
334
  assert hasattr(schema_root, "history"), f"{schema_root}"
334
335
 
@@ -1,4 +1,4 @@
1
- from typing import Tuple, Union
1
+ from typing import Tuple, Union, Optional
2
2
 
3
3
  from siliconcompiler.schema import BaseSchema, NamedSchema, EditableSchema, Parameter, \
4
4
  PerNode, Scope
@@ -13,7 +13,7 @@ class ASICComponentConstraint(NamedSchema):
13
13
  keepout halo, and rotation.
14
14
  """
15
15
 
16
- def __init__(self, name: str = None):
16
+ def __init__(self, name: Optional[str] = None):
17
17
  super().__init__()
18
18
  self.set_name(name)
19
19
 
@@ -113,7 +113,8 @@ class ASICComponentConstraint(NamedSchema):
113
113
  270 deg ccw
114
114
  """))
115
115
 
116
- def set_placement(self, x: float, y: float, step: str = None, index: Union[str, int] = None):
116
+ def set_placement(self, x: float, y: float,
117
+ step: Optional[str] = None, index: Optional[Union[str, int]] = None):
117
118
  """
118
119
  Sets the placement constraint for the component.
119
120
 
@@ -134,7 +135,8 @@ class ASICComponentConstraint(NamedSchema):
134
135
  raise TypeError("y must be a number")
135
136
  return self.set("placement", (x, y), step=step, index=index)
136
137
 
137
- def get_placement(self, step: str = None, index: Union[str, int] = None) -> Tuple[float, float]:
138
+ def get_placement(self, step: Optional[str] = None, index: Optional[Union[str, int]] = None) \
139
+ -> Tuple[float, float]:
138
140
  """
139
141
  Retrieves the current placement constraint of the component.
140
142
 
@@ -148,7 +150,8 @@ class ASICComponentConstraint(NamedSchema):
148
150
  """
149
151
  return self.get("placement", step=step, index=index)
150
152
 
151
- def set_partname(self, name: str, step: str = None, index: Union[str, int] = None):
153
+ def set_partname(self, name: str,
154
+ step: Optional[str] = None, index: Optional[Union[str, int]] = None):
152
155
  """
153
156
  Sets the part name (cell name) constraint for the component.
154
157
 
@@ -165,7 +168,8 @@ class ASICComponentConstraint(NamedSchema):
165
168
  raise ValueError("a partname is required")
166
169
  return self.set("partname", name, step=step, index=index)
167
170
 
168
- def get_partname(self, step: str = None, index: Union[str, int] = None) -> str:
171
+ def get_partname(self, step: Optional[str] = None, index: Optional[Union[str, int]] = None) \
172
+ -> str:
169
173
  """
170
174
  Retrieves the current part name (cell name) constraint of the component.
171
175
 
@@ -178,7 +182,8 @@ class ASICComponentConstraint(NamedSchema):
178
182
  """
179
183
  return self.get("partname", step=step, index=index)
180
184
 
181
- def set_halo(self, x: float, y: float, step: str = None, index: Union[str, int] = None):
185
+ def set_halo(self, x: float, y: float,
186
+ step: Optional[str] = None, index: Optional[Union[str, int]] = None):
182
187
  """
183
188
  Sets the placement keepout halo constraint around the component.
184
189
 
@@ -204,7 +209,8 @@ class ASICComponentConstraint(NamedSchema):
204
209
  raise ValueError("y must be a positive number")
205
210
  return self.set("halo", (x, y), step=step, index=index)
206
211
 
207
- def get_halo(self, step: str = None, index: Union[str, int] = None) -> Tuple[float, float]:
212
+ def get_halo(self, step: Optional[str] = None, index: Optional[Union[str, int]] = None) \
213
+ -> Tuple[float, float]:
208
214
  """
209
215
  Retrieves the current placement keepout halo constraint of the component.
210
216
 
@@ -218,7 +224,8 @@ class ASICComponentConstraint(NamedSchema):
218
224
  """
219
225
  return self.get("halo", step=step, index=index)
220
226
 
221
- def set_rotation(self, rotation: str, step: str = None, index: Union[str, int] = None):
227
+ def set_rotation(self, rotation: str,
228
+ step: Optional[str] = None, index: Optional[Union[str, int]] = None):
222
229
  """
223
230
  Sets the rotation constraint for the component.
224
231
 
@@ -231,7 +238,8 @@ class ASICComponentConstraint(NamedSchema):
231
238
  """
232
239
  return self.set("rotation", rotation, step=step, index=index)
233
240
 
234
- def get_rotation(self, step: str = None, index: Union[str, int] = None) -> str:
241
+ def get_rotation(self, step: Optional[str] = None, index: Optional[Union[str, int]] = None) \
242
+ -> str:
235
243
  """
236
244
  Retrieves the current rotation constraint of the component.
237
245
 
@@ -286,7 +294,7 @@ class ASICComponentConstraints(BaseSchema):
286
294
 
287
295
  EditableSchema(self).insert(component.name, component, clobber=True)
288
296
 
289
- def get_component(self, component: str = None):
297
+ def get_component(self, component: Optional[str] = None):
290
298
  """
291
299
  Retrieves one or all component constraints from the configuration.
292
300
 
@@ -350,6 +358,36 @@ class ASICComponentConstraints(BaseSchema):
350
358
  self.add_component(constraint)
351
359
  return constraint
352
360
 
361
+ def copy_component(self, component: str, name: str, insert: bool = True) \
362
+ -> ASICComponentConstraint:
363
+ """
364
+ Copies an existing component constraint, renames it, and optionally adds it to the design.
365
+
366
+ This method retrieves the component constraint identified by ``component``, creates a
367
+ deep copy of it, and renames the copy to ``name``. If ``insert`` is True,
368
+ the new constraint is immediately added to the configuration.
369
+
370
+ Args:
371
+ component (str): The name of the existing component constraint to be copied.
372
+ name (str): The name to assign to the new copied constraint.
373
+ insert (bool, optional): Whether to add the newly created constraint
374
+ to the configuration. Defaults to True.
375
+
376
+ Returns:
377
+ ASICComponentConstraint: The newly created copy of the component constraint.
378
+
379
+ Raises:
380
+ LookupError: If the source component constraint specified by ``component`` does not
381
+ exist.
382
+ """
383
+ constraint = EditableSchema(self.get_component(component)).copy()
384
+ EditableSchema(constraint).rename(name)
385
+ if insert:
386
+ if self.valid(name):
387
+ raise ValueError(f"{name} already exists")
388
+ self.add_component(constraint)
389
+ return constraint
390
+
353
391
  def remove_component(self, component: str) -> bool:
354
392
  """
355
393
  Removes a component constraint from the design configuration.
@@ -1,4 +1,4 @@
1
- from typing import Union, List, Tuple
1
+ from typing import Union, List, Tuple, Optional
2
2
 
3
3
  from siliconcompiler.schema import BaseSchema, EditableSchema, Parameter, PerNode, Scope
4
4
 
@@ -99,9 +99,9 @@ class ASICAreaConstraint(BaseSchema):
99
99
 
100
100
  def set_density(self,
101
101
  density: float,
102
- aspectratio: float = None,
103
- coremargin: float = None,
104
- step: str = None, index: Union[str, int] = None):
102
+ aspectratio: Optional[float] = None,
103
+ coremargin: Optional[float] = None,
104
+ step: Optional[str] = None, index: Optional[Union[str, int]] = None):
105
105
  """
106
106
  Sets the target layout density.
107
107
 
@@ -145,7 +145,8 @@ class ASICAreaConstraint(BaseSchema):
145
145
  params.append(self.set_coremargin(coremargin, step=step, index=index))
146
146
  return params
147
147
 
148
- def get_density(self, step: str = None, index: Union[str, int] = None) -> float:
148
+ def get_density(self, step: Optional[str] = None, index: Optional[Union[str, int]] = None) \
149
+ -> float:
149
150
  """
150
151
  Retrieves the current target layout density.
151
152
 
@@ -162,7 +163,7 @@ class ASICAreaConstraint(BaseSchema):
162
163
 
163
164
  def set_aspectratio(self,
164
165
  aspectratio: float,
165
- step: str = None, index: Union[str, int] = None):
166
+ step: Optional[str] = None, index: Optional[Union[str, int]] = None):
166
167
  """
167
168
  Sets the layout aspect ratio.
168
169
 
@@ -192,8 +193,8 @@ class ASICAreaConstraint(BaseSchema):
192
193
 
193
194
  return self.set("aspectratio", aspectratio, step=step, index=index)
194
195
 
195
- def get_aspectratio(self,
196
- step: str = None, index: Union[str, int] = None) -> float:
196
+ def get_aspectratio(self, step: Optional[str] = None, index: Optional[Union[str, int]] = None) \
197
+ -> float:
197
198
  """
198
199
  Retrieves the current layout aspect ratio.
199
200
 
@@ -210,7 +211,7 @@ class ASICAreaConstraint(BaseSchema):
210
211
 
211
212
  def set_coremargin(self,
212
213
  coremargin: float,
213
- step: str = None, index: Union[str, int] = None):
214
+ step: Optional[str] = None, index: Optional[Union[str, int]] = None):
214
215
  """
215
216
  Sets the core margin.
216
217
 
@@ -240,8 +241,8 @@ class ASICAreaConstraint(BaseSchema):
240
241
 
241
242
  return self.set("coremargin", coremargin, step=step, index=index)
242
243
 
243
- def get_coremargin(self,
244
- step: str = None, index: Union[str, int] = None) -> float:
244
+ def get_coremargin(self, step: Optional[str] = None, index: Optional[Union[str, int]] = None) \
245
+ -> float:
245
246
  """
246
247
  Retrieves the current core margin.
247
248
 
@@ -259,8 +260,8 @@ class ASICAreaConstraint(BaseSchema):
259
260
  def set_diearea_rectangle(self,
260
261
  height: float,
261
262
  width: float,
262
- coremargin: Union[float, Tuple[float, float]] = None,
263
- step: str = None, index: Union[str, int] = None):
263
+ coremargin: Optional[Union[float, Tuple[float, float]]] = None,
264
+ step: Optional[str] = None, index: Optional[Union[str, int]] = None):
264
265
  """
265
266
  Sets the die area as a rectangle with its bottom-left corner at (0,0).
266
267
 
@@ -311,7 +312,7 @@ class ASICAreaConstraint(BaseSchema):
311
312
  dieheight: float,
312
313
  diewidth: float,
313
314
  coremargin: Union[float, Tuple[float, float]],
314
- step: str = None, index: Union[str, int] = None):
315
+ step: Optional[str] = None, index: Optional[Union[str, int]] = None):
315
316
  """
316
317
  Sets the core area as a rectangle within a die area, based on margins.
317
318
 
@@ -378,7 +379,7 @@ class ASICAreaConstraint(BaseSchema):
378
379
 
379
380
  def set_diearea(self,
380
381
  points: List[Tuple[float, float]],
381
- step: str = None, index: Union[str, int] = None):
382
+ step: Optional[str] = None, index: Optional[Union[str, int]] = None):
382
383
  """
383
384
  Sets the die area using a list of points defining its boundary.
384
385
 
@@ -396,8 +397,8 @@ class ASICAreaConstraint(BaseSchema):
396
397
  """
397
398
  return self.set("diearea", points, step=step, index=index)
398
399
 
399
- def get_diearea(self,
400
- step: str = None, index: Union[str, int] = None) -> List[Tuple[float, float]]:
400
+ def get_diearea(self, step: Optional[str] = None, index: Optional[Union[str, int]] = None) \
401
+ -> List[Tuple[float, float]]:
401
402
  """
402
403
  Retrieves the current die area definition.
403
404
 
@@ -415,7 +416,7 @@ class ASICAreaConstraint(BaseSchema):
415
416
 
416
417
  def set_corearea(self,
417
418
  points: List[Tuple[float, float]],
418
- step: str = None, index: Union[str, int] = None):
419
+ step: Optional[str] = None, index: Optional[Union[str, int]] = None):
419
420
  """
420
421
  Sets the core area using a list of points defining its boundary.
421
422
 
@@ -432,8 +433,8 @@ class ASICAreaConstraint(BaseSchema):
432
433
  """
433
434
  return self.set("corearea", points, step=step, index=index)
434
435
 
435
- def get_corearea(self,
436
- step: str = None, index: Union[str, int] = None) -> List[Tuple[float, float]]:
436
+ def get_corearea(self, step: Optional[str] = None, index: Optional[Union[str, int]] = None) \
437
+ -> List[Tuple[float, float]]:
437
438
  """
438
439
  Retrieves the current core area definition.
439
440
 
@@ -449,7 +450,8 @@ class ASICAreaConstraint(BaseSchema):
449
450
  """
450
451
  return self.get("corearea", step=step, index=index)
451
452
 
452
- def calc_diearea(self, step: str = None, index: str = None) -> float:
453
+ def calc_diearea(self, step: Optional[str] = None, index: Optional[Union[str, int]] = None) \
454
+ -> float:
453
455
  '''Calculates the area of a rectilinear die.
454
456
 
455
457
  Uses the shoelace formula to calculate the design area from the (x,y)
@@ -1,4 +1,4 @@
1
- from typing import Union, Tuple
1
+ from typing import Union, Tuple, Optional
2
2
 
3
3
  from siliconcompiler.schema import BaseSchema, NamedSchema, EditableSchema, Parameter, \
4
4
  PerNode, Scope
@@ -13,7 +13,7 @@ class ASICPinConstraint(NamedSchema):
13
13
  metal layer, and its relative position on the chip's side.
14
14
  """
15
15
 
16
- def __init__(self, name: str = None):
16
+ def __init__(self, name: Optional[str] = None):
17
17
  super().__init__()
18
18
  self.set_name(name)
19
19
 
@@ -129,7 +129,8 @@ class ASICPinConstraint(NamedSchema):
129
129
  same order number, the actual order is at the discretion of the
130
130
  tool."""))
131
131
 
132
- def set_width(self, width: float, step: str = None, index: Union[str, int] = None):
132
+ def set_width(self, width: float,
133
+ step: Optional[str] = None, index: Optional[Union[str, int]] = None):
133
134
  """
134
135
  Sets the width constraint for the pin.
135
136
 
@@ -149,7 +150,8 @@ class ASICPinConstraint(NamedSchema):
149
150
  raise ValueError("width must be a positive value")
150
151
  return self.set("width", width, step=step, index=index)
151
152
 
152
- def get_width(self, step: str = None, index: Union[str, int] = None) -> float:
153
+ def get_width(self, step: Optional[str] = None, index: Optional[Union[str, int]] = None) \
154
+ -> float:
153
155
  """
154
156
  Retrieves the current width constraint of the pin.
155
157
 
@@ -162,7 +164,8 @@ class ASICPinConstraint(NamedSchema):
162
164
  """
163
165
  return self.get("width", step=step, index=index)
164
166
 
165
- def set_length(self, length: float, step: str = None, index: Union[str, int] = None):
167
+ def set_length(self, length: float,
168
+ step: Optional[str] = None, index: Optional[Union[str, int]] = None):
166
169
  """
167
170
  Sets the length constraint for the pin.
168
171
 
@@ -182,7 +185,8 @@ class ASICPinConstraint(NamedSchema):
182
185
  raise ValueError("length must be a positive value")
183
186
  return self.set("length", length, step=step, index=index)
184
187
 
185
- def get_length(self, step: str = None, index: Union[str, int] = None) -> float:
188
+ def get_length(self, step: Optional[str] = None, index: Optional[Union[str, int]] = None) \
189
+ -> float:
186
190
  """
187
191
  Retrieves the current length constraint of the pin.
188
192
 
@@ -195,7 +199,8 @@ class ASICPinConstraint(NamedSchema):
195
199
  """
196
200
  return self.get("length", step=step, index=index)
197
201
 
198
- def set_placement(self, x: float, y: float, step: str = None, index: Union[str, int] = None):
202
+ def set_placement(self, x: float, y: float,
203
+ step: Optional[str] = None, index: Optional[Union[str, int]] = None):
199
204
  """
200
205
  Sets the placement constraint for the pin.
201
206
 
@@ -216,7 +221,8 @@ class ASICPinConstraint(NamedSchema):
216
221
  raise TypeError("y must be a number")
217
222
  return self.set("placement", (x, y), step=step, index=index)
218
223
 
219
- def get_placement(self, step: str = None, index: Union[str, int] = None) -> Tuple[float, float]:
224
+ def get_placement(self, step: Optional[str] = None, index: Optional[Union[str, int]] = None) \
225
+ -> Tuple[float, float]:
220
226
  """
221
227
  Retrieves the current placement constraint of the pin.
222
228
 
@@ -230,7 +236,8 @@ class ASICPinConstraint(NamedSchema):
230
236
  """
231
237
  return self.get("placement", step=step, index=index)
232
238
 
233
- def set_shape(self, shape: str, step: str = None, index: Union[str, int] = None):
239
+ def set_shape(self, shape: str,
240
+ step: Optional[str] = None, index: Optional[Union[str, int]] = None):
234
241
  """
235
242
  Sets the shape constraint for the pin.
236
243
 
@@ -243,7 +250,7 @@ class ASICPinConstraint(NamedSchema):
243
250
  """
244
251
  return self.set("shape", shape, step=step, index=index)
245
252
 
246
- def get_shape(self, step: str = None, index: Union[str, int] = None) -> str:
253
+ def get_shape(self, step: Optional[str] = None, index: Optional[Union[str, int]] = None) -> str:
247
254
  """
248
255
  Retrieves the current shape constraint of the pin.
249
256
 
@@ -256,7 +263,8 @@ class ASICPinConstraint(NamedSchema):
256
263
  """
257
264
  return self.get("shape", step=step, index=index)
258
265
 
259
- def set_layer(self, layer: str, step: str = None, index: Union[str, int] = None):
266
+ def set_layer(self, layer: str,
267
+ step: Optional[str] = None, index: Optional[Union[str, int]] = None):
260
268
  """
261
269
  Sets the metal layer constraint for the pin.
262
270
 
@@ -269,7 +277,7 @@ class ASICPinConstraint(NamedSchema):
269
277
  """
270
278
  return self.set("layer", layer, step=step, index=index)
271
279
 
272
- def get_layer(self, step: str = None, index: Union[str, int] = None) -> str:
280
+ def get_layer(self, step: Optional[str] = None, index: Optional[Union[str, int]] = None) -> str:
273
281
  """
274
282
  Retrieves the current metal layer constraint of the pin.
275
283
 
@@ -282,7 +290,8 @@ class ASICPinConstraint(NamedSchema):
282
290
  """
283
291
  return self.get("layer", step=step, index=index)
284
292
 
285
- def set_side(self, side: Union[int, str], step: str = None, index: Union[str, int] = None):
293
+ def set_side(self, side: Union[int, str],
294
+ step: Optional[str] = None, index: Optional[Union[str, int]] = None):
286
295
  """
287
296
  Sets the side constraint for the pin, indicating where it should be placed.
288
297
 
@@ -318,7 +327,7 @@ class ASICPinConstraint(NamedSchema):
318
327
 
319
328
  return self.set("side", side, step=step, index=index)
320
329
 
321
- def get_side(self, step: str = None, index: Union[str, int] = None) -> int:
330
+ def get_side(self, step: Optional[str] = None, index: Optional[Union[str, int]] = None) -> int:
322
331
  """
323
332
  Retrieves the current side constraint of the pin.
324
333
 
@@ -331,7 +340,8 @@ class ASICPinConstraint(NamedSchema):
331
340
  """
332
341
  return self.get("side", step=step, index=index)
333
342
 
334
- def set_order(self, order: int, step: str = None, index: Union[str, int] = None):
343
+ def set_order(self, order: int,
344
+ step: Optional[str] = None, index: Optional[Union[str, int]] = None):
335
345
  """
336
346
  Sets the relative order constraint for the pin on its assigned side.
337
347
 
@@ -343,7 +353,7 @@ class ASICPinConstraint(NamedSchema):
343
353
  """
344
354
  return self.set("order", order, step=step, index=index)
345
355
 
346
- def get_order(self, step: str = None, index: Union[str, int] = None) -> int:
356
+ def get_order(self, step: Optional[str] = None, index: Optional[Union[str, int]] = None) -> int:
347
357
  """
348
358
  Retrieves the current order constraint of the pin.
349
359
 
@@ -398,7 +408,7 @@ class ASICPinConstraints(BaseSchema):
398
408
 
399
409
  EditableSchema(self).insert(pin.name, pin, clobber=True)
400
410
 
401
- def get_pinconstraint(self, pin: str = None):
411
+ def get_pinconstraint(self, pin: Optional[str] = None):
402
412
  """
403
413
  Retrieves one or all pin constraints from the configuration.
404
414
 
@@ -461,6 +471,34 @@ class ASICPinConstraints(BaseSchema):
461
471
  self.add_pinconstraint(constraint)
462
472
  return constraint
463
473
 
474
+ def copy_pinconstraint(self, pin: str, name: str, insert: bool = True) -> ASICPinConstraint:
475
+ """
476
+ Copies an existing pin constraint, renames it, and optionally adds it to the design.
477
+
478
+ This method retrieves the pin constraint identified by ``pin``, creates a
479
+ deep copy of it, and renames the copy to ``name``. If ``insert`` is True,
480
+ the new constraint is immediately added to the configuration.
481
+
482
+ Args:
483
+ pin (str): The name of the existing pin constraint to be copied.
484
+ name (str): The name to assign to the new copied constraint.
485
+ insert (bool, optional): Whether to add the newly created constraint
486
+ to the configuration. Defaults to True.
487
+
488
+ Returns:
489
+ ASICPinConstraint: The newly created copy of the pin constraint.
490
+
491
+ Raises:
492
+ LookupError: If the source pin constraint specified by ``pin`` does not exist.
493
+ """
494
+ constraint = EditableSchema(self.get_pinconstraint(pin)).copy()
495
+ EditableSchema(constraint).rename(name)
496
+ if insert:
497
+ if self.valid(name):
498
+ raise ValueError(f"{name} already exists")
499
+ self.add_pinconstraint(constraint)
500
+ return constraint
501
+
464
502
  def remove_pinconstraint(self, pin: str) -> bool:
465
503
  """
466
504
  Removes a pin constraint from the design configuration.