siliconcompiler 0.34.2__py3-none-any.whl → 0.34.3__py3-none-any.whl

siliconcompiler/tools/vivado/syn_fpga.py

@@ -19,6 +19,12 @@ def setup(chip):
     chip.add('tool', tool, 'task', task, 'output', f'{design}.vg',
              step=step, index=index)
 
+    chip.set('tool', tool, 'task', task, 'var', 'synth_directive', 'Default',
+             step=step, index=index, clobber=False)
+
+    chip.set('tool', tool, 'task', task, 'var', 'synth_mode', 'none',
+             step=step, index=index, clobber=False)
+
 
 def post_process(chip):
     vivado.post_process(chip)

siliconcompiler/tools/vivado/vivado.py

@@ -11,6 +11,7 @@ import re
 from siliconcompiler import utils
 from siliconcompiler import sc_open
 from siliconcompiler.tools._common import record_metric
+from siliconcompiler.tools._common import get_tool_task
 
 
 def make_docs(chip):
@@ -57,6 +58,9 @@ def setup_task(chip, task):
     chip.set('tool', tool, 'task', task, 'regex', 'warnings', r'^(CRITICAL )?WARNING:',
              step=step, index=index, clobber=False)
 
+    chip.set('tool', tool, 'task', task, 'var', 'metric_luts', 'true',
+             step=step, index=index, clobber=False)
+
 
 def parse_version(stdout):
     # Vivado v2021.2 (64-bit)
@@ -121,9 +125,22 @@ def _parse_utilization(chip, step, index):
     if not os.path.isfile('reports/total_utilization.rpt'):
         return
 
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
     with sc_open('reports/total_utilization.rpt') as f:
         regexes = {
             'luts': (re.compile(r'(?:CLB|Slice) LUTs\*?\s+\|\s+(\d+)'), int),
+            'lut6': (re.compile(r'LUT6\*?\s+\|\s+(\d+)'), int),
+            'lut5': (re.compile(r'LUT5\*?\s+\|\s+(\d+)'), int),
+            'lut4': (re.compile(r'LUT4\*?\s+\|\s+(\d+)'), int),
+            'lut3': (re.compile(r'LUT3\*?\s+\|\s+(\d+)'), int),
+            'lut2': (re.compile(r'LUT2\*?\s+\|\s+(\d+)'), int),
+            'lut1': (re.compile(r'LUT1\*?\s+\|\s+(\d+)'), int),
+            'f7mux': (re.compile(r'MUXF7\*?\s+\|\s+(\d+)'), int),
+            'f8mux': (re.compile(r'MUXF8\*?\s+\|\s+(\d+)'), int),
+            'dsps': (re.compile(r'DSPs\*?\s+\|\s+(\d+)'), int),
             'regs': (re.compile(r'(?:CLB|Slice) Registers\s+\|\s+(\d+)'), int),
             'bram': (re.compile(r'Block RAM Tile\s+\|\s+(\d+(.\d+)?)'), float),
             # TODO: should URAM be float?
@@ -140,8 +157,20 @@ def _parse_utilization(chip, step, index):
                     vals[metric] = datatype(match.group(1))
                     continue
 
-        if 'luts' in vals:
-            record_metric(chip, step, index, 'luts', vals['luts'],
+        lut_cnt = 0
+        if chip.get('tool', tool, 'task', task, 'var', 'metric_luts', step=step, index=index)[0] \
+                == 'true':
+            lut_cnt = vals.get('luts', 0)
+        else:
+            lut_cnt = sum([cnt for name, cnt in vals.items() if name.startswith('lut')])
+            lut_cnt -= vals.get('luts', 0)  # avoid double counting
+            if "f7mux" in vals:
+                lut_cnt += vals["f7mux"]
+            if "f8mux" in vals:
+                lut_cnt -= vals["f8mux"]
+
+        if lut_cnt != 0:
+            record_metric(chip, step, index, 'luts', lut_cnt,
                           'reports/total_utilization.rpt')
         if 'regs' in vals:
             record_metric(chip, step, index, 'registers', vals['regs'],
@@ -156,6 +185,10 @@ def _parse_utilization(chip, step, index):
             record_metric(chip, step, index, 'brams', total_bram,
                           'reports/total_utilization.rpt')
 
+        if 'dsps' in vals:
+            record_metric(chip, step, index, 'dsps', vals['dsps'],
+                          'reports/total_utilization.rpt')
+
 
 def post_process(chip):
     step = chip.get('arg', 'step')

siliconcompiler/tools/vpr/__init__.py

@@ -0,0 +1,150 @@
+from typing import List, Union
+
+from siliconcompiler import FPGASchema
+
+
+class VPRFPGA(FPGASchema):
+    """
+    Schema for defining library parameters specifically for the
+    VPR (Verilog Place and Route) tool.
+
+    This class extends the base FPGASchema to manage various settings
+    related to VPR, such as device information, channel width, resource types,
+    and input file paths for the architecture and routing graph.
+    """
+    def __init__(self):
+        super().__init__()
+
+        self.define_tool_parameter("vpr", "devicecode", "str",
+                                   "The name or code for the target FPGA device.")
+        self.define_tool_parameter("vpr", "channelwidth", "int",
+                                   "The channel width to be used during routing.")
+
+        self.define_tool_parameter("vpr", "registers", "{str}",
+                                   "A set of supported register types.")
+        self.define_tool_parameter("vpr", "brams", "{str}",
+                                   "A set of supported block RAM types.")
+        self.define_tool_parameter("vpr", "dsps", "{str}",
+                                   "A set of supported DSP types.")
+
+        self.define_tool_parameter("vpr", "archfile", "file",
+                                   "The path to the VPR architecture description file.")
+        self.define_tool_parameter("vpr", "graphfile", "file",
+                                   "The path to the VPR routing graph file.")
+        self.define_tool_parameter("vpr", "constraintsmap", "file",
+                                   "The path to the VPR constraints map file.")
+
+        self.define_tool_parameter("vpr", "clock_model", "<ideal,route,dedicated_network>",
+                                   "The clock modeling strategy to be used.")
+
+    def set_vpr_devicecode(self, name: str):
+        """
+        Sets the device code for VPR.
+
+        Args:
+            name (str): The name or code of the device.
+        """
+        return self.set("tool", "vpr", "devicecode", name)
+
+    def set_vpr_channelwidth(self, width: int):
+        """
+        Sets the channel width for VPR routing.
+
+        Args:
+            width (int): The channel width value.
+        """
+        return self.set("tool", "vpr", "channelwidth", width)
+
+    def add_vpr_registertype(self, name: Union[str, List[str]] = None, clobber: bool = False):
+        """
+        Adds one or more register types to the list of supported registers.
+
+        Args:
+            name (Union[str, List[str]], optional): The register type or a list of types.
+                                                    Defaults to None.
+            clobber (bool, optional): If True, overwrites the existing list.
+                                      If False, adds to the list. Defaults to False.
+        """
+        if clobber:
+            return self.set("tool", "vpr", "registers", name)
+        else:
+            return self.add("tool", "vpr", "registers", name)
+
+    def add_vpr_bramtype(self, name: Union[str, List[str]] = None, clobber: bool = False):
+        """
+        Adds one or more block RAM types to the list of supported BRAMs.
+
+        Args:
+            name (Union[str, List[str]], optional): The BRAM type or a list of types.
+                                                    Defaults to None.
+            clobber (bool, optional): If True, overwrites the existing list.
+                                      If False, adds to the list. Defaults to False.
+        """
+        if clobber:
+            return self.set("tool", "vpr", "brams", name)
+        else:
+            return self.add("tool", "vpr", "brams", name)
+
+    def add_vpr_dsptype(self, name: Union[str, List[str]] = None, clobber: bool = False):
+        """
+        Adds one or more DSP types to the list of supported DSPs.
+
+        Args:
+            name (Union[str, List[str]], optional): The DSP type or a list of types.
+                                                    Defaults to None.
+            clobber (bool, optional): If True, overwrites the existing list.
+                                      If False, adds to the list. Defaults to False.
+        """
+        if clobber:
+            return self.set("tool", "vpr", "dsps", name)
+        else:
+            return self.add("tool", "vpr", "dsps", name)
+
+    def set_vpr_archfile(self, file: str, dataroot: str = None):
+        """
+        Sets the path to the VPR architecture file.
+
+        Args:
+            file (str): The path to the architecture file.
+            dataroot (str, optional): The data root directory. Defaults to the active package.
+        """
+        if not dataroot:
+            dataroot = self._get_active("package")
+        with self.active_dataroot(dataroot):
+            return self.set("tool", "vpr", "archfile", file)
+
+    def set_vpr_graphfile(self, file: str, dataroot: str = None):
+        """
+        Sets the path to the VPR routing graph file.
+
+        Args:
+            file (str): The path to the routing graph file.
+            dataroot (str, optional): The data root directory. Defaults to the active package.
+        """
+        if not dataroot:
+            dataroot = self._get_active("package")
+        with self.active_dataroot(dataroot):
+            return self.set("tool", "vpr", "graphfile", file)
+
+    def set_vpr_constraintsmap(self, file: str, dataroot: str = None):
+        """
+        Sets the path to the VPR constraints map file.
+
+        Args:
+            file (str): The path to the constraints map file.
+            dataroot (str, optional): The data root directory. Defaults to the active package.
+        """
+        if not dataroot:
+            dataroot = self._get_active("package")
+        with self.active_dataroot(dataroot):
+            return self.set("tool", "vpr", "constraintsmap", file)
+
+    def set_vpr_clockmodel(self, model: str):
+        """
+        Sets the clock modeling strategy.
+
+        Args:
+            model (str): The name of the clock model to use
+                         (e.g., 'ideal', 'route', or 'dedicated_network').
+        """
+        return self.set("tool", "vpr", "clock_model", model)

siliconcompiler/tools/yosys/__init__.py

@@ -12,12 +12,380 @@ Sources: https://github.com/YosysHQ/yosys
 
 Installation: https://github.com/YosysHQ/yosys
 '''
+import json
 import os
 import re
-import json
+
+from typing import List, Union
+
 from siliconcompiler import sc_open
 from siliconcompiler.tools._common import get_tool_task, record_metric
 
+from siliconcompiler import StdCellLibrarySchema
+from siliconcompiler import FPGASchema
+
+
+class YosysStdCellLibrary(StdCellLibrarySchema):
+    """
+    Schema for a standard cell library specifically for the Yosys tool.
+
+    This class extends the base StdCellLibrarySchema to define and manage
+    a variety of tool-specific parameters required by Yosys for synthesis
+    and technology mapping.
+    """
+    def __init__(self):
+        super().__init__()
+
+        self.define_tool_parameter("yosys", "abc_clock_multiplier", "float",
+                                   "Scalar factor to convert timing from library units to ns "
+                                   "for ABC.")
+        self.define_tool_parameter("yosys", "abc_constraint_load", "float",
+                                   "The load constraint for the ABC tool", unit="fF")
+
+        self.define_tool_parameter("yosys", "driver_cell", "str",
+                                   "The name of the driver cell to be used.")
+        self.define_tool_parameter("yosys", "buffer_cell", "(str,str,str)",
+                                   "A tuple specifying the buffer cell name, its input port, and "
+                                   "its output port.")
+        self.define_tool_parameter("yosys", "tiehigh_cell", "(str,str)",
+                                   "A tuple specifying the tie-high cell name and its output port.")
+        self.define_tool_parameter("yosys", "tielow_cell", "(str,str)",
+                                   "A tuple specifying the tie-low cell name and its output port.")
+
+        self.define_tool_parameter("yosys", "techmap", "[file]",
+                                   "A list of technology map files to be used by Yosys.")
+        self.define_tool_parameter("yosys", "tristatebuffermap",
+                                   "file", "The file to be used for tristate buffer mapping.")
+        self.define_tool_parameter("yosys", "addermap", "file",
+                                   "The file to be used for adder mapping.")
+
+        self.define_tool_parameter("yosys", "synthesis_fileset", "[str]",
+                                   "name of the filesets to use for yosys synthesis")
+        self.define_tool_parameter("yosys", "blackbox_fileset", "[str]",
+                                   "A list of fileset names that contain blackbox definitions.")
+
+    def set_yosys_driver_cell(self, cell: str):
+        """
+        Sets the driver cell for Yosys synthesis.
+
+        Args:
+            cell (str): The name of the driver cell.
+        """
+        self.set("tool", "yosys", "driver_cell", cell)
+
+    def set_yosys_buffer_cell(self, cell: str, input_port: str, output_port: str):
+        """
+        Sets the buffer cell and its corresponding input and output ports.
+
+        Args:
+            cell (str): The name of the buffer cell.
+            input_port (str): The name of the input port.
+            output_port (str): The name of the output port.
+        """
+        self.set("tool", "yosys", "buffer_cell", (cell, input_port, output_port))
+
+    def set_yosys_tiehigh_cell(self, cell: str, output_port: str):
+        """
+        Sets the tie-high cell and its output port.
+
+        Args:
+            cell (str): The name of the tie-high cell.
+            output_port (str): The name of the output port.
+        """
+        self.set("tool", "yosys", "tiehigh_cell", (cell, output_port))
+
+    def set_yosys_tielow_cell(self, cell: str, output_port: str):
+        """
+        Sets the tie-low cell and its output port.
+
+        Args:
+            cell (str): The name of the tie-low cell.
+            output_port (str): The name of the output port.
+        """
+        self.set("tool", "yosys", "tielow_cell", (cell, output_port))
+
+    def set_yosys_abc(self, clock_multiplier: float, load: float):
+        """
+        Sets the clock multiplier and load constraints for the Yosys ABC tool.
+
+        Args:
+            clock_multiplier (float): The scalar clock multiplier.
+            load (float): The constraint load in fF.
+        """
+        self.set("tool", "yosys", "abc_clock_multiplier", clock_multiplier)
+        self.set("tool", "yosys", "abc_constraint_load", load)
+
+    def set_yosys_tristatebuffer_map(self, map: str, dataroot: str = None):
+        """
+        Sets the file path for the tristate buffer mapping.
+
+        Args:
+            map (str): The file path for the mapping.
+            dataroot (str, optional): The data root directory. Defaults to the active package.
+        """
+        if not dataroot:
+            dataroot = self._get_active("package")
+        with self.active_dataroot(dataroot):
+            self.set("tool", "yosys", "tristatebuffermap", map)
+
+    def set_yosys_adder_map(self, map: str, dataroot: str = None):
+        """
+        Sets the file path for the adder mapping.
+
+        Args:
+            map (str): The file path for the mapping.
+            dataroot (str, optional): The data root directory. Defaults to the active package.
+        """
+        if not dataroot:
+            dataroot = self._get_active("package")
+        with self.active_dataroot(dataroot):
+            self.set("tool", "yosys", "addermap", map)
+
+    def add_yosys_tech_map(self,
+                           map: Union[str, List[str]],
+                           dataroot: str = None,
+                           clobber: bool = False):
+        """
+        Adds a technology map file to the list of maps.
+
+        Args:
+            map (Union[str, List[str]]): The file path or a list of file paths for the technology
+                                         map.
+            dataroot (str, optional): The data root directory. Defaults to the active package.
+            clobber (bool, optional): If True, replaces the current value. Defaults to False.
+        """
+        if not dataroot:
+            dataroot = self._get_active("package")
+        with self.active_dataroot(dataroot):
+            if clobber:
+                self.set("tool", "yosys", "techmap", map)
+            else:
+                self.add("tool", "yosys", "techmap", map)
+
+    def add_yosys_synthesis_fileset(self, fileset: Union[str, List[str]], clobber: bool = False):
+        """
+        Adds a fileset name to the list of synthesis filesets.
+
+        Args:
+            fileset (Union[str, List[str]]): The name of the fileset or a list of fileset names.
+            clobber (bool, optional): If True, replaces the current value. Defaults to False.
+        """
+        if clobber:
+            self.set("tool", "yosys", "synthesis_fileset", fileset)
+        else:
+            self.add("tool", "yosys", "synthesis_fileset", fileset)
+
+    def add_yosys_blackbox_fileset(self, fileset: Union[str, List[str]], clobber: bool = False):
+        """
+        Adds a fileset name to the list of blackbox filesets.
+
+        Args:
+            fileset (Union[str, List[str]]): The name of the fileset or a list of fileset names.
+            clobber (bool, optional): If True, replaces the current value. Defaults to False.
+        """
+        if clobber:
+            self.set("tool", "yosys", "blackbox_fileset", fileset)
+        else:
+            self.add("tool", "yosys", "blackbox_fileset", fileset)
+
+
+class YosysFPGA(FPGASchema):
+    """
+    Schema for defining FPGA-specific parameters for the Yosys tool.
+
+    This class extends the base FPGASchema to manage various configurations
+    and technology-specific files required for synthesizing designs onto
+    an FPGA using Yosys, including macro libraries, technology maps, and
+    feature sets.
+    """
+    def __init__(self):
+        super().__init__()
+
+        self.define_tool_parameter("yosys", "fpga_config", "file",
+                                   "The main configuration file for the target FPGA.")
+        self.define_tool_parameter("yosys", "macrolib", "[file]",
+                                   "A list of macro library files to be used.")
+        self.define_tool_parameter("yosys", "extractlib", "[file]",
+                                   "A list of files used to extract a macro library.")
+        self.define_tool_parameter("yosys", "dsp_techmap", "file",
+                                   "The technology map file for DSP blocks.")
+        self.define_tool_parameter("yosys", "dsp_options", "{str}",
+                                   "A list of synthesis options for DSP blocks.")
+        self.define_tool_parameter("yosys", "memory_libmap", "file",
+                                   "The library map file for memory elements.")
+        self.define_tool_parameter("yosys", "memory_techmap", "file",
+                                   "The technology map file for memory elements.")
+        self.define_tool_parameter("yosys", "flop_techmap", "file",
+                                   "The technology map file for flip-flop elements.")
+        self.define_tool_parameter("yosys", "feature_set",
+                                   "{<mem_init,enable,async_reset,async_set>}",
+                                   "The set of supported features for the FPGA.")
+
+        self.define_tool_parameter("yosys", "registers", "{str}",
+                                   "A list of supported register types.")
+        self.define_tool_parameter("yosys", "brams", "{str}",
+                                   "A list of supported block RAM types.")
+        self.define_tool_parameter("yosys", "dsps", "{str}",
+                                   "A list of supported DSP types.")
+
+    def set_yosys_config(self, file: str, dataroot: str = None):
+        """
+        Sets the main FPGA configuration file.
+
+        Args:
+            file (str): The path to the configuration file.
+            dataroot (str, optional): The data root directory. Defaults to the active package.
+        """
+        if not dataroot:
+            dataroot = self._get_active("package")
+        with self.active_dataroot(dataroot):
+            return self.set("tool", "yosys", "fpga_config", file)
+
+    def add_yosys_macrolib(self, file: Union[str, List[str]], dataroot: str = None,
+                           clobber: bool = False):
+        """
+        Adds a macro library file.
+
+        Args:
+            file (Union[str, List[str]]): The path to the macro library file or a list of paths.
+            dataroot (str, optional): The data root directory. Defaults to the active package.
+            clobber (bool, optional): If True, overwrites the existing list with the new file(s).
+                                      If False, appends the file(s) to the list. Defaults to False.
+        """
+        if not dataroot:
+            dataroot = self._get_active("package")
+        with self.active_dataroot(dataroot):
+            if clobber:
+                return self.set("tool", "yosys", "macrolib", file)
+            else:
+                return self.add("tool", "yosys", "macrolib", file)
+
+    def add_yosys_extractlib(self, file: Union[str, List[str]], dataroot: str = None,
+                             clobber: bool = False):
+        """
+        Adds a file used to extract a macro library.
+
+        Args:
+            file (Union[str, List[str]]): The path to the extraction file or a list of paths.
+            dataroot (str, optional): The data root directory. Defaults to the active package.
+            clobber (bool, optional): If True, overwrites the existing list with the new file(s).
+                                      If False, appends the file(s) to the list. Defaults to False.
+        """
+        if not dataroot:
+            dataroot = self._get_active("package")
+        with self.active_dataroot(dataroot):
+            if clobber:
+                return self.set("tool", "yosys", "extractlib", file)
+            else:
+                return self.add("tool", "yosys", "extractlib", file)
+
+    def set_yosys_dsptechmap(self, file: str, options: List[str] = None, dataroot: str = None):
+        """
+        Sets the technology map file and optional synthesis options for DSP blocks.
+
+        Args:
+            file (str): The path to the DSP technology map file.
+            options (List[str], optional): A list of synthesis options for DSP blocks.
+                Defaults to None.
+            dataroot (str, optional): The data root directory. Defaults to the active package.
+        """
+        if not dataroot:
+            dataroot = self._get_active("package")
+        with self.active_dataroot(dataroot):
+            self.set("tool", "yosys", "dsp_techmap", file)
+        if options:
+            self.set("tool", "yosys", "dsp_options", options)
+
+    def set_yosys_memorymap(self, libmap: str = None, techmap: str = None, dataroot: str = None):
+        """
+        Sets the library and technology map files for memory elements.
+
+        Args:
+            libmap (str, optional): The path to the memory library map file. Defaults to None.
+            techmap (str, optional): The path to the memory technology map file. Defaults to None.
+            dataroot (str, optional): The data root directory. Defaults to the active package.
+        """
+        if not dataroot:
+            dataroot = self._get_active("package")
+        with self.active_dataroot(dataroot):
+            if libmap:
+                self.set("tool", "yosys", "memory_libmap", libmap)
+            if techmap:
+                self.set("tool", "yosys", "memory_techmap", techmap)
+
+    def set_yosys_flipfloptechmap(self, file: str = None, dataroot: str = None):
+        """
+        Sets the technology map file for flip-flops.
+
+        Args:
+            file (str, optional): The path to the flip-flop technology map file. Defaults to None.
+            dataroot (str, optional): The data root directory. Defaults to the active package.
+        """
+        if not dataroot:
+            dataroot = self._get_active("package")
+        with self.active_dataroot(dataroot):
+            return self.set("tool", "yosys", "flop_techmap", file)
+
+    def add_yosys_featureset(self, feature: Union[str, List[str]] = None, clobber: bool = False):
+        """
+        Adds a feature to the feature set.
+
+        Args:
+            feature (Union[str, List[str]], optional): The name of the feature or a list of feature
+                                                       names to add. Defaults to None.
+            clobber (bool, optional): If True, overwrites the existing set with the new feature(s).
+                                      If False, adds the feature(s) to the set. Defaults to False.
+        """
+        if clobber:
+            return self.set("tool", "yosys", "feature_set", feature)
+        else:
+            return self.add("tool", "yosys", "feature_set", feature)
+
+    def add_yosys_registertype(self, name: Union[str, List[str]] = None, clobber: bool = False):
+        """
+        Adds a register type to the list of supported registers.
+
+        Args:
+            name (Union[str, List[str]], optional): The name of the register type or a list
+                                                    of types. Defaults to None.
+            clobber (bool, optional): If True, overwrites the existing list with the new type(s).
+                                      If False, adds the type(s) to the list. Defaults to False.
+        """
+        if clobber:
+            return self.set("tool", "yosys", "registers", name)
+        else:
+            return self.add("tool", "yosys", "registers", name)
+
+    def add_yosys_bramtype(self, name: Union[str, List[str]] = None, clobber: bool = False):
+        """
+        Adds a block RAM type to the list of supported BRAMs.
+
+        Args:
+            name (Union[str, List[str]], optional): The name of the BRAM type or a list of types.
+                                                    Defaults to None.
+            clobber (bool, optional): If True, overwrites the existing list with the new type(s).
+                                      If False, adds the type(s) to the list. Defaults to False.
+        """
+        if clobber:
+            return self.set("tool", "yosys", "brams", name)
+        else:
+            return self.add("tool", "yosys", "brams", name)
+
+    def add_yosys_dsptype(self, name: Union[str, List[str]] = None, clobber: bool = False):
+        """
+        Adds a DSP type to the list of supported DSPs.
+
+        Args:
+            name (Union[str, List[str]], optional): The name of the DSP type or a list of types.
+                                                    Defaults to None.
+            clobber (bool, optional): If True, overwrites the existing list with the new type(s).
+                                      If False, adds the type(s) to the list. Defaults to False.
+        """
+        if clobber:
+            return self.set("tool", "yosys", "dsps", name)
+        else:
+            return self.add("tool", "yosys", "dsps", name)
+
 
 ######################################################################
 # Make Docs

siliconcompiler/tools/yosys/scripts/procs.tcl

@@ -123,7 +123,6 @@ proc sc_fpga_legalize_flops { feature_set } {
         # won't tech map.  Goal is to get the user to fix
         # their code and put in synchronous resets
         lappend legalize_flop_types \$_DFF_P_
-        lappend legalize_flop_types \$_DFF_P??_
     }
 
     set legalize_list []