siliconcompiler 0.32.2__py3-none-any.whl → 0.33.0__py3-none-any.whl

siliconcompiler/tools/yosys/sc_synth_asic.tcl

@@ -32,43 +32,119 @@ set sc_pdk [sc_cfg_get option pdk]
 
 source "$sc_refdir/procs.tcl"
 
+####################
+# DESIGNER's CHOICE
+####################
+
+set sc_logiclibs [sc_get_asic_libraries logic]
+set sc_macrolibs [sc_get_asic_libraries macro]
+
+set sc_libraries [sc_cfg_tool_task_get {file} synthesis_libraries]
+if { [sc_cfg_tool_task_exists {file} synthesis_libraries_macros] } {
+    set sc_macro_libraries \
+        [sc_cfg_tool_task_get {file} synthesis_libraries_macros]
+} else {
+    set sc_macro_libraries []
+}
+set sc_mainlib [lindex $sc_logiclibs 0]
+
+set sc_abc_constraints \
+    [lindex [sc_cfg_tool_task_get {file} abc_constraint_file] 0]
+
+set sc_blackboxes []
+foreach lib $sc_macrolibs {
+    if { [sc_cfg_exists library $lib output blackbox verilog] } {
+        foreach lib_f [sc_cfg_get library $lib output blackbox verilog] {
+            lappend sc_blackboxes $lib_f
+        }
+    }
+}
+
+set sc_memory_libmap_files ""
+if { [sc_cfg_tool_task_exists file memory_libmap] } {
+    set sc_memory_libmap_files [sc_cfg_tool_task_get file memory_libmap]
+}
+
+set sc_memory_techmap_files ""
+if { [sc_cfg_tool_task_exists file memory_techmap] } {
+    set sc_memory_techmap_files [sc_cfg_tool_task_get file memory_techmap]
+}
+
+########################################################
+# Read Libraries
+########################################################
+
+foreach lib_file "$sc_libraries $sc_macro_libraries" {
+    yosys read_liberty -setattr liberty_cell -lib $lib_file
+}
+foreach bb_file $sc_blackboxes {
+    yosys log "Reading blackbox model file: $bb_file"
+    yosys read_verilog -setattr blackbox -sv $bb_file
+}
+
+# Before working on the design, we mask out any module supplied via
+# `blackbox_modules`. This allows synthesis of parts of the design without having
+# to modify the input RTL.
+if { [sc_cfg_tool_task_exists var blackbox_modules] } {
+    foreach bb [sc_cfg_tool_task_get var blackbox_modules] {
+        foreach module [get_modules $bb] {
+            yosys log "Blackboxing module: $module"
+            yosys blackbox $module
+        }
+    }
+}
+
 ########################################################
 # Design Inputs
 ########################################################
 
 set input_verilog "inputs/$sc_design.v"
-if { [file exists $input_verilog] } {
-    if { [lindex [sc_cfg_tool_task_get var use_slang] 0] == "true" && [sc_load_plugin slang] } {
-        # This needs some reordering of loaded to ensure blackboxes are handled
-        # before this
-        set slang_params []
-        if { [sc_cfg_exists option param] } {
-            dict for {key value} [sc_cfg_get option param] {
-                if { ![string is integer $value] } {
-                    set value [concat \"$value\"]
-                }
-
-                lappend slang_params -G "${key}=${value}"
-            }
+if { ![file exists $input_verilog] } {
+    set input_verilog "inputs/$sc_design.sv"
+    if { ![file exists $input_verilog] } {
+        set input_verilog []
+        if { [sc_cfg_exists input rtl systemverilog] } {
+            lappend input_verilog {*}[sc_cfg_get input rtl systemverilog]
         }
-        yosys read_slang \
-            -D SYNTHESIS \
-            --keep-hierarchy \
-            --top $sc_design \
-            {*}$slang_params \
-            $input_verilog
-    } else {
-        # Use -noblackbox to correctly interpret empty modules as empty,
-        # actual black boxes are read in later
-        # https://github.com/YosysHQ/yosys/issues/1468
-        yosys read_verilog -noblackbox -sv $input_verilog
+        if { [sc_cfg_exists input rtl verilog] } {
+            lappend input_verilog {*}[sc_cfg_get input rtl verilog]
+        }
+    }
+}
 
-        ########################################################
-        # Override top level parameters
-        ########################################################
+if { [lindex [sc_cfg_tool_task_get var use_slang] 0] == "true" && [sc_load_plugin slang] } {
+    # This needs some reordering of loaded to ensure blackboxes are handled
+    # before this
+    set slang_params []
+    if { [sc_cfg_exists option param] } {
+        dict for {key value} [sc_cfg_get option param] {
+            if { ![string is integer $value] } {
+                set value [concat \"$value\"]
+            }
 
-        sc_apply_params
+            lappend slang_params -G "${key}=${value}"
+        }
     }
+    yosys read_slang \
+        -D SYNTHESIS \
+        --keep-hierarchy \
+        --ignore-assertions \
+        --allow-use-before-declare \
+        --top $sc_design \
+        {*}$slang_params \
+        {*}$input_verilog
+    yosys setattr -unset init
+} else {
+    # Use -noblackbox to correctly interpret empty modules as empty,
+    # actual black boxes are read in later
+    # https://github.com/YosysHQ/yosys/issues/1468
+    yosys read_verilog -noblackbox -sv {*}$input_verilog
+
+    ########################################################
+    # Override top level parameters
+    ########################################################
+
+    sc_apply_params
 }
 
 ####################
@@ -111,44 +187,6 @@ proc get_modules { { find "*" } } {
     return [lsort $modules]
 }
 
-####################
-# DESIGNER's CHOICE
-####################
-
-set sc_logiclibs [sc_get_asic_libraries logic]
-set sc_macrolibs [sc_get_asic_libraries macro]
-
-set sc_libraries [sc_cfg_tool_task_get {file} synthesis_libraries]
-if { [sc_cfg_tool_task_exists {file} synthesis_libraries_macros] } {
-    set sc_macro_libraries \
-        [sc_cfg_tool_task_get {file} synthesis_libraries_macros]
-} else {
-    set sc_macro_libraries []
-}
-set sc_mainlib [lindex $sc_logiclibs 0]
-
-set sc_abc_constraints \
-    [lindex [sc_cfg_tool_task_get {file} abc_constraint_file] 0]
-
-set sc_blackboxes []
-foreach lib $sc_macrolibs {
-    if { [sc_cfg_exists library $lib output blackbox verilog] } {
-        foreach lib_f [sc_cfg_get library $lib output blackbox verilog] {
-            lappend sc_blackboxes $lib_f
-        }
-    }
-}
-
-set sc_memory_libmap_files ""
-if { [sc_cfg_tool_task_exists file memory_libmap] } {
-    set sc_memory_libmap_files [sc_cfg_tool_task_get file memory_libmap]
-}
-
-set sc_memory_techmap_files ""
-if { [sc_cfg_tool_task_exists file memory_techmap] } {
-    set sc_memory_techmap_files [sc_cfg_tool_task_get file memory_techmap]
-}
-
 #########################
 # Schema helper functions
 #########################
@@ -201,34 +239,10 @@ proc get_buffer_cell { } {
     return "$cell $in $out"
 }
 
-########################################################
-# Read Libraries
-########################################################
-
-foreach lib_file "$sc_libraries $sc_macro_libraries" {
-    yosys read_liberty -setattr liberty_cell -lib $lib_file
-}
-foreach bb_file $sc_blackboxes {
-    yosys log "Reading blackbox model file: $bb_file"
-    yosys read_verilog -setattr blackbox -sv $bb_file
-}
-
 ########################################################
 # Synthesis
 ########################################################
 
-# Before working on the design, we mask out any module supplied via
-# `blackbox_modules`. This allows synthesis of parts of the design without having
-# to modify the input RTL.
-if { [sc_cfg_tool_task_exists var blackbox_modules] } {
-    foreach bb [sc_cfg_tool_task_get var blackbox_modules] {
-        foreach module [get_modules $bb] {
-            yosys log "Blackboxing module: $module"
-            yosys blackbox $module
-        }
-    }
-}
-
 # Although the `synth` command also runs `hierarchy`, we run it here without the
 # `-check` flag first in order to resolve parameters before looking for missing
 # modules. This works around the fact that Surelog doesn't pickle modules that

siliconcompiler/tools/yosys/syn_asic.py

@@ -8,7 +8,7 @@ from siliconcompiler import utils
 from siliconcompiler.tools._common.asic import set_tool_task_var, get_libraries, get_mainlib, \
     CellArea
 from siliconcompiler.tools._common.asic_clock import get_clock_period
-from siliconcompiler.tools._common import get_tool_task
+from siliconcompiler.tools._common import get_tool_task, input_provides, add_require_input
 
 
 def make_docs(chip):
@@ -34,7 +34,18 @@ def setup(chip):
              step=step, index=index, clobber=False)
 
     # Input/output requirements.
-    chip.set('tool', tool, 'task', task, 'input', design + '.v', step=step, index=index)
+    if f'{design}.v' in input_provides(chip, step, index):
+        chip.set('tool', tool, 'task', task, 'input', design + '.v', step=step, index=index)
+    elif f'{design}.sv' in input_provides(chip, step, index):
+        chip.set('tool', tool, 'task', task, 'input', design + '.sv', step=step, index=index)
+    else:
+        added = False
+        added |= add_require_input(chip, 'input', 'rtl', 'systemverilog',
+                                   include_library_files=False)
+        added |= add_require_input(chip, 'input', 'rtl', 'verilog',
+                                   include_library_files=False)
+        if not added:
+            chip.add('tool', tool, 'task', task, 'require', 'input,rtl,verilog')
     chip.set('tool', tool, 'task', task, 'output', design + '.vg', step=step, index=index)
     chip.add('tool', tool, 'task', task, 'output', design + '.netlist.json', step=step, index=index)
 
@@ -556,8 +567,6 @@ def _generate_cell_area_report(chip):
             area = info["area"]
 
         for cell, inst_count in info["num_cells_by_type"].items():
-            # print(module, cell, inst_count)
-
             cell_area, cell_count = get_area_count(cell)
 
             count += cell_count * inst_count

siliconcompiler/toolscripts/_tools.json

@@ -1,7 +1,7 @@
 {
   "openroad": {
     "git-url": "https://github.com/The-OpenROAD-Project/OpenROAD.git",
-    "git-commit": "10c0e05959e169ec9740d83e80bb4f2395afcc7b",
+    "git-commit": "ce617810e4dc11b3cdb5a267ef3454788f81aaf0",
     "docker-cmds": [
       "# Remove OR-Tools files",
       "RUN rm -f $SC_PREFIX/Makefile $SC_PREFIX/README.md",
@@ -15,6 +15,11 @@
     "git-commit": "v1.84",
     "auto-update": true
   },
+  "opensta": {
+    "git-url": "https://github.com/parallaxsw/OpenSTA.git",
+    "git-commit": "b32eed9a849381172a5d3208cc7798a8a11c4c9b",
+    "auto-update": true
+  },
   "netgen": {
     "git-url": "https://github.com/RTimothyEdwards/netgen.git",
     "git-commit": "fb7876c7a6f9d58a3d88a49e302e682c1d12e00d",
@@ -36,7 +41,7 @@
     "auto-update": false
   },
   "klayout": {
-    "version": "0.30.0",
+    "version": "0.30.1",
     "git-url": "https://github.com/KLayout/klayout.git",
     "docker-skip": true,
     "auto-update": true,
@@ -45,7 +50,7 @@
   },
   "sv2v": {
     "git-url": "https://github.com/zachjs/sv2v.git",
-    "git-commit": "e5effb5e1ea4e0cf9b4af2c769d364e0ed4b6d84",
+    "git-commit": "d30c7e7f4e9018b9d4a565207ff752460c81eeb4",
     "auto-update": true
   },
   "verilator": {
@@ -66,7 +71,7 @@
   },
   "vpr": {
     "git-url": "https://github.com/verilog-to-routing/vtr-verilog-to-routing.git",
-    "git-commit": "2a4e92181280a235315621253d1dc9eb8826bc53",
+    "git-commit": "c606a21d9ab5db53fb382a7dd79a0703c887108c",
     "auto-update": false
   },
   "icepack": {
@@ -91,7 +96,7 @@
   },
   "yosys": {
     "git-url": "https://github.com/YosysHQ/yosys.git",
-    "git-commit": "v0.51",
+    "git-commit": "v0.53",
     "version-prefix": "",
     "auto-update": true
   },
@@ -139,7 +144,7 @@
   },
   "yosys-slang": {
     "git-url": "https://github.com/povik/yosys-slang.git",
-    "git-commit": "e23228f4b4ec5ec0b4b17f1f675debfa29458665",
+    "git-commit": "7d4959430442ac1d7e3bf7b3e55d648293a5ac7b",
     "docker-depends": "yosys",
     "auto-update": true
   },
@@ -151,7 +156,7 @@
   },
   "yosys-parmys": {
     "git-url": "https://github.com/verilog-to-routing/vtr-verilog-to-routing.git",
-    "git-commit": "2a4e92181280a235315621253d1dc9eb8826bc53",
+    "git-commit": "c606a21d9ab5db53fb382a7dd79a0703c887108c",
     "docker-depends": [
       "yosys",
       "vpr"

siliconcompiler/toolscripts/rhel8/install-chisel.sh

@@ -5,6 +5,8 @@ set -e
 # Get directory of script
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
+sudo yum install -y wget
+
 mkdir -p deps
 cd deps
 

siliconcompiler/toolscripts/rhel8/install-icarus.sh

@@ -6,6 +6,7 @@ set -e
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
 sudo yum group install -y "Development Tools"
+sudo yum install -y wget git
 
 args=
 if [ ! -z ${PREFIX} ]; then

siliconcompiler/toolscripts/rhel8/install-klayout.sh

@@ -5,6 +5,8 @@ set -e
 # Get directory of script
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
+sudo yum install -y wget
+
 mkdir -p deps
 cd deps
 

siliconcompiler/toolscripts/rhel8/install-magic.sh

@@ -6,8 +6,7 @@ set -e
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
 sudo yum group install -y "Development Tools"
-sudo yum install -y tcl-devel tk-devel tcsh csh
-# sudo apt-get install -y build-essential m4 tcsh csh libx11-dev tcl-dev tk-dev
+sudo yum install -y tcl-devel tk-devel tcsh csh git
 
 mkdir -p deps
 cd deps

siliconcompiler/toolscripts/rhel8/install-netgen.sh

@@ -6,7 +6,7 @@ set -e
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
 sudo yum group install -y "Development Tools"
-sudo yum install -y tcl-devel tk-devel
+sudo yum install -y tcl-devel tk-devel git
 
 mkdir -p deps
 cd deps

siliconcompiler/toolscripts/rhel8/install-slang.sh

@@ -5,6 +5,8 @@ set -e
 # Get directory of script
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
+sudo yum install -y git
+
 mkdir -p deps
 cd deps
 

siliconcompiler/toolscripts/rhel8/install-surelog.sh

@@ -5,6 +5,8 @@ set -e
 # Get directory of script
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
+sudo yum install -y git
+
 # These dependencies are up-to-date with instructions from the INSTALL.md from the commit we are pinned to below
 sudo yum install -y gcc-toolset-12
 sudo dnf config-manager --set-enabled devel || true
@@ -17,7 +19,7 @@ cd deps
 python3 -m venv .surelog --clear
 . .surelog/bin/activate
 python3 -m pip install --upgrade pip
-python3 -m pip install cmake
+python3 -m pip install cmake==3.28.4
 python3 -m pip install orderedmultidict
 
 git clone $(python3 ${src_path}/_tools.py --tool surelog --field git-url) surelog

siliconcompiler/toolscripts/rhel8/install-sv2v.sh

@@ -8,6 +8,7 @@ src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 mkdir -p deps
 cd deps
 
+sudo yum install -y git curl
 sudo yum group install -y "Development Tools"
 sudo yum install -y gmp-devel xz
 

siliconcompiler/toolscripts/rhel8/install-verible.sh

@@ -5,6 +5,8 @@ set -e
 # Get directory of script
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
+sudo yum install -y wget
+
 mkdir -p deps
 cd deps
 

siliconcompiler/toolscripts/rhel8/install-verilator.sh

@@ -6,6 +6,7 @@ set -e
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
 sudo yum group install -y "Development Tools"
+sudo yum install -y git wget
 
 mkdir -p deps
 cd deps

siliconcompiler/toolscripts/rhel8/install-xyce.sh

@@ -5,6 +5,8 @@ set -e
 # Get directory of script
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
+sudo yum install -y wget
+
 mkdir -p deps
 cd deps
 

siliconcompiler/toolscripts/rhel9/install-chisel.sh

@@ -5,6 +5,8 @@ set -e
 # Get directory of script
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
+sudo yum install -y wget
+
 mkdir -p deps
 cd deps
 

siliconcompiler/toolscripts/rhel9/install-ghdl.sh

@@ -6,6 +6,7 @@ set -e
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
 sudo yum install -y gcc-gnat zlib-devel diffutils
+sudo yum install -y git
 
 mkdir -p deps
 cd deps

siliconcompiler/toolscripts/rhel9/install-gtkwave.sh

@@ -8,6 +8,7 @@ src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 sudo yum group install -y "Development Tools"
 sudo yum install -y gtk3-devel \
     bzip2-devel xz-devel tcl-devel tk-devel
+sudo yum install -y wget git
 sudo dnf config-manager --set-enabled devel || true
 sudo yum install -y Judy-devel
 sudo dnf config-manager --set-disabled devel || true

siliconcompiler/toolscripts/rhel9/install-icarus.sh

@@ -6,6 +6,7 @@ set -e
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
 sudo yum group install -y "Development Tools"
+sudo yum install -y wget git
 
 args=
 if [ ! -z ${PREFIX} ]; then

siliconcompiler/toolscripts/rhel9/install-klayout.sh

@@ -5,6 +5,8 @@ set -e
 # Get directory of script
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
+sudo yum install -y wget
+
 mkdir -p deps
 cd deps
 

siliconcompiler/toolscripts/rhel9/install-magic.sh

@@ -6,8 +6,7 @@ set -e
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
 sudo yum group install -y "Development Tools"
-sudo yum install -y tcl-devel tk-devel tcsh csh
-# sudo apt-get install -y build-essential m4 tcsh csh libx11-dev tcl-dev tk-dev
+sudo yum install -y tcl-devel tk-devel tcsh csh git
 
 mkdir -p deps
 cd deps

siliconcompiler/toolscripts/rhel9/install-netgen.sh

@@ -6,7 +6,7 @@ set -e
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
 sudo yum group install -y "Development Tools"
-sudo yum install -y tcl-devel tk-devel
+sudo yum install -y tcl-devel tk-devel git
 
 mkdir -p deps
 cd deps

siliconcompiler/toolscripts/rhel9/install-openroad.sh

@@ -4,6 +4,8 @@ set -e
 
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
+sudo yum install -y git
+
 mkdir -p deps
 cd deps
 

siliconcompiler/toolscripts/rhel9/install-opensta.sh

@@ -0,0 +1,76 @@
+#!/bin/sh
+
+set -e
+
+src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
+
+sudo yum install -y git gcc-c++ wget
+sudo yum install -y tcl-tclreadline-devel \
+    bison flex zlib-devel automake autoconf
+sudo yum install -y \
+    https://mirror.stream.centos.org/9-stream/AppStream/x86_64/os/Packages/flex-2.6.4-9.el9.x86_64.rpm \
+    https://mirror.stream.centos.org/9-stream/AppStream/x86_64/os/Packages/readline-devel-8.1-4.el9.x86_64.rpm \
+    https://rpmfind.net/linux/centos-stream/9-stream/AppStream/x86_64/os/Packages/tcl-devel-8.6.10-7.el9.x86_64.rpm
+
+mkdir -p deps
+cd deps
+
+python3 -m venv .opensta --clear
+. .opensta/bin/activate
+python3 -m pip install cmake==3.31.6
+
+if [ ! -z ${PREFIX} ]; then
+    cmake_args="-DCMAKE_INSTALL_PREFIX=$PREFIX"
+    config_prefix="--prefix=$PREFIX"
+fi
+
+# eigen
+mkdir -p eigen3
+cd eigen3
+git clone --depth=1 -b 3.4 https://gitlab.com/libeigen/eigen.git
+cd eigen
+mkdir build
+cd build
+cmake $cmake_args ..
+make -j$(nproc)
+sudo make install
+
+cd ../../..
+# cudd
+mkdir -p cudd
+cd cudd
+git clone --depth=1 -b 3.0.0 https://github.com/The-OpenROAD-Project/cudd.git
+cd cudd
+autoreconf
+./configure $config_prefix
+make -j$(nproc)
+sudo make install
+
+cd ../..
+#swig
+wget -O swig.tar.gz https://github.com/swig/swig/archive/v4.1.0.tar.gz
+tar xfz swig.tar.gz
+cd swig-4.1.0
+
+wget https://github.com/PCRE2Project/pcre2/releases/download/pcre2-10.42/pcre2-10.42.tar.gz
+./Tools/pcre-build.sh
+
+./autogen.sh
+./configure $config_prefix
+make -j$(nproc)
+sudo make -j$(nproc) install
+
+cd ../..
+# opensta
+git clone $(python3 ${src_path}/_tools.py --tool opensta --field git-url) opensta
+cd opensta
+git checkout $(python3 ${src_path}/_tools.py --tool opensta --field git-commit)
+git submodule update --init --recursive
+
+mkdir -p build
+cd build
+cmake .. $cmake_args
+make -j$(nproc)
+sudo make install
+
+cd -

siliconcompiler/toolscripts/rhel9/install-slang.sh

@@ -5,13 +5,15 @@ set -e
 # Get directory of script
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
+sudo yum install -y git
+
 mkdir -p deps
 cd deps
 
 python3 -m venv .slang --clear
 . .slang/bin/activate
 python3 -m pip install --upgrade pip
-python3 -m pip install cmake
+python3 -m pip install cmake==3.31.6
 
 sudo yum install -y gcc-toolset-12
 

siliconcompiler/toolscripts/rhel9/install-surelog.sh

@@ -10,6 +10,7 @@ sudo yum install -y gcc-toolset-12
 sudo dnf config-manager --set-enabled devel || true
 sudo yum install -y libuuid-devel java-11-openjdk-devel python3 zlib-static openssl-devel 
 sudo dnf config-manager --set-disabled devel || true
+sudo yum install -y git
 
 mkdir -p deps
 cd deps
@@ -17,7 +18,7 @@ cd deps
 python3 -m venv .surelog --clear
 . .surelog/bin/activate
 python3 -m pip install --upgrade pip
-python3 -m pip install cmake
+python3 -m pip install cmake==3.31.6
 python3 -m pip install orderedmultidict
 
 git clone $(python3 ${src_path}/_tools.py --tool surelog --field git-url) surelog

siliconcompiler/toolscripts/rhel9/install-sv2v.sh

@@ -8,6 +8,7 @@ src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 mkdir -p deps
 cd deps
 
+sudo yum install -y --skip-broken git curl
 sudo yum group install -y "Development Tools"
 sudo yum install -y gmp-devel xz
 

siliconcompiler/toolscripts/rhel9/install-verible.sh

@@ -5,6 +5,8 @@ set -e
 # Get directory of script
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
+sudo yum install -y wget
+
 mkdir -p deps
 cd deps
 

siliconcompiler/toolscripts/rhel9/install-verilator.sh

@@ -6,6 +6,7 @@ set -e
 src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
 
 sudo yum group install -y "Development Tools"
+sudo yum install -y git wget
 
 mkdir -p deps
 cd deps