siliconcompiler 0.32.2__py3-none-any.whl → 0.33.0__py3-none-any.whl

siliconcompiler/tools/_common/__init__.py

@@ -103,6 +103,8 @@ def add_require_input(chip, *key, include_library_files=True):
                  ",".join(key),
                  step=step, index=index)
 
+    return bool(keys)
+
 
 def get_input_files(chip, *key, add_library_files=True):
     '''
@@ -463,16 +465,12 @@ def record_metric(chip, step, index, metric, value, source, source_unit=None):
         Records the metric cell area under 'floorplan0' and notes the source as
         'reports/metrics.json'
     '''
-    from siliconcompiler import units
-
-    metric_unit = None
-    if chip.schema.has_field('metric', metric, 'unit'):
-        metric_unit = chip.get('metric', metric, field='unit')
-
-    if metric_unit:
-        value = units.convert(value, from_unit=source_unit, to_unit=metric_unit)
-
-    chip.set('metric', metric, value, step=step, index=index)
+    chip.get("metric", field="schema").record(
+        step, index,
+        metric,
+        value,
+        unit=source_unit
+    )
 
     if source:
         flow = chip.get('option', 'flow')

siliconcompiler/tools/_common/sdc/sc_constraints.sdc

@@ -1,6 +1,6 @@
 # Default constraints file that sets up clocks based on definitions in schema.
 
-source sc_manifest.tcl > /dev/null
+source sc_manifest.tcl
 
 ### Create clocks
 if { [sc_cfg_exists datasheet pin] } {

siliconcompiler/tools/bluespec/convert.py

@@ -70,24 +70,24 @@ def runtime_options(chip):
     opts = get_frontend_options(chip, ['idir', 'ydir', 'define'])
 
     cmdlist.append('-verilog')
-    cmdlist.append(f'-vdir {VLOG_DIR}')
-    cmdlist.append(f'-bdir {BSC_DIR}')
-    cmdlist.append('-info-dir reports')
+    cmdlist.extend(['-vdir', VLOG_DIR])
+    cmdlist.extend(['-bdir', BSC_DIR])
+    cmdlist.extend(['-info-dir', 'reports'])
     cmdlist.append('-u')
     cmdlist.append('-v')
 
     cmdlist.append('-show-module-use')
     cmdlist.append('-sched-dot')
 
-    cmdlist.append(f'-g {chip.top(step, index)}')
+    cmdlist.extend(['-g', chip.top(step, index)])
 
     bsc_path = ':'.join(opts['ydir'] + ['%/Libraries'])
-    cmdlist.append('-p ' + bsc_path)
+    cmdlist.extend(['-p', bsc_path])
 
     for value in opts['idir']:
-        cmdlist.append('-I ' + value)
+        cmdlist.extend(['-I', value])
     for value in opts['define']:
-        cmdlist.append('-D ' + value)
+        cmdlist.extend(['-D', value])
 
     sources = get_input_files(chip, 'input', 'hll', 'bsv', add_library_files=False)
     if len(sources) != 1:

siliconcompiler/tools/builtin/_common.py

@@ -3,7 +3,7 @@ from siliconcompiler import NodeStatus, SiliconCompilerError
 from siliconcompiler import utils
 import shutil
 from siliconcompiler.tools._common import get_tool_task
-from siliconcompiler.flowgraph import _get_pruned_node_inputs
+from siliconcompiler.utils.flowgraph import _get_pruned_node_inputs
 
 
 ###########################################################################

siliconcompiler/tools/builtin/concatenate.py

@@ -3,7 +3,7 @@ import os
 from siliconcompiler import sc_open, SiliconCompilerError
 from siliconcompiler import utils
 from siliconcompiler.tools._common import input_provides, input_file_node_name, get_tool_task
-from siliconcompiler import flowgraph
+from siliconcompiler.utils import flowgraph
 from siliconcompiler import scheduler
 
 
@@ -12,7 +12,7 @@ def make_docs(chip):
     _make_docs(chip)
     chip.set('option', 'flow', 'asicflow')
 
-    for step, index in flowgraph._get_flowgraph_entry_nodes(chip, 'asicflow'):
+    for step, index in chip.schema.get("flowgraph", "asicflow", field="schema").get_entry_nodes():
         scheduler._setup_node(chip, step, index)
 
     chip.set('arg', 'step', 'import.combine')

siliconcompiler/tools/builtin/minimum.py

@@ -1,5 +1,5 @@
 from siliconcompiler.tools.builtin import _common
-from siliconcompiler import flowgraph
+from siliconcompiler.utils import flowgraph
 from siliconcompiler.tools.builtin.builtin import set_io_files
 
 

siliconcompiler/tools/builtin/mux.py

@@ -1,7 +1,8 @@
 from siliconcompiler.tools.builtin import _common
 import re
 from siliconcompiler.tools.builtin.builtin import set_io_files
-from siliconcompiler import flowgraph, SiliconCompilerError
+from siliconcompiler import SiliconCompilerError
+from siliconcompiler.utils import flowgraph
 
 
 def setup(chip):

siliconcompiler/tools/builtin/nop.py

@@ -1,6 +1,6 @@
 from siliconcompiler.tools.builtin import _common
 from siliconcompiler.tools.builtin.builtin import set_io_files
-from siliconcompiler import flowgraph
+from siliconcompiler.utils import flowgraph
 
 
 def setup(chip):

siliconcompiler/tools/builtin/verify.py

@@ -1,11 +1,13 @@
 from siliconcompiler.tools.builtin import _common
-from siliconcompiler.schema import Schema
+from siliconcompiler.schema.parametertype import NodeType
 from siliconcompiler.scheduler import _haltstep
 from siliconcompiler.tools.builtin.builtin import set_io_files
-from siliconcompiler import utils, flowgraph, SiliconCompilerError
+from siliconcompiler import utils, SiliconCompilerError
 
 import re
 
+from siliconcompiler.utils import flowgraph
+
 
 def setup(chip):
     '''
@@ -52,8 +54,8 @@ def _select_inputs(chip, step, index):
             raise SiliconCompilerError(
                 f"Missing metric for {metric} in {inputs[0]}{inputs[1]}", chip=chip)
 
-        metric_type = chip.get('metric', metric, field='type')
-        goal = Schema._normalize_value(goal, metric_type, "", None)
+        metric_type = chip.get('metric', metric, field=None)
+        goal = NodeType.normalize(goal, metric_type.get(field='type'))
         if not utils.safecompare(chip, value, op, goal):
             chip.error(f"{step}{index} fails '{metric}' metric: {value}{op}{goal}")
 

siliconcompiler/tools/chisel/convert.py

@@ -120,15 +120,15 @@ def runtime_options(chip):
                                     step=step, index=index))
         runMain.append("--")
 
-        runMain.append("--target-dir chisel-output")
+        runMain.extend(["--target-dir", "chisel-output"])
     else:
         # Use built in driver
         runMain.append("SCDriver")
-        runMain.append(f"--module {chip.top(step=step, index=index)}")
+        runMain.extend(["--module", chip.top(step=step, index=index)])
 
-        runMain.append(f"--output-file ../outputs/{design}.v")
+        runMain.extend(["--output-file", f"../outputs/{design}.v"])
 
-    return [f'"{" ".join(runMain)}"']
+    return [" ".join(runMain)]
 
 
 def post_process(chip):

siliconcompiler/tools/genfasm/bitstream.py

@@ -41,9 +41,9 @@ def runtime_options(chip):
     blif = f"inputs/{design}.blif"
     options.append(blif)
 
-    options.append(f'--net_file inputs/{design}.net')
-    options.append(f'--place_file inputs/{design}.place')
-    options.append(f'--route_file inputs/{design}.route')
+    options.extend(['--net_file', f'inputs/{design}.net'])
+    options.extend(['--place_file', f'inputs/{design}.place'])
+    options.extend(['--route_file', f'inputs/{design}.route'])
 
     return options
 

siliconcompiler/tools/ghdl/convert.py

@@ -25,7 +25,7 @@ def setup(chip):
 
     chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=clobber)
-    chip.set('tool', tool, 'task', task, 'option', '',
+    chip.set('tool', tool, 'task', task, 'option', [],
              step=step, index=index, clobber=clobber)
     chip.set('tool', tool, 'task', task, 'stdout', 'destination', 'output',
              step=step, index=index)

siliconcompiler/tools/icarus/compile.py

@@ -68,19 +68,19 @@ def runtime_options(chip):
 
     # source files
     for value in opts['ydir']:
-        cmdlist.append('-y ' + value)
+        cmdlist.extend(['-y', value])
     for value in opts['vlib']:
-        cmdlist.append('-v ' + value)
+        cmdlist.extend(['-v', value])
     for value in opts['idir']:
         cmdlist.append('-I' + value)
     for value in opts['define']:
         cmdlist.append('-D' + value)
 
     # add siliconcompiler specific defines
-    cmdlist.append(f"-DSILICONCOMPILER_TRACE_FILE=\\\"reports/{design}.vcd\\\"")
+    cmdlist.append(f"-DSILICONCOMPILER_TRACE_FILE=\"reports/{design}.vcd\"")
 
     for value in get_input_files(chip, 'input', 'cmdfile', 'f'):
-        cmdlist.append('-f ' + value)
+        cmdlist.extend(['-f', value])
     for value in get_input_files(chip, 'input', 'rtl', 'netlist'):
         cmdlist.append(value)
     for value in get_input_files(chip, 'input', 'rtl', 'verilog'):

siliconcompiler/tools/icepack/bitstream.py

@@ -1,4 +1,5 @@
 from siliconcompiler.tools._common import get_tool_task
+from siliconcompiler.tools.icepack.icepack import runtime_options as tool_runtime_options
 
 
 def setup(chip):
@@ -15,6 +16,10 @@ def setup(chip):
 
     chip.set('tool', tool, 'exe', tool)
 
-    chip.set('tool', tool, 'task', task, 'option', "", step=step, index=index, clobber=clobber)
+    chip.set('tool', tool, 'task', task, 'option', [], step=step, index=index, clobber=clobber)
     chip.set('tool', tool, 'task', task, 'input', f'{design}.asc', step=step, index=index)
     chip.set('tool', tool, 'task', task, 'output', f'{design}.bit', step=step, index=index)
+
+
+def runtime_options(chip):
+    return tool_runtime_options(chip)

siliconcompiler/tools/klayout/convert_drc_db.py

@@ -1,6 +1,7 @@
 from siliconcompiler.tools._common import input_provides, input_file_node_name, get_tool_task
 
 from siliconcompiler.tools.klayout.klayout import setup as setup_tool
+from siliconcompiler.tools.klayout.klayout import runtime_options as tool_runtime_options
 
 
 def make_docs(chip):
@@ -58,3 +59,7 @@ def setup(chip):
 
     chip.set('tool', tool, 'task', task, 'output', f'{design}.json',
              step=step, index=index)
+
+
+def runtime_options(chip):
+    return tool_runtime_options(chip)

siliconcompiler/tools/klayout/klayout_export.py

@@ -121,7 +121,6 @@ def main():
     # SC_ROOT provided by CLI
     sys.path.append(SC_KLAYOUT_ROOT)  # noqa: F821
     sys.path.append(SC_TOOLS_ROOT)  # noqa: F821
-    print(sys.path)
 
     from klayout_utils import (
         technology,

siliconcompiler/tools/klayout/klayout_utils.py

@@ -1,5 +1,4 @@
 import pya
-import importlib.util as importlib_util
 import json
 import os
 import shutil
@@ -172,15 +171,9 @@ def get_write_options(filename, timestamps):
 
 
 def get_schema(manifest):
-    scroot = os.path.join(os.path.dirname(__file__), '..', '..')
-    module_name = 'schema'
-    schema_base = os.path.join(scroot, module_name, '__init__.py')
-    spec = importlib_util.spec_from_file_location(module_name, schema_base)
-    module = importlib_util.module_from_spec(spec)
-    sys.modules[module_name] = module
-    spec.loader.exec_module(module)
-    # Return schema
-    return module.Schema(manifest=manifest)
+    sys.path.append(os.path.join(os.path.dirname(__file__), '..', '..'))
+    from schema.safeschema import SafeSchema
+    return SafeSchema.from_manifest(filepath=manifest)
 
 
 def generate_metrics():

siliconcompiler/tools/nextpnr/apr.py

@@ -1,4 +1,5 @@
 from siliconcompiler.tools._common import get_tool_task
+from siliconcompiler.tools.nextpnr.nextpnr import runtime_options as tool_runtime_options
 
 
 def setup(chip):
@@ -18,7 +19,11 @@ def setup(chip):
     chip.set('tool', tool, 'vswitch', '--version')
     chip.set('tool', tool, 'version', '>=0.2', clobber=clobber)
 
-    chip.set('tool', tool, 'task', task, 'option', "", step=step, index=index, clobber=clobber)
+    chip.set('tool', tool, 'task', task, 'option', [], step=step, index=index, clobber=clobber)
     chip.set('tool', tool, 'task', task, 'input', f'{topmodule}.netlist.json',
              step=step, index=index)
     chip.set('tool', tool, 'task', task, 'output', f'{topmodule}.asc', step=step, index=index)
+
+
+def runtime_options(chip):
+    return tool_runtime_options(chip)

siliconcompiler/tools/nextpnr/nextpnr.py

@@ -33,14 +33,14 @@ def runtime_options(chip):
 
     options = []
 
-    options.append('--json inputs/' + topmodule + '.netlist.json')
-    options.append('--asc outputs/' + topmodule + '.asc')
+    options.extend(['--json', 'inputs/' + topmodule + '.netlist.json'])
+    options.extend(['--asc', 'outputs/' + topmodule + '.asc'])
 
     if partname == 'ice40up5k-sg48':
-        options.append('--up5k --package sg48')
+        options.extend(['--up5k', '--package', 'sg48'])
 
     for constraint_file in chip.find_files('input', 'constraint', 'pcf', step=step, index=index):
-        options.append('--pcf ' + constraint_file)
+        options.extend(['--pcf', constraint_file])
 
     return options
 

siliconcompiler/tools/openroad/_apr.py

@@ -500,6 +500,10 @@ def define_ppl_params(chip):
                 ['pdk', pdkname, 'var', 'openroad', 'pin_layer_vertical', stackup]):
         chip.add('tool', tool, 'task', task, 'require', ",".join(key),
                  step=step, index=index)
+    if chip.get('tool', tool, 'task', task, 'file', 'ppl_constraints', step=step, index=index):
+        chip.add('tool', tool, 'task', task, 'require',
+                 ",".join(['tool', tool, 'task', task, 'file', 'ppl_constraints']),
+                 step=step, index=index)
 
 
 def define_pdn_params(chip):
@@ -797,6 +801,14 @@ def define_sta_params(chip):
     set_tool_task_var(chip, param_key='sta_top_n_paths',
                       default_value='10',
                       schelp='number of paths to report timing for')
+    set_tool_task_var(chip, param_key='sta_define_path_groups',
+                      default_value=True,
+                      skip=['pdk', 'lib'],
+                      schelp='true/false, if true will generate path groups for timing reporting')
+    set_tool_task_var(chip, param_key='sta_unique_path_groups_per_clock',
+                      default_value=False,
+                      skip=['pdk', 'lib'],
+                      schelp='true/false, if true will generate separate path groups per clock')
 
     chip.set('tool', tool, 'task', task, 'var', 'power_corner', get_power_corner(chip),
              step=step, index=index, clobber=False)
@@ -1040,6 +1052,8 @@ def set_pnr_inputs(chip):
 
     design = chip.top()
 
+    # clear
+    chip.set('tool', tool, 'task', task, 'input', [], step=step, index=index)
     if f'{design}.sdc' in input_provides(chip, step, index):
         chip.add('tool', tool, 'task', task, 'input', design + '.sdc',
                  step=step, index=index)
@@ -1067,6 +1081,9 @@ def set_pnr_outputs(chip):
 
     design = chip.top()
 
+    # clear
+    chip.set('tool', tool, 'task', task, 'output', [], step=step, index=index)
+
     chip.add('tool', tool, 'task', task, 'output', design + '.sdc', step=step, index=index)
     chip.add('tool', tool, 'task', task, 'output', design + '.vg', step=step, index=index)
     chip.add('tool', tool, 'task', task, 'output', design + '.def', step=step, index=index)

siliconcompiler/tools/openroad/fillmetal_insertion.py

@@ -1,5 +1,3 @@
-from siliconcompiler import NodeStatus
-
 from siliconcompiler.tools._common import get_tool_task, has_pre_post_script
 from siliconcompiler.tools._common.asic import get_mainlib
 
@@ -55,24 +53,26 @@ def setup(chip):
         'clock_trees'
     ])
 
-
-def pre_process(chip):
-    step = chip.get('arg', 'step')
-    index = chip.get('arg', 'index')
-    tool, task = get_tool_task(chip, step, index)
-    if not has_pre_post_script(chip) and \
-            chip.get('tool', tool, 'task', task, 'var', 'fin_add_fill',
-                     step=step, index=index) == ["true"]:
+    if chip.get('tool', tool, 'task', task, 'var', 'fin_add_fill',
+                step=step, index=index) == ["true"]:
         pdk = chip.get('option', 'pdk')
         stackup = chip.get('option', 'stackup')
         mainlib = get_mainlib(chip)
         libtype = chip.get('library', mainlib, 'asic', 'libarch', step=step, index=index)
+        if chip.get('pdk', pdk, 'aprtech', tool, stackup, libtype, 'fill'):
+            chip.add('tool', tool, 'task', task, 'require',
+                     ",".join(['pdk', pdk, 'aprtech', tool, stackup, libtype, 'fill']),
+                     step=step, index=index)
+        else:
+            if not has_pre_post_script(chip):
+                # nothing to do so we can skip
+                return "no fill script is available"
 
-        if not chip.find_files('pdk', pdk, 'aprtech', tool, stackup, libtype, 'fill'):
-            chip.set('record', 'status', NodeStatus.SKIPPED, step=step, index=index)
-            chip.logger.warning(f'{step}{index} will be skipped since there is nothing to do.')
-            return
+            chip.set('tool', tool, 'task', task, 'var', 'fin_add_fill', False,
+                     step=step, index=index)
 
+
+def pre_process(chip):
     define_ord_files(chip)
     build_pex_corners(chip)
 

siliconcompiler/tools/openroad/rdlroute.py

@@ -31,11 +31,11 @@ def setup(chip):
     chip.set('tool', tool, 'format', 'tcl')
 
     # exit automatically in batch mode and not breakpoint
-    option = ''
+    option = ['-no_init']
     if exit and not chip.get('option', 'breakpoint', step=step, index=index):
-        option += " -exit"
+        option.append("-exit")
 
-    option += " -metrics reports/metrics.json"
+    option.extend(["-metrics", "reports/metrics.json"])
     chip.set('tool', tool, 'task', task, 'option', option, step=step, index=index)
 
     # Input/Output requirements for default asicflow steps

siliconcompiler/tools/openroad/scripts/apr/postamble.tcl

@@ -8,7 +8,7 @@ utl::push_metrics_stage "sc__poststep__{}"
 if { [sc_cfg_tool_task_exists postscript] } {
     foreach sc_post_script [sc_cfg_tool_task_get postscript] {
         puts "Sourcing post script: ${sc_post_script}"
-        source -echo $sc_post_script
+        source $sc_post_script
     }
 }
 utl::pop_metrics_stage

siliconcompiler/tools/openroad/scripts/apr/preamble.tcl

@@ -14,7 +14,7 @@ set sc_refdir [sc_cfg_tool_task_get refdir]
 # Setup debugging
 ###############################
 
-source -echo "$sc_refdir/common/debugging.tcl"
+source "$sc_refdir/common/debugging.tcl"
 
 ###############################
 # Setup helper functions
@@ -47,11 +47,11 @@ set_thread_count [sc_cfg_tool_task_get threads]
 # Read Files
 ###############################
 
-source -echo "$sc_refdir/common/read_liberty.tcl"
+source "$sc_refdir/common/read_liberty.tcl"
 
-source -echo "$sc_refdir/common/read_input_files.tcl"
+source "$sc_refdir/common/read_input_files.tcl"
 
-source -echo "$sc_refdir/common/read_timing_constraints.tcl"
+source "$sc_refdir/common/read_timing_constraints.tcl"
 
 ###############################
 # Common Setup
@@ -81,7 +81,7 @@ utl::push_metrics_stage "sc__prestep__{}"
 if { [sc_cfg_tool_task_exists prescript] } {
     foreach sc_pre_script [sc_cfg_tool_task_get prescript] {
         puts "Sourcing pre script: ${sc_pre_script}"
-        source -echo $sc_pre_script
+        source $sc_pre_script
     }
 }
 utl::pop_metrics_stage

siliconcompiler/tools/openroad/scripts/apr/sc_antenna_repair.tcl

@@ -2,14 +2,14 @@
 # Reading SC Schema
 ###############################
 
-source ./sc_manifest.tcl > /dev/null
+source ./sc_manifest.tcl
 
 ###############################
 # Task Preamble
 ###############################
 
 set sc_refdir [sc_cfg_tool_task_get refdir]
-source -echo "$sc_refdir/apr/preamble.tcl"
+source "$sc_refdir/apr/preamble.tcl"
 
 ###############################
 # Report and Repair Antennas
@@ -48,4 +48,4 @@ estimate_parasitics -global_routing
 # Task Postamble
 ###############################
 
-source -echo "$sc_refdir/apr/postamble.tcl"
+source "$sc_refdir/apr/postamble.tcl"

siliconcompiler/tools/openroad/scripts/apr/sc_clock_tree_synthesis.tcl

@@ -2,14 +2,14 @@
 # Reading SC Schema
 ###############################
 
-source ./sc_manifest.tcl > /dev/null
+source ./sc_manifest.tcl
 
 ###############################
 # Task Preamble
 ###############################
 
 set sc_refdir [sc_cfg_tool_task_get refdir]
-source -echo "$sc_refdir/apr/preamble.tcl"
+source "$sc_refdir/apr/preamble.tcl"
 
 ###############################
 # Clock tree synthesis
@@ -66,4 +66,4 @@ estimate_parasitics -placement
 # Task Postamble
 ###############################
 
-source -echo "$sc_refdir/apr/postamble.tcl"
+source "$sc_refdir/apr/postamble.tcl"

siliconcompiler/tools/openroad/scripts/apr/sc_detailed_placement.tcl

@@ -2,14 +2,14 @@
 # Reading SC Schema
 ###############################
 
-source ./sc_manifest.tcl > /dev/null
+source ./sc_manifest.tcl
 
 ###############################
 # Task Preamble
 ###############################
 
 set sc_refdir [sc_cfg_tool_task_get refdir]
-source -echo "$sc_refdir/apr/preamble.tcl"
+source "$sc_refdir/apr/preamble.tcl"
 
 ###############################
 # DETAILED PLACEMENT
@@ -38,4 +38,4 @@ estimate_parasitics -placement
 # Task Postamble
 ###############################
 
-source -echo "$sc_refdir/apr/postamble.tcl"
+source "$sc_refdir/apr/postamble.tcl"

siliconcompiler/tools/openroad/scripts/apr/sc_detailed_route.tcl

@@ -2,14 +2,14 @@
 # Reading SC Schema
 ###############################
 
-source ./sc_manifest.tcl > /dev/null
+source ./sc_manifest.tcl
 
 ###############################
 # Task Preamble
 ###############################
 
 set sc_refdir [sc_cfg_tool_task_get refdir]
-source -echo "$sc_refdir/apr/preamble.tcl"
+source "$sc_refdir/apr/preamble.tcl"
 
 ###############################
 # Detailed Routing
@@ -78,4 +78,4 @@ estimate_parasitics -global_routing
 # Task Postamble
 ###############################
 
-source -echo "$sc_refdir/apr/postamble.tcl"
+source "$sc_refdir/apr/postamble.tcl"

siliconcompiler/tools/openroad/scripts/apr/sc_endcap_tapcell_insertion.tcl

@@ -2,14 +2,14 @@
 # Reading SC Schema
 ###############################
 
-source ./sc_manifest.tcl > /dev/null
+source ./sc_manifest.tcl
 
 ###############################
 # Task Preamble
 ###############################
 
 set sc_refdir [sc_cfg_tool_task_get refdir]
-source -echo "$sc_refdir/apr/preamble.tcl"
+source "$sc_refdir/apr/preamble.tcl"
 
 ###############################
 # Error checking
@@ -52,4 +52,4 @@ if {
 # Task Postamble
 ###############################
 
-source -echo "$sc_refdir/apr/postamble.tcl"
+source "$sc_refdir/apr/postamble.tcl"

siliconcompiler/tools/openroad/scripts/apr/sc_fillercell_insertion.tcl

@@ -2,14 +2,14 @@
 # Reading SC Schema
 ###############################
 
-source ./sc_manifest.tcl > /dev/null
+source ./sc_manifest.tcl
 
 ###############################
 # Task Preamble
 ###############################
 
 set sc_refdir [sc_cfg_tool_task_get refdir]
-source -echo "$sc_refdir/apr/preamble.tcl"
+source "$sc_refdir/apr/preamble.tcl"
 
 ###############################
 # Add fillers
@@ -24,4 +24,4 @@ estimate_parasitics -placement
 # Task Postamble
 ###############################
 
-source -echo "$sc_refdir/apr/postamble.tcl"
+source "$sc_refdir/apr/postamble.tcl"