siliconcompiler 0.32.1__py3-none-any.whl → 0.32.3__py3-none-any.whl

siliconcompiler/tools/openroad/scripts/common/reports.tcl

@@ -28,7 +28,7 @@ if { [sc_cfg_tool_task_check_in_list setup var reports] } {
         "report_tns"
     report_tns_metric -setup
 
-    if { [sc_check_version 19519] } {
+    if { [sc_check_version 19519] && [llength [all_clocks]] > 0 } {
         tee -quiet -file reports/timing/setup.histogram.rpt \
             "report_timing_histogram -num_bins 20 -setup"
     }
@@ -48,7 +48,7 @@ if { [sc_cfg_tool_task_check_in_list hold var reports] } {
 
     report_tns_metric -hold
 
-    if { [sc_check_version 19519] } {
+    if { [sc_check_version 19519] && [llength [all_clocks]] > 0 } {
         tee -quiet -file reports/timing/hold.histogram.rpt \
             "report_timing_histogram -num_bins 20 -hold"
     }
@@ -112,13 +112,24 @@ if { [sc_cfg_tool_task_check_in_list fmax var reports] } {
     }
     if { $fmax_metric == 0 } {
         # attempt to compute based on combinatorial path
+        set fmax_valid true
         set max_path [find_timing_paths -unconstrained -path_delay max]
-        set max_path_delay [$max_path data_arrival_time]
+        if { $max_path == "" } {
+            set fmax_valid false
+        } else {
+            set max_path_delay [$max_path data_arrival_time]
+        }
         set min_path [find_timing_paths -unconstrained -path_delay min]
-        set min_path_delay [$min_path data_arrival_time]
-        set path_delay [expr { $max_path_delay - min(0, $min_path_delay) }]
-        if { $path_delay > 0 } {
-            set fmax_metric [expr { 1.0 / $path_delay }]
+        if { $min_path == "" } {
+            set fmax_valid false
+        } else {
+            set min_path_delay [$min_path data_arrival_time]
+        }
+        if { $fmax_valid } {
+            set path_delay [expr { $max_path_delay - min(0, $min_path_delay) }]
+            if { $path_delay > 0 } {
+                set fmax_metric [expr { 1.0 / $path_delay }]
+            }
         }
     }
     if { $fmax_metric > 0 } {

siliconcompiler/tools/openroad/scripts/sc_rcx.tcl

@@ -2,7 +2,7 @@
 # Reading SC Schema
 ###############################
 
-source ./sc_manifest.tcl > /dev/null
+source ./sc_manifest.tcl
 
 ##############################
 # Schema Helper functions

siliconcompiler/tools/openroad/scripts/sc_rdlroute.tcl

@@ -2,7 +2,7 @@
 # Reading SC Schema
 ###############################
 
-source ./sc_manifest.tcl > /dev/null
+source ./sc_manifest.tcl
 
 ##############################
 # Schema Adapter

siliconcompiler/tools/openroad/scripts/sc_show.tcl

@@ -2,7 +2,7 @@
 # Reading SC Schema
 ###############################
 
-source ./sc_manifest.tcl > /dev/null
+source ./sc_manifest.tcl
 
 ##############################
 # Schema Adapter

siliconcompiler/tools/opensta/__init__.py

@@ -32,7 +32,7 @@ def setup(chip):
 
     chip.set('tool', tool, 'exe', 'sta')
     chip.set('tool', tool, 'vswitch', '-version')
-    chip.set('tool', tool, 'version', '>=v2.5.0', clobber=False)
+    chip.set('tool', tool, 'version', '>=v2.6.2', clobber=False)
     chip.set('tool', tool, 'format', 'tcl')
 
     targetlibs = get_libraries(chip, 'logic')

siliconcompiler/tools/opensta/scripts/sc_check_library.tcl

@@ -2,7 +2,7 @@
 # Reading SC Schema
 ###############################
 
-source ./sc_manifest.tcl > /dev/null
+source ./sc_manifest.tcl
 
 ##############################
 # Schema Adapter

siliconcompiler/tools/opensta/scripts/sc_procs.tcl

@@ -44,3 +44,19 @@ proc sc_display_report { report } {
     close $fid
     puts $report_content
 }
+
+proc sc_path_group { args } {
+    sta::parse_key_args "sc_path_group" args \
+        keys {-name -to -from} \
+        flags {}
+
+    sta::check_argc_eq0 "sc_path_group" $args
+
+    if { [llength $keys(-from)] == 0 } {
+        return
+    }
+    if { [llength $keys(-to)] == 0 } {
+        return
+    }
+    group_path -name $keys(-name) -from $keys(-from) -to $keys(-to)
+}

siliconcompiler/tools/opensta/scripts/sc_report_libraries.tcl

@@ -2,7 +2,7 @@
 # Reading SC Schema
 ###############################
 
-source ./sc_manifest.tcl > /dev/null
+source ./sc_manifest.tcl
 
 ##############################
 # Schema Adapter

siliconcompiler/tools/opensta/scripts/sc_timing.tcl

@@ -2,7 +2,7 @@
 # Reading SC Schema
 ###############################
 
-source ./sc_manifest.tcl > /dev/null
+source ./sc_manifest.tcl
 
 ##############################
 # Schema Adapter
@@ -38,6 +38,12 @@ foreach corner [dict keys [sc_cfg_get constraint timing]] {
 # MACROS
 set sc_macrolibs [sc_get_asic_libraries macro]
 
+###############################
+# Source helper functions
+###############################
+
+source "$sc_refdir/sc_procs.tcl"
+
 ###############################
 # Read Files
 ###############################
@@ -104,6 +110,34 @@ if { [file exists "inputs/${sc_design}.sdc"] } {
     read_sdc "${sdc}"
 }
 
+# Create path groups
+if { [llength [sta::path_group_names]] == 0 } {
+    sc_path_group -name in2out -from [all_inputs -no_clocks] -to [all_outputs]
+
+    if {
+        [llength [all_clocks]] == 1 ||
+        [lindex [sc_cfg_tool_task_get var unique_path_groups_per_clock] 0] == "false"
+    } {
+        sc_path_group -name in2reg -from [all_inputs -no_clocks] -to [all_registers]
+        sc_path_group -name reg2reg -from [all_registers] -to [all_registers]
+        sc_path_group -name reg2out -from [all_registers] -to [all_outputs]
+    } else {
+        foreach clock [all_clocks] {
+            set clk_name [get_property $clock name]
+            sc_path_group -name in2reg.${clk_name} \
+                -from [all_inputs -no_clocks] \
+                -to [all_registers -clock $clock]
+            sc_path_group -name reg2reg.${clk_name} \
+                -from [all_registers -clock $clock] \
+                -to [all_registers -clock $clock]
+            sc_path_group -name reg2out.${clk_name} \
+                -from [all_registers -clock $clock] \
+                -to [all_outputs]
+        }
+    }
+}
+puts "Timing path groups: [sta::path_group_names]"
+
 ###############################
 
 foreach corner $sc_scenarios {
@@ -116,12 +150,6 @@ foreach corner $sc_scenarios {
     }
 }
 
-###############################
-# Source helper functions
-###############################
-
-source "$sc_refdir/sc_procs.tcl"
-
 ###############################
 # Report Metrics
 ###############################

siliconcompiler/tools/opensta/timing.py

@@ -45,6 +45,10 @@ def setup(chip):
     set_tool_task_var(chip, param_key='top_n_paths',
                       default_value='10',
                       schelp='number of paths to report timing for')
+    set_tool_task_var(chip, param_key='unique_path_groups_per_clock',
+                      default_value=False,
+                      skip=['pdk', 'lib'],
+                      schelp='true/false, if true will generate separate path groups per clock')
 
     modes = get_timing_modes(chip)
 
@@ -165,13 +169,13 @@ def post_process(chip):
                     metric = None
                 elif metric in ('holdslack', 'setupslack'):
                     if slack:
-                        record_metric(chip, step, index, metric, float(slack.group(1)),
+                        record_metric(chip, step, index, metric, float(slack.group(1).split()[-1]),
                                       __report_map(chip, metric, logfile),
                                       source_unit=timescale)
                         metric = None
                 elif metric in ('setuptns', 'holdtns'):
                     if tns:
-                        record_metric(chip, step, index, metric, float(tns.group(1)),
+                        record_metric(chip, step, index, metric, float(tns.group(1).split()[-1]),
                                       __report_map(chip, metric, logfile),
                                       source_unit=timescale)
                         metric = None

siliconcompiler/tools/slang/__init__.py

@@ -151,7 +151,7 @@ def _get_driver(chip, options_func, ignored_diagnotics=None):
             driver.diagEngine.setSeverity(
                 getattr(pyslang.Diags, warning),
                 pyslang.DiagnosticSeverity.Ignored)
-        elif not chip.get('option', 'quiet', step=step, index=index):
+        else:
             chip.logger.warning(f'{warning} is not a valid slang category')
 
     if not ignored_diagnotics:
@@ -200,13 +200,12 @@ def _diagnostics(chip, driver, compilation):
 
                     report[report_level].append(line)
 
-    if not chip.get('option', 'quiet', step=step, index=index):
-        if report["warning"]:
-            for line in report["warning"]:
-                chip.logger.warning(line)
-        if report["error"]:
-            for line in report["error"]:
-                chip.logger.error(line)
+    if report["warning"]:
+        for line in report["warning"]:
+            chip.logger.warning(line)
+    if report["error"]:
+        for line in report["error"]:
+            chip.logger.error(line)
 
     diags.clearCounts()
     for diag in compilation.getAllDiagnostics():

siliconcompiler/tools/sv2v/sv2v.py

@@ -26,7 +26,10 @@ def make_docs(chip):
 
 def parse_version(stdout):
     # 0.0.7-130-g1aa30ea
-    return '-'.join(stdout.split('-')[:-1])
+    stdout = stdout.strip()
+    if '-' in stdout:
+        return '-'.join(stdout.split('-')[:-1])
+    return stdout
 
 
 ##################################################

siliconcompiler/tools/yosys/__init__.py

@@ -34,12 +34,9 @@ def setup(chip):
     ''' Tool specific function to run before step execution
     '''
 
-    # If the 'lock' bit is set, don't reconfigure.
-    tool = 'yosys'
-    refdir = 'tools/' + tool
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
-    _, task = get_tool_task(chip, step, index)
+    tool, task = get_tool_task(chip, step, index)
 
     # Standard Setup
     chip.set('tool', tool, 'exe', 'yosys')
@@ -54,7 +51,8 @@ def setup(chip):
         option.append('-C')
     option.append('-c')
     chip.set('tool', tool, 'task', task, 'option', option, step=step, index=index, clobber=False)
-    chip.set('tool', tool, 'task', task, 'refdir', refdir, step=step, index=index,
+    chip.set('tool', tool, 'task', task, 'refdir', os.path.join('tools', tool),
+             step=step, index=index,
              package='siliconcompiler', clobber=False)
     chip.set('tool', tool, 'task', task, 'regex', 'warnings', "Warning:",
              step=step, index=index, clobber=False)
@@ -76,38 +74,8 @@ def normalize_version(version):
     return version.replace('+', '-')
 
 
-def syn_setup(chip):
-    ''' Helper method for configs specific to synthesis tasks.
-    '''
-
-    # Generic tool setup.
-    setup(chip)
-
-    tool = 'yosys'
-    step = chip.get('arg', 'step')
-    index = chip.get('arg', 'index')
-    _, task = get_tool_task(chip, step, index)
-    design = chip.top()
-
-    # Set yosys script path.
-    chip.set('tool', tool, 'task', task, 'script', 'sc_syn.tcl',
-             step=step, index=index, clobber=False)
-
-    # Input/output requirements.
-    chip.set('tool', tool, 'task', task, 'input', design + '.v', step=step, index=index)
-    chip.set('tool', tool, 'task', task, 'output', design + '.vg', step=step, index=index)
-    chip.add('tool', tool, 'task', task, 'output', design + '.netlist.json', step=step, index=index)
-
-    chip.set('tool', tool, 'task', task, 'var', 'use_slang', False,
-             step=step, index=index,
-             clobber=False)
-    chip.set('tool', tool, 'task', task, 'var', 'use_slang',
-             'true/false, if true will attempt to use the slang frontend',
-             field='help')
-
-
 ##################################################
-def syn_post_process(chip):
+def synth_post_process(chip):
     ''' Tool specific function to run after step execution
     '''
 

siliconcompiler/tools/yosys/lec.py

@@ -1,7 +1,7 @@
 import re
 
 from siliconcompiler.tools.yosys import setup as setup_tool
-from siliconcompiler.tools.yosys.syn_asic import setup_asic, prepare_synthesis_libraries
+from siliconcompiler.tools.yosys.syn_asic import prepare_synthesis_libraries, setup_asic
 from siliconcompiler import sc_open
 from siliconcompiler.tools._common import get_tool_task, record_metric, input_provides
 
@@ -14,13 +14,12 @@ def setup(chip):
     # Generic tool setup.
     setup_tool(chip)
 
-    # Generic setup.
+    # Setup for asic
     setup_asic(chip)
 
-    tool = 'yosys'
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
-    _, task = get_tool_task(chip, step, index)
+    tool, task = get_tool_task(chip, step, index)
     design = chip.top()
 
     # Set yosys script path.

siliconcompiler/tools/yosys/{syn_asic.tcl → sc_synth_asic.tcl}

@@ -1,3 +1,84 @@
+###############################
+# Reading SC Schema
+###############################
+
+source ./sc_manifest.tcl
+
+yosys echo on
+
+###############################
+# Schema Adapter
+###############################
+
+set sc_tool yosys
+set sc_step [sc_cfg_get arg step]
+set sc_index [sc_cfg_get arg index]
+set sc_flow [sc_cfg_get option flow]
+set sc_task [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
+set sc_refdir [sc_cfg_tool_task_get refdir]
+
+####################
+# DESIGNER's CHOICE
+####################
+
+set sc_design [sc_top]
+set sc_flow [sc_cfg_get option flow]
+set sc_optmode [sc_cfg_get option optmode]
+set sc_pdk [sc_cfg_get option pdk]
+
+########################################################
+# Helper function
+########################################################
+
+source "$sc_refdir/procs.tcl"
+
+########################################################
+# Design Inputs
+########################################################
+
+set input_verilog "inputs/$sc_design.v"
+if { ![file exists $input_verilog] } {
+    set input_verilog []
+    if { [sc_cfg_exists input rtl systemverilog] } {
+        lappend input_verilog {*}[sc_cfg_get input rtl systemverilog]
+    }
+    if { [sc_cfg_exists input rtl verilog] } {
+        lappend input_verilog {*}[sc_cfg_get input rtl verilog]
+    }
+}
+
+if { [lindex [sc_cfg_tool_task_get var use_slang] 0] == "true" && [sc_load_plugin slang] } {
+    # This needs some reordering of loaded to ensure blackboxes are handled
+    # before this
+    set slang_params []
+    if { [sc_cfg_exists option param] } {
+        dict for {key value} [sc_cfg_get option param] {
+            if { ![string is integer $value] } {
+                set value [concat \"$value\"]
+            }
+
+            lappend slang_params -G "${key}=${value}"
+        }
+    }
+    yosys read_slang \
+        -D SYNTHESIS \
+        --keep-hierarchy \
+        --top $sc_design \
+        {*}$slang_params \
+        {*}$input_verilog
+} else {
+    # Use -noblackbox to correctly interpret empty modules as empty,
+    # actual black boxes are read in later
+    # https://github.com/YosysHQ/yosys/issues/1468
+    yosys read_verilog -noblackbox -sv {*}$input_verilog
+
+    ########################################################
+    # Override top level parameters
+    ########################################################
+
+    sc_apply_params
+}
+
 ####################
 # Helper functions
 ####################
@@ -416,3 +497,9 @@ foreach lib_file "$sc_libraries $sc_macro_libraries" {
 yosys echo off
 yosys tee -o ./reports/stat.json stat -json -top $sc_design {*}$stat_libs
 yosys echo on
+
+########################################################
+# Write Netlist
+########################################################
+yosys write_verilog -noexpr -nohex -nodec "outputs/${sc_design}.vg"
+yosys write_json "outputs/${sc_design}.netlist.json"

siliconcompiler/tools/yosys/{syn_fpga.tcl → sc_synth_fpga.tcl}

@@ -1,3 +1,79 @@
+###############################
+# Reading SC Schema
+###############################
+
+source ./sc_manifest.tcl
+
+yosys echo on
+
+###############################
+# Schema Adapter
+###############################
+
+set sc_tool yosys
+set sc_step [sc_cfg_get arg step]
+set sc_index [sc_cfg_get arg index]
+set sc_flow [sc_cfg_get option flow]
+set sc_task [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
+set sc_refdir [sc_cfg_tool_task_get refdir]
+
+####################
+# DESIGNER's CHOICE
+####################
+
+set sc_design [sc_top]
+set sc_flow [sc_cfg_get option flow]
+set sc_optmode [sc_cfg_get option optmode]
+set sc_pdk [sc_cfg_get option pdk]
+
+########################################################
+# Helper function
+########################################################
+
+source "$sc_refdir/procs.tcl"
+
+########################################################
+# Design Inputs
+########################################################
+
+# TODO: the original OpenFPGA synth script used read_verilog with -nolatches. Is
+# that a flag we might want here?
+
+set input_verilog "inputs/$sc_design.v"
+if { [file exists $input_verilog] } {
+    if { [lindex [sc_cfg_tool_task_get var use_slang] 0] == "true" && [sc_load_plugin slang] } {
+        # This needs some reordering of loaded to ensure blackboxes are handled
+        # before this
+        set slang_params []
+        if { [sc_cfg_exists option param] } {
+            dict for {key value} [sc_cfg_get option param] {
+                if { ![string is integer $value] } {
+                    set value [concat \"$value\"]
+                }
+
+                lappend slang_params -G "${key}=${value}"
+            }
+        }
+        yosys read_slang \
+            -D SYNTHESIS \
+            --keep-hierarchy \
+            --top $sc_design \
+            {*}$slang_params \
+            $input_verilog
+    } else {
+        # Use -noblackbox to correctly interpret empty modules as empty,
+        # actual black boxes are read in later
+        # https://github.com/YosysHQ/yosys/issues/1468
+        yosys read_verilog -noblackbox -sv $input_verilog
+
+        ########################################################
+        # Override top level parameters
+        ########################################################
+
+        sc_apply_params
+    }
+}
+
 ####################
 # Helper functions
 ####################
@@ -241,4 +317,6 @@ yosys echo on
 ########################################################
 # Write Netlist
 ########################################################
+yosys write_verilog -noexpr -nohex -nodec "outputs/${sc_design}.vg"
+yosys write_json "outputs/${sc_design}.netlist.json"
 yosys write_blif "outputs/${sc_design}.blif"

siliconcompiler/tools/yosys/syn_asic.py

@@ -1,5 +1,4 @@
-
-from siliconcompiler.tools.yosys import syn_setup, syn_post_process
+from siliconcompiler.tools.yosys import synth_post_process, setup as tool_setup
 import os
 import json
 import re
@@ -9,7 +8,7 @@ from siliconcompiler import utils
 from siliconcompiler.tools._common.asic import set_tool_task_var, get_libraries, get_mainlib, \
     CellArea
 from siliconcompiler.tools._common.asic_clock import get_clock_period
-from siliconcompiler.tools._common import get_tool_task
+from siliconcompiler.tools._common import get_tool_task, input_provides, add_require_input
 
 
 def make_docs(chip):
@@ -22,22 +21,48 @@ def setup(chip):
     Perform ASIC synthesis
     '''
 
+    tool_setup(chip)
+
     # Generic synthesis task setup.
-    syn_setup(chip)
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+    design = chip.top()
+
+    # Set yosys script path.
+    chip.set('tool', tool, 'task', task, 'script', 'sc_synth_asic.tcl',
+             step=step, index=index, clobber=False)
+
+    # Input/output requirements.
+    if f'{design}.v' in input_provides(chip, step, index):
+        chip.set('tool', tool, 'task', task, 'input', design + '.v', step=step, index=index)
+    else:
+        added = False
+        added |= add_require_input(chip, 'input', 'rtl', 'systemverilog',
+                                   include_library_files=False)
+        added |= add_require_input(chip, 'input', 'rtl', 'verilog',
+                                   include_library_files=False)
+        if not added:
+            chip.add('tool', tool, 'task', task, 'require', 'input,rtl,verilog')
+    chip.set('tool', tool, 'task', task, 'output', design + '.vg', step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', design + '.netlist.json', step=step, index=index)
+
+    chip.set('tool', tool, 'task', task, 'var', 'use_slang', False,
+             step=step, index=index,
+             clobber=False)
+    chip.set('tool', tool, 'task', task, 'var', 'use_slang',
+             'true/false, if true will attempt to use the slang frontend',
+             field='help')
 
-    # ASIC-specific setup.
     setup_asic(chip)
 
 
 def setup_asic(chip):
-    ''' Helper method for configs specific to ASIC steps (both syn and lec).
-    '''
-
-    tool = 'yosys'
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
-    _, task = get_tool_task(chip, step, index)
+    tool, task = get_tool_task(chip, step, index)
 
+    # Setup ASIC params
     chip.add('tool', tool, 'task', task, 'require',
              ",".join(['asic', 'logiclib']),
              step=step, index=index)
@@ -506,7 +531,7 @@ def pre_process(chip):
 
 
 def post_process(chip):
-    syn_post_process(chip)
+    synth_post_process(chip)
     _generate_cell_area_report(chip)