siliconcompiler 0.29.4__py3-none-any.whl → 0.31.0__py3-none-any.whl

siliconcompiler/tools/openroad/scripts/common/reports.tcl

@@ -70,10 +70,17 @@ if { [sc_cfg_tool_task_check_in_list drv_violations var reports] } {
     tee -file reports/timing/drv_violators.rpt \
         "report_check_types -max_slew -max_capacitance -max_fanout -violators"
     report_erc_metrics
+}
 
-    puts "$PREFIX floating nets"
-    tee -file reports/floating_nets.rpt \
-        "report_floating_nets -verbose"
+puts "$PREFIX floating nets"
+tee -file reports/floating_nets.rpt \
+    "report_floating_nets -verbose"
+if { [sc_check_version 19048] } {
+    puts "$PREFIX overdriven nets"
+    tee -file reports/overdriven_nets.rpt \
+        "report_overdriven_nets -verbose"
+    tee -file reports/overdriven_nets_with_parallel.rpt \
+        "report_overdriven_nets -include_parallel_driven -verbose"
 }
 
 utl::metric_int "timing__clocks" [llength [all_clocks]]
@@ -93,6 +100,17 @@ if { [sc_cfg_tool_task_check_in_list fmax var reports] } {
         puts "$clk_name fmax = [format %.2f [expr { $fmax / 1e6 }]] MHz"
         set fmax_metric [expr { max($fmax_metric, $fmax) }]
     }
+    if { $fmax_metric == 0 } {
+        # attempt to compute based on combinatorial path
+        set max_path [find_timing_paths -unconstrained -path_delay max]
+        set max_path_delay [$max_path data_arrival_time]
+        set min_path [find_timing_paths -unconstrained -path_delay min]
+        set min_path_delay [$min_path data_arrival_time]
+        set path_delay [expr { $max_path_delay - min(0, $min_path_delay) }]
+        if { $path_delay > 0 } {
+            set fmax_metric [expr { 1.0 / $path_delay }]
+        }
+    }
     if { $fmax_metric > 0 } {
         utl::metric_float "timing__fmax" $fmax_metric
     }
@@ -162,6 +180,10 @@ foreach markerdb [[ord::get_db_block] getMarkerCategories] {
         continue
     }
 
+    if { [lsearch -exact $sc_starting_markers [$markerdb getName]] != -1 } {
+        continue
+    }
+
     $markerdb writeTR "reports/markers/${sc_design}.[$markerdb getName].rpt"
     $markerdb writeJSON "reports/markers/${sc_design}.[$markerdb getName].json"
 }

siliconcompiler/tools/openroad/scripts/common/write_images.tcl

@@ -210,6 +210,24 @@ proc sc_image_placement_density { } {
         "placement density"
 }
 
+proc sc_image_module_view { } {
+    if { ![sc_has_placed_instances] } {
+        return
+    }
+
+    if { [llength [[ord::get_db_block] getModInsts]] < 1 } {
+        return
+    }
+
+    global sc_design
+    sc_image_setup_default
+
+    gui::set_display_controls "Misc/Module view" visible true
+    gui::set_display_controls "Nets/*" visible false
+
+    sc_save_image "module view" reports/images/${sc_design}.modules.png
+}
+
 proc sc_image_clocks { } {
     if { ![sc_has_placed_instances] } {
         return
@@ -333,12 +351,18 @@ proc sc_image_markers { } {
     global sc_design
     sc_image_setup_default
 
+    global sc_starting_markers
+
     file mkdir reports/images/markers
     foreach markerdb [[ord::get_db_block] getMarkerCategories] {
         if { [$markerdb getMarkerCount] == 0 } {
             continue
         }
 
+        if { [lsearch -exact $sc_starting_markers [$markerdb getName]] != -1 } {
+            continue
+        }
+
         gui::select_marker_category $markerdb
 
         sc_save_image \
@@ -359,6 +383,10 @@ sc_image_everything
 sc_image_placement
 sc_image_routing
 
+if { [sc_cfg_tool_task_check_in_list module_view var reports] } {
+    sc_image_module_view
+}
+
 # Markers
 sc_image_markers
 

siliconcompiler/tools/yosys/__init__.py

@@ -98,6 +98,13 @@ def syn_setup(chip):
     chip.set('tool', tool, 'task', task, 'output', design + '.vg', step=step, index=index)
     chip.add('tool', tool, 'task', task, 'output', design + '.netlist.json', step=step, index=index)
 
+    chip.set('tool', tool, 'task', task, 'var', 'use_slang', False,
+             step=step, index=index,
+             clobber=False)
+    chip.set('tool', tool, 'task', task, 'var', 'use_slang',
+             'true/false, if true will attempt to use the slang frontend',
+             field='help')
+
 
 ##################################################
 def syn_post_process(chip):

siliconcompiler/tools/yosys/sc_syn.tcl

@@ -39,32 +39,41 @@ source "$sc_refdir/procs.tcl"
 # TODO: the original OpenFPGA synth script used read_verilog with -nolatches. Is
 # that a flag we might want here?
 
-# If UHDM, ilang, or Verilog inputs exist, read them in (this allows mixed
-# inputs in designs). UHDM requires a version of Yosys built with this support.
-
-if { [file exists "inputs/$sc_design.uhdm"] } {
-    set input_uhdm "inputs/$sc_design.uhdm"
-    yosys read_uhdm $input_uhdm
-}
-if { [file exists "inputs/$sc_design.ilang"] } {
-    set input_ilang "inputs/$sc_design.ilang"
-    yosys read_ilang $input_ilang
-}
-
-if { [file exists "inputs/$sc_design.v"] } {
-    set input_verilog "inputs/$sc_design.v"
-    # Use -noblackbox to correctly interpret empty modules as empty,
-    # actual black boxes are read in later
-    # https://github.com/YosysHQ/yosys/issues/1468
-    yosys read_verilog -noblackbox -sv $input_verilog
+set input_verilog "inputs/$sc_design.v"
+if { [file exists $input_verilog] } {
+    if { [lindex [sc_cfg_tool_task_get var use_slang] 0] == "true" && [sc_load_plugin slang] } {
+        # This needs some reordering of loaded to ensure blackboxes are handled
+        # before this
+        set slang_params []
+        if { [sc_cfg_exists option param] } {
+            dict for {key value} [sc_cfg_get option param] {
+                if { ![string is integer $value] } {
+                    set value [concat \"$value\"]
+                }
+
+                lappend slang_params -G "${key}=${value}"
+            }
+        }
+        yosys read_slang \
+            -D SYNTHESIS \
+            --keep-hierarchy \
+            --top $sc_design \
+            {*}$slang_params \
+            $input_verilog
+    } else {
+        # Use -noblackbox to correctly interpret empty modules as empty,
+        # actual black boxes are read in later
+        # https://github.com/YosysHQ/yosys/issues/1468
+        yosys read_verilog -noblackbox -sv $input_verilog
+
+        ########################################################
+        # Override top level parameters
+        ########################################################
+
+        sc_apply_params
+    }
 }
 
-########################################################
-# Override top level parameters
-########################################################
-
-sc_apply_params
-
 ########################################################
 # Synthesis based on mode
 ########################################################

siliconcompiler/tools/yosys/syn_asic.py

@@ -217,6 +217,33 @@ def setup_asic(chip):
     chip.set('tool', tool, 'task', task, 'file', 'synth_extra_map',
              'Files used in synthesis to perform additional techmapping', field='help')
 
+    chip.set('tool', tool, 'task', task, 'var', 'lock_design', False,
+             step=step, index=index,
+             clobber=False)
+    chip.set('tool', tool, 'task', task, 'var', 'lock_design',
+             'true/false, if true will attempt to lock the design with moosic',
+             field='help')
+    chip.add('tool', tool, 'task', task, 'require',
+             ",".join(['tool', tool, 'task', task, 'var', 'lock_design']),
+             step=step, index=index)
+    chip.set('tool', tool, 'task', task, 'var', 'lock_design_key',
+             'lock locking key',
+             field='help')
+    chip.set('tool', tool, 'task', task, 'var', 'lock_design_port', 'moosic_key',
+             step=step, index=index,
+             clobber=False)
+    chip.set('tool', tool, 'task', task, 'var', 'lock_design_port',
+             'lock locking port name',
+             field='help')
+    if chip.get('tool', tool, 'task', task, 'var', 'lock_design', step=step, index=index)[0] == \
+            'true':
+        chip.add('tool', tool, 'task', task, 'require',
+                 ",".join(['tool', tool, 'task', task, 'var', 'lock_design_key']),
+                 step=step, index=index)
+        chip.add('tool', tool, 'task', task, 'require',
+                 ",".join(['tool', tool, 'task', task, 'var', 'lock_design_port']),
+                 step=step, index=index)
+
 
 ################################
 # mark cells dont use and format liberty files for yosys and abc

siliconcompiler/tools/yosys/syn_asic.tcl

@@ -217,6 +217,33 @@ if { !$flatten_design && [lindex [sc_cfg_tool_task_get var auto_flatten] 0] == "
 # Finish synthesis
 yosys synth {*}$synth_args -top $sc_design -run fine:check
 
+# Logic locking
+if { [lindex [sc_cfg_tool_task_get var lock_design] 0] == "true" } {
+    if { [sc_load_plugin moosic] } {
+        # moosic cannot handle hierarchy
+        foreach module [get_modules "*"] {
+            yosys select -module $module
+            yosys setattr -mod -unset keep_hierarchy
+            yosys select -clear
+        }
+        yosys flatten
+        yosys opt -fast
+
+        set ll_port [lindex [sc_cfg_tool_task_get var lock_design_port] 0]
+        set ll_key [lindex [sc_cfg_tool_task_get var lock_design_key] 0]
+        set ll_bits [expr { 4 * [string length $ll_key] }]
+        yosys select -module $sc_design
+        yosys logic_locking \
+            -nb-locked $ll_bits \
+            -key $ll_key \
+            -port-name $ll_port
+        yosys tee -o reports/logic_locking.rpt {ll_show}
+        yosys select -clear
+    } else {
+        puts "ERROR: unable to load moosic"
+    }
+}
+
 # https://github.com/hdl/bazel_rules_hdl/blob/4cca75f32a3869a57c0635bc7426a696a15ec143/synthesis/synth.tcl#L54C1-L58C26
 # Remove $print cells.  These cells represent Verilog $display() tasks.
 # Some place and route tools cannot handle these in the output Verilog,

siliconcompiler/toolscripts/_tools.json

@@ -1,7 +1,7 @@
 {
   "openroad": {
     "git-url": "https://github.com/The-OpenROAD-Project/OpenROAD.git",
-    "git-commit": "6645a5370f109cff49d7a735d81dae239df387c0",
+    "git-commit": "6e6fccbbe0ffbe683a51de3ecac2a24958a53fa1",
     "docker-cmds": [
       "# Remove OR-Tools files",
       "RUN rm -f $SC_PREFIX/Makefile $SC_PREFIX/README.md",
@@ -45,7 +45,7 @@
   },
   "sv2v": {
     "git-url": "https://github.com/zachjs/sv2v.git",
-    "git-commit": "aa0a885699ca8f4fc1d07ef34fb041c6f37b1ba3",
+    "git-commit": "5d5723f65dd4501d17004736d7d048bea7ef2339",
     "auto-update": true
   },
   "verilator": {
@@ -91,7 +91,7 @@
   },
   "yosys": {
     "git-url": "https://github.com/YosysHQ/yosys.git",
-    "git-commit": "v0.49",
+    "git-commit": "v0.50",
     "version-prefix": "",
     "auto-update": true
   },
@@ -128,7 +128,7 @@
     "auto-update": false
   },
   "slang": {
-    "git-commit": "v7.0",
+    "git-commit": "v8.0",
     "git-url": "https://github.com/MikePopoloski/slang.git",
     "auto-update": true
   },
@@ -136,5 +136,17 @@
     "git-commit": "v3.3.116",
     "git-url": "https://github.com/gtkwave/gtkwave.git",
     "auto-update": false
+  },
+  "yosys-slang": {
+    "git-url": "https://github.com/povik/yosys-slang.git",
+    "git-commit": "0adba99ea43331235506b9b154c78a401f4fe9b6",
+    "docker-depends": "yosys",
+    "auto-update": true
+  },
+  "yosys-moosic": {
+    "git-url": "https://github.com/gadfort/moosic-yosys-plugin.git",
+    "git-commit": "5dd1d8a60d0cc7228be856350bb90faad24dae9e",
+    "docker-depends": "yosys",
+    "auto-update": true
   }
 }

siliconcompiler/toolscripts/rhel8/install-yosys-moosic.sh

@@ -0,0 +1,17 @@
+#!/bin/bash
+
+set -e
+
+# Get directory of script
+src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
+
+mkdir -p deps
+cd deps
+
+git clone $(python3 ${src_path}/_tools.py --tool yosys-moosic --field git-url) yosys-moosic
+cd yosys-moosic
+git checkout $(python3 ${src_path}/_tools.py --tool yosys-moosic --field git-commit)
+
+make -j$(nproc)
+sudo PATH="$PATH" make install
+cd -

siliconcompiler/toolscripts/rhel8/install-yosys-slang.sh

@@ -0,0 +1,22 @@
+#!/bin/bash
+
+set -e
+
+# Get directory of script
+src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
+
+mkdir -p deps
+cd deps
+
+python3 -m venv .yosys-slang --clear
+. .yosys-slang/bin/activate
+python3 -m pip install cmake
+
+git clone $(python3 ${src_path}/_tools.py --tool yosys-slang --field git-url) yosys-slang
+cd yosys-slang
+git checkout $(python3 ${src_path}/_tools.py --tool yosys-slang --field git-commit)
+git submodule update --init --recursive
+
+make -j$(nproc)
+sudo PATH="$PATH" make install
+cd -

siliconcompiler/toolscripts/rhel9/install-openroad.sh

@@ -19,7 +19,7 @@ deps_args=""
 if [ ! -z ${PREFIX} ]; then
     deps_args="-prefix=$PREFIX"
 fi
-sudo ./etc/DependencyInstaller.sh $deps_args
+sudo ./etc/DependencyInstaller.sh -all $deps_args
 
 cmake_args="-DENABLE_TESTS=OFF"
 if [ ! -z ${PREFIX} ]; then

siliconcompiler/toolscripts/rhel9/install-yosys-moosic.sh

@@ -0,0 +1,17 @@
+#!/bin/bash
+
+set -e
+
+# Get directory of script
+src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
+
+mkdir -p deps
+cd deps
+
+git clone $(python3 ${src_path}/_tools.py --tool yosys-moosic --field git-url) yosys-moosic
+cd yosys-moosic
+git checkout $(python3 ${src_path}/_tools.py --tool yosys-moosic --field git-commit)
+
+make -j$(nproc)
+sudo PATH="$PATH" make install
+cd -

siliconcompiler/toolscripts/rhel9/install-yosys-slang.sh

@@ -0,0 +1,22 @@
+#!/bin/bash
+
+set -e
+
+# Get directory of script
+src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
+
+mkdir -p deps
+cd deps
+
+python3 -m venv .yosys-slang --clear
+. .yosys-slang/bin/activate
+python3 -m pip install cmake
+
+git clone $(python3 ${src_path}/_tools.py --tool yosys-slang --field git-url) yosys-slang
+cd yosys-slang
+git checkout $(python3 ${src_path}/_tools.py --tool yosys-slang --field git-commit)
+git submodule update --init --recursive
+
+make -j$(nproc)
+sudo PATH="$PATH" make install
+cd -

siliconcompiler/toolscripts/ubuntu20/install-openroad.sh

@@ -16,7 +16,7 @@ deps_args=""
 if [ ! -z ${PREFIX} ]; then
     deps_args="-prefix=$PREFIX"
 fi
-sudo ./etc/DependencyInstaller.sh $deps_args
+sudo ./etc/DependencyInstaller.sh -all $deps_args
 
 cmake_args="-DENABLE_TESTS=OFF"
 if [ ! -z ${PREFIX} ]; then

siliconcompiler/toolscripts/ubuntu20/install-yosys-moosic.sh

@@ -0,0 +1,17 @@
+#!/bin/bash
+
+set -e
+
+# Get directory of script
+src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
+
+mkdir -p deps
+cd deps
+
+git clone $(python3 ${src_path}/_tools.py --tool yosys-moosic --field git-url) yosys-moosic
+cd yosys-moosic
+git checkout $(python3 ${src_path}/_tools.py --tool yosys-moosic --field git-commit)
+
+make -j$(nproc)
+sudo PATH="$PATH" make install
+cd -

siliconcompiler/toolscripts/ubuntu20/install-yosys-slang.sh

@@ -0,0 +1,22 @@
+#!/bin/bash
+
+set -e
+
+# Get directory of script
+src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
+
+mkdir -p deps
+cd deps
+
+python3 -m venv .yosys-slang --clear
+. .yosys-slang/bin/activate
+python3 -m pip install cmake
+
+git clone $(python3 ${src_path}/_tools.py --tool yosys-slang --field git-url) yosys-slang
+cd yosys-slang
+git checkout $(python3 ${src_path}/_tools.py --tool yosys-slang --field git-commit)
+git submodule update --init --recursive
+
+make -j$(nproc)
+sudo PATH="$PATH" make install
+cd -

siliconcompiler/toolscripts/ubuntu22/install-openroad.sh

@@ -16,7 +16,7 @@ deps_args=""
 if [ ! -z ${PREFIX} ]; then
     deps_args="-prefix=$PREFIX"
 fi
-sudo ./etc/DependencyInstaller.sh $deps_args
+sudo ./etc/DependencyInstaller.sh -all $deps_args
 
 cmake_args="-DENABLE_TESTS=OFF"
 if [ ! -z ${PREFIX} ]; then

siliconcompiler/toolscripts/ubuntu22/install-yosys-moosic.sh

@@ -0,0 +1,17 @@
+#!/bin/bash
+
+set -e
+
+# Get directory of script
+src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
+
+mkdir -p deps
+cd deps
+
+git clone $(python3 ${src_path}/_tools.py --tool yosys-moosic --field git-url) yosys-moosic
+cd yosys-moosic
+git checkout $(python3 ${src_path}/_tools.py --tool yosys-moosic --field git-commit)
+
+make -j$(nproc)
+sudo PATH="$PATH" make install
+cd -

siliconcompiler/toolscripts/ubuntu22/install-yosys-slang.sh

@@ -0,0 +1,22 @@
+#!/bin/bash
+
+set -e
+
+# Get directory of script
+src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
+
+mkdir -p deps
+cd deps
+
+python3 -m venv .yosys-slang --clear
+. .yosys-slang/bin/activate
+python3 -m pip install cmake
+
+git clone $(python3 ${src_path}/_tools.py --tool yosys-slang --field git-url) yosys-slang
+cd yosys-slang
+git checkout $(python3 ${src_path}/_tools.py --tool yosys-slang --field git-commit)
+git submodule update --init --recursive
+
+make -j$(nproc)
+sudo PATH="$PATH" make install
+cd -

siliconcompiler/toolscripts/ubuntu24/install-openroad.sh

@@ -16,7 +16,7 @@ deps_args=""
 if [ ! -z ${PREFIX} ]; then
     deps_args="-prefix=$PREFIX"
 fi
-sudo ./etc/DependencyInstaller.sh $deps_args
+sudo ./etc/DependencyInstaller.sh -all $deps_args
 
 cmake_args="-DENABLE_TESTS=OFF"
 if [ ! -z ${PREFIX} ]; then

siliconcompiler/toolscripts/ubuntu24/install-yosys-moosic.sh

@@ -0,0 +1,17 @@
+#!/bin/bash
+
+set -e
+
+# Get directory of script
+src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
+
+mkdir -p deps
+cd deps
+
+git clone $(python3 ${src_path}/_tools.py --tool yosys-moosic --field git-url) yosys-moosic
+cd yosys-moosic
+git checkout $(python3 ${src_path}/_tools.py --tool yosys-moosic --field git-commit)
+
+make -j$(nproc)
+sudo PATH="$PATH" make install
+cd -

siliconcompiler/toolscripts/ubuntu24/install-yosys-slang.sh

@@ -0,0 +1,22 @@
+#!/bin/bash
+
+set -e
+
+# Get directory of script
+src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
+
+mkdir -p deps
+cd deps
+
+python3 -m venv .yosys-slang --clear
+. .yosys-slang/bin/activate
+python3 -m pip install cmake
+
+git clone $(python3 ${src_path}/_tools.py --tool yosys-slang --field git-url) yosys-slang
+cd yosys-slang
+git checkout $(python3 ${src_path}/_tools.py --tool yosys-slang --field git-commit)
+git submodule update --init --recursive
+
+make -j$(nproc)
+sudo PATH="$PATH" make install
+cd -

siliconcompiler/utils/__init__.py

@@ -130,6 +130,12 @@ def get_default_iomap():
     report_drc = ('lyrdb', 'ascii')
     report_log = ('log',)
 
+    # Images
+    image_dot = ('dot', 'xdot')
+    image_png = ('png',)
+    image_jpg = ('jpg', 'jpeg')
+    image_bmp = ('bmp',)
+
     # Build default map with fileset and type
     default_iomap = {}
     default_iomap.update({ext: ('hll', 'c') for ext in hll_c})
@@ -169,6 +175,11 @@ def get_default_iomap():
     default_iomap.update({ext: ('report', 'drc') for ext in report_drc})
     default_iomap.update({ext: ('report', 'log') for ext in report_log})
 
+    default_iomap.update({ext: ('image', 'dot') for ext in image_dot})
+    default_iomap.update({ext: ('image', 'png') for ext in image_png})
+    default_iomap.update({ext: ('image', 'jpeg') for ext in image_jpg})
+    default_iomap.update({ext: ('image', 'bitmap') for ext in image_bmp})
+
     return default_iomap
 
 
@@ -321,17 +332,20 @@ def grep(chip, args, line):
 
 
 #######################################
-def _resolve_env_vars(chip, filepath):
+def _resolve_env_vars(chip, filepath, step, index):
     if not filepath:
         return None
 
     env_save = os.environ.copy()
-    for env in chip.getkeys('option', 'env'):
-        os.environ[env] = chip.get('option', 'env', env)
+
+    os.environ.update(get_env_vars(chip, step, index))
     resolved_path = os.path.expandvars(filepath)
+
     os.environ.clear()
     os.environ.update(env_save)
 
+    resolved_path = os.path.expanduser(resolved_path)
+
     # variables that don't exist in environment get ignored by `expandvars`,
     # but we can do our own error checking to ensure this doesn't result in
     # silent bugs
@@ -342,8 +356,31 @@ def _resolve_env_vars(chip, filepath):
     return resolved_path
 
 
+#######################################
+def get_env_vars(chip, step, index):
+    '''
+    Returns a dictionary of environmental variables from the manifest
+    '''
+
+    schema_env = {}
+    for env in chip.getkeys('option', 'env'):
+        schema_env[env] = chip.get('option', 'env', env)
+
+    flow = chip.get('option', 'flow')
+    if step is not None and index is not None and flow:
+        tool = chip.get('flowgraph', flow, step, str(index), 'tool')
+        task = chip.get('flowgraph', flow, step, str(index), 'task')
+
+        if chip.valid('tool', tool, 'task', task, 'env'):
+            for env in chip.getkeys('tool', tool, 'task', task, 'env'):
+                schema_env[env] = chip.get('tool', tool, 'task', task, 'env', env,
+                                           step=step, index=index)
+
+    return schema_env
+
+
 ###########################################################################
-def find_sc_file(chip, filename, missing_ok=False, search_paths=None):
+def find_sc_file(chip, filename, missing_ok=False, search_paths=None, step=None, index=None):
     """
     Returns the absolute path for the filename provided.
 
@@ -359,6 +396,8 @@ def find_sc_file(chip, filename, missing_ok=False, search_paths=None):
             found, rather than returning None.
         search_paths (list): List of directories to search under instead of
             the defaults.
+        step (str): Step name
+        index (str): Index
 
     Returns:
         Returns absolute path of 'filename' if found, otherwise returns
@@ -374,7 +413,7 @@ def find_sc_file(chip, filename, missing_ok=False, search_paths=None):
         return None
 
     # Replacing environment variables
-    filename = _resolve_env_vars(chip, filename)
+    filename = _resolve_env_vars(chip, filename, step, index)
 
     # If we have an absolute path, pass-through here
     if os.path.isabs(filename) and os.path.exists(filename):