siliconcompiler 0.29.3__py3-none-any.whl → 0.30.0__py3-none-any.whl

siliconcompiler/tools/openroad/scripts/apr/sc_global_route.tcl

@@ -16,6 +16,8 @@ source -echo "$sc_refdir/apr/preamble.tcl"
 ###############################
 
 if { [lindex [sc_cfg_tool_task_get {var} grt_use_pin_access] 0] == "true" } {
+    sc_setup_detailed_route
+
     set sc_minmetal [sc_cfg_get pdk $sc_pdk minlayer $sc_stackup]
     set sc_minmetal [sc_get_layer_name $sc_minmetal]
     set sc_maxmetal [sc_cfg_get pdk $sc_pdk maxlayer $sc_stackup]
@@ -45,11 +47,19 @@ if { [lindex [sc_cfg_tool_task_get {var} grt_allow_overflow] 0] == "true" } {
     lappend sc_grt_arguments "-allow_overflow"
 }
 
-global_route -guide_file "reports/route.guide" \
-    -congestion_iterations [lindex [sc_cfg_tool_task_get {var} grt_overflow_iter] 0] \
-    -congestion_report_file "reports/${sc_design}_congestion.rpt" \
-    -verbose \
-    {*}$sc_grt_arguments
+if {
+    [catch {
+        global_route -guide_file "reports/route.guide" \
+            -congestion_iterations [lindex [sc_cfg_tool_task_get {var} grt_overflow_iter] 0] \
+            -congestion_report_file "reports/${sc_design}_congestion.rpt" \
+            -verbose \
+            {*}$sc_grt_arguments
+    }]
+} {
+    write_db "reports/${sc_design}.globalroute-error.odb"
+    utl::error FLW 1 \
+        "Global routing failed, saving database to reports/${sc_design}.globalroute-error.odb"
+}
 
 # estimate for metrics
 estimate_parasitics -global_routing

siliconcompiler/tools/openroad/scripts/apr/sc_init_floorplan.tcl

@@ -25,6 +25,7 @@ if { [sc_cfg_tool_task_exists {file} global_connect] } {
         source $global_connect
     }
 }
+tee -file reports/global_connections.rpt {report_global_connect}
 
 ###############################
 # Initialize floorplan

siliconcompiler/tools/openroad/scripts/apr/sc_macro_placement.tcl

@@ -11,6 +11,14 @@ source ./sc_manifest.tcl > /dev/null
 set sc_refdir [sc_cfg_tool_task_get refdir]
 source -echo "$sc_refdir/apr/preamble.tcl"
 
+###############################
+# Macro placement constraints
+###############################
+foreach script [sc_cfg_tool_task_get file rtlmp_constraints] {
+    puts "Sourcing macro placement constraints: $script"
+    source -echo $script
+}
+
 # Need to check if we have any macros before performing macro placement,
 # since we get an error otherwise.
 if { [sc_design_has_unplaced_macros] } {
@@ -94,7 +102,7 @@ if { [sc_design_has_unplaced_macros] } {
         -report_directory reports/rtlmp \
         -halo_width $halo_x \
         -halo_height $halo_y \
-        -target_util [sc_global_placement_density] \
+        -target_util [sc_global_placement_density -exclude_padding] \
         {*}$rtlmp_args
 }
 

siliconcompiler/tools/openroad/scripts/apr/sc_power_grid.tcl

@@ -19,6 +19,48 @@ if { [sc_design_has_unplaced_macros] } {
     utl::error FLW 1 "Design contains unplaced macros."
 }
 
+###############################
+# Add blockages
+###############################
+
+set pdn_blockages []
+set pdn_pin_keepout [lindex [sc_cfg_tool_task_get var fixed_pin_keepout] 0]
+if { $pdn_pin_keepout > 0 } {
+    foreach bterm [[ord::get_db_block] getBTerms] {
+        foreach bpin [$bterm getBPins] {
+            if {
+                [$bpin getPlacementStatus] != "FIRM" &&
+                [$bpin getPlacementStatus] != "LOCKED"
+            } {
+                continue
+            }
+
+            foreach box [$bpin getBoxes] {
+                set layer [$box getTechLayer]
+                if { $layer == "NULL" } {
+                    continue
+                }
+
+                set tech_pitch [expr { [$layer getPitch] * $pdn_pin_keepout }]
+
+                set xmin [expr { [$box xMin] - $tech_pitch }]
+                set xmax [expr { [$box xMax] + $tech_pitch }]
+                set ymin [expr { [$box yMin] - $tech_pitch }]
+                set ymax [expr { [$box yMax] + $tech_pitch }]
+
+                set blockage [odb::dbObstruction_create \
+                    [ord::get_db_block] \
+                    $layer \
+                    $xmin $ymin \
+                    $xmax $ymax]
+                lappend pdn_blockages $blockage
+            }
+        }
+    }
+
+    utl::info FLW 1 "Added [llength $pdn_blockages] obstructions to pins"
+}
+
 ###############################
 # Power Network
 ###############################
@@ -33,6 +75,7 @@ foreach pdnconfig [sc_cfg_tool_task_get {file} pdn_config] {
 
     lappend pdn_files $pdnconfig
 }
+tee -quiet -file reports/power_grid_configuration.rpt {pdngen -report_only}
 pdngen -failed_via_report "reports/${sc_design}_pdngen_failed_vias.rpt"
 
 ###############################
@@ -63,6 +106,17 @@ foreach net [sc_psm_check_nets] {
         {*}$check_args
 }
 
+###############################
+# Remove blockages
+###############################
+
+if { [llength $pdn_blockages] > 0 } {
+    foreach obstruction $pdn_blockages {
+        odb::dbObstruction_destroy $obstruction
+    }
+    utl::info FLW 1 "Deleted [llength $pdn_blockages] obstructions"
+}
+
 ###############################
 # Task Postamble
 ###############################

siliconcompiler/tools/openroad/scripts/apr/sc_repair_timing.tcl

@@ -20,6 +20,7 @@ set rsz_hold_slack_margin [lindex [sc_cfg_tool_task_get {var} rsz_hold_slack_mar
 set rsz_slew_margin [lindex [sc_cfg_tool_task_get {var} rsz_slew_margin] 0]
 set rsz_cap_margin [lindex [sc_cfg_tool_task_get {var} rsz_cap_margin] 0]
 set rsz_repair_tns [lindex [sc_cfg_tool_task_get {var} rsz_repair_tns] 0]
+set rsz_recover_power [lindex [sc_cfg_tool_task_get {var} rsz_recover_power] 0]
 
 set repair_timing_args []
 if { [lindex [sc_cfg_tool_task_get {var} rsz_skip_pin_swap] 0] == "true" } {
@@ -77,6 +78,29 @@ if { [lindex [sc_cfg_tool_task_get var rsz_skip_hold_repair] 0] != "true" } {
     sc_set_dont_use
 }
 
+if { [lindex [sc_cfg_tool_task_get var rsz_skip_recover_power] 0] != "true" } {
+    ###############################
+    # Recover power
+    ###############################
+
+    estimate_parasitics -placement
+
+    # Enable cells
+    sc_set_dont_use -hold -scanchain -multibit -report dont_use.repair_timing.power
+
+    repair_timing \
+        -recover_power $rsz_recover_power \
+        -verbose \
+        -setup_margin $rsz_setup_slack_margin \
+        -hold_margin $rsz_hold_slack_margin \
+        {*}$repair_timing_args
+
+    sc_detailed_placement
+
+    # Restore dont use
+    sc_set_dont_use
+}
+
 global_connect
 
 # estimate for metrics

siliconcompiler/tools/openroad/scripts/common/procs.tcl

@@ -2,15 +2,24 @@
 # Global Placement
 #######################
 
-proc sc_global_placement_density { } {
-    set gpl_padding [lindex [sc_cfg_tool_task_get var pad_global_place] 0]
+proc sc_global_placement_density { args } {
+    sta::parse_key_args "sc_global_placement_density" args \
+        keys {} \
+        flags {-exclude_padding}
+    sta::check_argc_eq0 "sc_global_placement_density" $args
+
     set gpl_place_density [lindex [sc_cfg_tool_task_get var place_density] 0]
     set gpl_uniform_placement_adjustment \
         [lindex [sc_cfg_tool_task_get var gpl_uniform_placement_adjustment] 0]
 
-    set or_uniform_density [gpl::get_global_placement_uniform_density \
-        -pad_left $gpl_padding \
-        -pad_right $gpl_padding]
+    set density_args []
+    if { ![info exists flags(-exclude_padding)] } {
+        set gpl_padding [lindex [sc_cfg_tool_task_get var pad_global_place] 0]
+
+        lappend density_args -pad_left $gpl_padding
+        lappend density_args -pad_right $gpl_padding
+    }
+    set or_uniform_density [gpl::get_global_placement_uniform_density {*}$density_args]
 
     # Small adder to ensure requested density is slightly over the uniform density
     set or_adjust_density_adder 0.001
@@ -758,6 +767,19 @@ proc sc_set_dont_use { args } {
     }
 
     if { [info exists keys(-report)] } {
-        tee -file reports/$keys(-report).rpt {report_dont_use}
+        puts "Dont use report: reports/$keys(-report).rpt"
+        tee -quiet -file reports/$keys(-report).rpt {report_dont_use}
+    }
+}
+
+proc sc_setup_detailed_route { } {
+    foreach via [sc_cfg_tool_task_get var detailed_route_default_via] {
+        utl::info FLW 1 "Marking $via a default routing via"
+        detailed_route_set_default_via $via
+    }
+    foreach layer [sc_cfg_tool_task_get var detailed_route_unidirectional_layer] {
+        set layer [sc_get_layer_name $layer]
+        utl::info FLW 1 "Marking $layer as a unidirectional routing layer"
+        detailed_route_set_unidirectional_layer $layer
     }
 }

siliconcompiler/tools/openroad/scripts/common/read_input_files.tcl

@@ -56,4 +56,5 @@ if { [sc_has_input_files odb "input layout odb"] } {
             source $global_connect
         }
     }
+    tee -file reports/global_connections.rpt {report_global_connect}
 }

siliconcompiler/tools/openroad/scripts/common/reports.tcl

@@ -70,10 +70,17 @@ if { [sc_cfg_tool_task_check_in_list drv_violations var reports] } {
     tee -file reports/timing/drv_violators.rpt \
         "report_check_types -max_slew -max_capacitance -max_fanout -violators"
     report_erc_metrics
+}
 
-    puts "$PREFIX floating nets"
-    tee -file reports/floating_nets.rpt \
-        "report_floating_nets -verbose"
+puts "$PREFIX floating nets"
+tee -file reports/floating_nets.rpt \
+    "report_floating_nets -verbose"
+if { [sc_check_version 19048] } {
+    puts "$PREFIX overdriven nets"
+    tee -file reports/overdriven_nets.rpt \
+        "report_overdriven_nets -verbose"
+    tee -file reports/overdriven_nets_with_parallel.rpt \
+        "report_overdriven_nets -include_parallel_driven -verbose"
 }
 
 utl::metric_int "timing__clocks" [llength [all_clocks]]
@@ -168,17 +175,4 @@ foreach markerdb [[ord::get_db_block] getMarkerCategories] {
 
 utl::push_metrics_stage "sc__cellarea__{}"
 tee -file reports/cell_usage.rpt {report_cell_usage -verbose}
-
-foreach modinst [[ord::get_db_block] getModInsts] {
-    tee -quiet -append -file reports/cell_usage.rpt { puts "" }
-    tee -quiet -append -file reports/cell_usage.rpt {
-    puts "########################################################"
-}
-    tee -quiet -append -file reports/cell_usage.rpt { puts "" }
-
-    utl::metric "design__instance__name__in_module:[[$modinst getMaster] getName]" \
-        [$modinst getHierarchicalName]
-    tee -quiet -append -file reports/cell_usage.rpt \
-        "report_cell_usage -verbose [$modinst getHierarchicalName]"
-}
 utl::pop_metrics_stage

siliconcompiler/tools/slang/__init__.py

@@ -120,6 +120,7 @@ def common_runtime_options(chip):
     ###############################
     # Set up user-provided parameters to ensure we elaborate the correct modules
     for param, value in opts['param']:
+        value = value.replace('"', '\\"')
         options.append(f'-G {param}={value}')
 
     return options

siliconcompiler/tools/verilator/verilator.py

@@ -137,6 +137,7 @@ def runtime_options(chip):
         cmdlist.append(value)
 
     for param, value in frontend_opts['param']:
+        value = value.replace('"', '\\"')
         cmdlist.append(f'-G{param}={value}')
 
     if os.path.isfile(f'inputs/{design}.v'):

siliconcompiler/tools/yosys/__init__.py

@@ -12,7 +12,7 @@ Sources: https://github.com/YosysHQ/yosys
 
 Installation: https://github.com/YosysHQ/yosys
 '''
-
+import os
 import re
 import json
 from siliconcompiler import sc_open
@@ -107,28 +107,31 @@ def syn_post_process(chip):
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
 
-    with sc_open("reports/stat.json") as f:
-        metrics = json.load(f)
-        if "design" in metrics:
-            metrics = metrics["design"]
-
-        if "area" in metrics:
-            record_metric(chip, step, index, 'cellarea',
-                          float(metrics["area"]),
-                          "reports/stat.json",
-                          source_unit='um^2')
-        if "num_cells" in metrics:
-            record_metric(chip, step, index, 'cells',
-                          metrics["num_cells"],
-                          "reports/stat.json")
-        if "num_wire_bits" in metrics:
-            record_metric(chip, step, index, 'nets',
-                          metrics["num_wire_bits"],
-                          "reports/stat.json")
-        if "num_port_bits" in metrics:
-            record_metric(chip, step, index, 'pins',
-                          metrics["num_port_bits"],
-                          "reports/stat.json")
+    if os.path.exists("reports/stat.json"):
+        with sc_open("reports/stat.json") as f:
+            metrics = json.load(f)
+            if "design" in metrics:
+                metrics = metrics["design"]
+
+            if "area" in metrics:
+                record_metric(chip, step, index, 'cellarea',
+                              float(metrics["area"]),
+                              "reports/stat.json",
+                              source_unit='um^2')
+            if "num_cells" in metrics:
+                record_metric(chip, step, index, 'cells',
+                              metrics["num_cells"],
+                              "reports/stat.json")
+            if "num_wire_bits" in metrics:
+                record_metric(chip, step, index, 'nets',
+                              metrics["num_wire_bits"],
+                              "reports/stat.json")
+            if "num_port_bits" in metrics:
+                record_metric(chip, step, index, 'pins',
+                              metrics["num_port_bits"],
+                              "reports/stat.json")
+    else:
+        chip.logger.warning("Yosys cell statistics are missing")
 
     registers = None
     with sc_open(f"{step}.log") as f:

siliconcompiler/tools/yosys/procs.tcl

@@ -52,3 +52,20 @@ proc sc_apply_params { } {
         }
     }
 }
+
+proc sc_get_scratchpad { name } {
+    yosys echo off
+    set value [yosys tee -q -s result.string scratchpad -get $name]
+    yosys echo on
+
+    return $value
+}
+
+proc sc_load_plugin { name } {
+    catch { yosys tee -q -s sc.load.test plugin -i $name }
+    set load_test [sc_get_scratchpad sc.load.test]
+    if { [string first "ERROR" $load_test] == -1 } {
+        return 1
+    }
+    return 0
+}

siliconcompiler/tools/yosys/syn_asic.py

@@ -8,6 +8,7 @@ from siliconcompiler import sc_open
 from siliconcompiler import utils
 from siliconcompiler.tools._common.asic import set_tool_task_var, get_libraries, get_mainlib, \
     CellArea
+from siliconcompiler.tools._common.asic_clock import get_clock_period
 from siliconcompiler.tools._common import get_tool_task
 
 
@@ -75,12 +76,11 @@ def setup_asic(chip):
     # set default control knobs
     mainlib = get_mainlib(chip)
     for option, value in [
-            ('flatten', "true"),
-            ('auto_flatten', "true"),
-            ('hier_iterations', "10"),
-            ('hier_threshold', "1000"),
-            ('autoname', "true"),
-            ('add_buffers', "true")]:
+            ('flatten', True),
+            ('auto_flatten', True),
+            ('hier_threshold', 1000),
+            ('autoname', True),
+            ('add_buffers', True)]:
         chip.set('tool', tool, 'task', task, 'var', option, value,
                  step=step, index=index, clobber=False)
         chip.add('tool', tool, 'task', task, 'require',
@@ -387,11 +387,9 @@ def _get_synthesis_library_key(chip, lib, corners):
 
 
 def get_abc_period(chip):
-
-    tool = 'yosys'
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
-    _, task = get_tool_task(chip, step, index)
+    tool, task = get_tool_task(chip, step, index)
 
     mainlib = get_mainlib(chip)
 
@@ -400,67 +398,16 @@ def get_abc_period(chip):
     if abc_clock_period:
         return abc_clock_period[0]
 
-    period = None
-
     abc_clock_multiplier = float(chip.get('library', mainlib, 'option', 'var',
                                           'yosys_abc_clock_multiplier')[0])
 
-    # get clock information from sdc files
-    # TODO: fix for fpga/asic differentiation later
-    if chip.valid('input', 'constraint', 'sdc'):
-        for sdc in chip.find_files('input', 'constraint', 'sdc', step=step, index=index):
-            lines = []
-            with sc_open(sdc) as f:
-                lines = f.read().splitlines()
-
-            # collect simple variables in case clock is specified with a variable
-            re_var = r"[A-Za-z0-9_]+"
-            re_num = r"[0-9\.]+"
-            sdc_vars = {}
-            for line in lines:
-                tcl_variable = re.findall(fr"^\s*set\s+({re_var})\s+({re_num})", line)
-                if tcl_variable:
-                    var_name, var_value = tcl_variable[0]
-                    sdc_vars[f'${var_name}'] = float(var_value)
-
-            # TODO: handle line continuations
-            for line in lines:
-                clock_period = re.findall(fr"create_clock\s.*-period\s+({re_num}|\${re_var})",
-                                          line)
-                if clock_period:
-                    clock_period = clock_period[0]
-                    if clock_period[0] == '$':
-                        if clock_period in sdc_vars:
-                            clock_period = sdc_vars[clock_period]
-                        else:
-                            chip.logger.warning('Unable to identify clock period from '
-                                                f'{clock_period}.')
-                            continue
-                    else:
-                        clock_period = float(clock_period)
-
-                    clock_period = clock_period * abc_clock_multiplier
-
-                    if period is None:
-                        period = clock_period
-                    else:
-                        period = min(period, clock_period)
-
-    if period is None:
-        # get clock information from defined clocks
-        for pin in chip.getkeys('datasheet', 'pin'):
-            for mode in chip.getkeys('datasheet', 'pin', pin, 'type'):
-                if chip.get('datasheet', 'pin', pin, 'type', mode) == 'clock':
-                    clock_period = min(chip.get('datasheet', 'pin', pin, 'tperiod', mode)) * 1e12
-
-                    if period is None:
-                        period = clock_period
-                    else:
-                        period = min(period, clock_period)
-
-    if period is None:
+    _, period = get_clock_period(chip,
+                                 clock_units_multiplier=abc_clock_multiplier / 1000)
+    if not period:
         return None
 
+    period *= 1000
+
     abc_clock_derating = chip.get('tool', tool, 'task', task, 'var', 'abc_clock_derating',
                                   step=step, index=index)
     if abc_clock_derating:

siliconcompiler/tools/yosys/syn_asic.tcl

@@ -38,44 +38,6 @@ proc get_modules { { find "*" } } {
     return [lsort $modules]
 }
 
-proc determine_keep_hierarchy { iter cell_limit } {
-    global sc_design
-
-    # Grab only the modules and not the header and footer
-    set modules [get_modules]
-
-    # Save a copy of the current design so we can do a few optimizations and techmap
-    yosys design -save hierarchy_checkpoint
-    yosys techmap
-    yosys opt -fast -full -purge
-
-    set cell_counts [dict create]
-
-    foreach module $modules {
-        yosys stat -top $module
-        yosys echo off
-        set cells_count [yosys tee -q -s result.string scratchpad -get stat.num_cells]
-        yosys echo on
-        dict set cell_counts $module [expr { int($cells_count) }]
-    }
-
-    # Restore design
-    yosys design -load hierarchy_checkpoint
-    foreach module $modules {
-        yosys select -module $module
-        yosys setattr -mod -set keep_hierarchy \
-            [expr { [dict get $cell_counts $module] > $cell_limit }]
-        yosys select -clear
-    }
-
-    preserve_modules
-
-    # Rerun coarse synth with flatten
-    yosys synth -flatten -top $sc_design -run coarse:fine
-
-    return [expr { [llength $modules] != [llength [get_modules]] }]
-}
-
 ####################
 # DESIGNER's CHOICE
 ####################
@@ -171,11 +133,11 @@ proc get_buffer_cell { } {
 ########################################################
 
 foreach lib_file "$sc_libraries $sc_macro_libraries" {
-    yosys read_liberty -lib $lib_file
+    yosys read_liberty -setattr liberty_cell -lib $lib_file
 }
 foreach bb_file $sc_blackboxes {
     yosys log "Reading blackbox model file: $bb_file"
-    yosys read_verilog -sv $bb_file
+    yosys read_verilog -setattr blackbox -sv $bb_file
 }
 
 ########################################################
@@ -216,7 +178,6 @@ if {
     set sc_tbuf "true"
 
     yosys tribuf
-    yosys stat
 }
 
 set flatten_design [expr {
@@ -245,18 +206,12 @@ sc_map_memory $sc_memory_libmap_files $sc_memory_techmap_files 0
 
 # Perform hierarchy flattening
 if { !$flatten_design && [lindex [sc_cfg_tool_task_get var auto_flatten] 0] == "true" } {
-    yosys log -push
-    yosys log -header "SC Auto flattening"
-    set sc_hier_iterations \
-        [lindex [sc_cfg_tool_task_get var hier_iterations] 0]
     set sc_hier_threshold \
         [lindex [sc_cfg_tool_task_get var hier_threshold] 0]
-    for { set i 0 } { $i < $sc_hier_iterations } { incr i } {
-        if { [determine_keep_hierarchy $i $sc_hier_threshold] == 0 } {
-            break
-        }
-    }
-    yosys log -pop
+
+    yosys keep_hierarchy -min_cost $sc_hier_threshold
+
+    yosys synth -flatten {*}$synth_args -top $sc_design -run coarse:fine
 }
 
 # Finish synthesis

siliconcompiler/toolscripts/_tools.json

@@ -1,7 +1,7 @@
 {
   "openroad": {
     "git-url": "https://github.com/The-OpenROAD-Project/OpenROAD.git",
-    "git-commit": "44e36144112da6b2a3bb346ca0d0b692b6d117ca",
+    "git-commit": "3258b30e2c47d695ff2bb6c14a23c6779ed130bb",
     "docker-cmds": [
       "# Remove OR-Tools files",
       "RUN rm -f $SC_PREFIX/Makefile $SC_PREFIX/README.md",
@@ -32,7 +32,7 @@
   },
   "bluespec": {
     "git-url": "https://github.com/B-Lang-org/bsc.git",
-    "git-commit": "4cac6ebae076e8b8378597aba1d2119aa29ec419",
+    "git-commit": "2024.07",
     "auto-update": false
   },
   "klayout": {
@@ -45,7 +45,7 @@
   },
   "sv2v": {
     "git-url": "https://github.com/zachjs/sv2v.git",
-    "git-commit": "aa0a885699ca8f4fc1d07ef34fb041c6f37b1ba3",
+    "git-commit": "4ec99fcffd2c533c4a2c74ad6f56278f2672f05d",
     "auto-update": true
   },
   "verilator": {
@@ -91,7 +91,7 @@
   },
   "yosys": {
     "git-url": "https://github.com/YosysHQ/yosys.git",
-    "git-commit": "v0.49",
+    "git-commit": "v0.50",
     "version-prefix": "",
     "auto-update": true
   },
@@ -128,7 +128,7 @@
     "auto-update": false
   },
   "slang": {
-    "git-commit": "v7.0",
+    "git-commit": "v8.0",
     "git-url": "https://github.com/MikePopoloski/slang.git",
     "auto-update": true
   },

siliconcompiler/toolscripts/rhel8/install-yosys.sh

@@ -18,6 +18,6 @@ cd yosys
 git checkout $(python3 ${src_path}/_tools.py --tool yosys --field git-commit)
 git submodule update --init --recursive
 
-make -j$(nproc)
+make -j$(nproc) PREFIX="$PREFIX"
 sudo make install PREFIX="$PREFIX"
 cd -

siliconcompiler/toolscripts/rhel9/install-openroad.sh

@@ -0,0 +1,34 @@
+#!/bin/sh
+
+set -e
+
+src_path=$(cd -- "$(dirname "$0")" >/dev/null 2>&1 ; pwd -P)/..
+
+mkdir -p deps
+cd deps
+
+git clone $(python3 ${src_path}/_tools.py --tool openroad --field git-url) openroad
+cd openroad
+git checkout $(python3 ${src_path}/_tools.py --tool openroad --field git-commit)
+git submodule update --init --recursive
+
+# Install missing dependencies
+sudo yum install -y bison byacc
+
+deps_args=""
+if [ ! -z ${PREFIX} ]; then
+    deps_args="-prefix=$PREFIX"
+fi
+sudo ./etc/DependencyInstaller.sh -all $deps_args
+
+cmake_args="-DENABLE_TESTS=OFF"
+if [ ! -z ${PREFIX} ]; then
+    cmake_args="$cmake_args -DCMAKE_INSTALL_PREFIX=$PREFIX"
+fi
+
+./etc/Build.sh -cmake="$cmake_args"
+
+cd build
+sudo make install
+
+cd -