siliconcompiler 0.29.3__py3-none-any.whl → 0.30.0__py3-none-any.whl

siliconcompiler/tools/_common/asic_clock.py

@@ -0,0 +1,101 @@
+import re
+from siliconcompiler.utils import sc_open
+from siliconcompiler.tools._common.asic import get_tool_task
+
+
+def __get_clock_data(chip, clock_units_multiplier=1):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+
+    period = None
+    # get clock information from sdc files
+    if chip.valid('input', 'constraint', 'sdc'):
+        for sdc in chip.find_files('input', 'constraint', 'sdc', step=step, index=index):
+            lines = []
+            with sc_open(sdc) as f:
+                lines = f.read().splitlines()
+
+            # collect simple variables in case clock is specified with a variable
+            re_var = r"[A-Za-z0-9_]+"
+            re_num = r"[0-9\.]+"
+            sdc_vars = {}
+            for line in lines:
+                tcl_variable = re.findall(fr"^\s*set\s+({re_var})\s+({re_num}|\${re_var})", line)
+                if tcl_variable:
+                    var_name, var_value = tcl_variable[0]
+                    sdc_vars[f'${var_name}'] = var_value
+
+            # TODO: handle line continuations
+            for line in lines:
+                clock_period = re.findall(fr"create_clock\s.*-period\s+({re_num}|\${re_var})",
+                                          line)
+                if clock_period:
+                    convert_period = clock_period[0]
+                    while isinstance(convert_period, str) and convert_period[0] == "$":
+                        if convert_period in sdc_vars:
+                            convert_period = sdc_vars[convert_period]
+                        else:
+                            break
+                    if isinstance(convert_period, str) and convert_period[0] == "$":
+                        chip.logger.warning('Unable to identify clock period from '
+                                            f'{clock_period[0]}.')
+                        continue
+                    else:
+                        try:
+                            clock_period = float(convert_period)
+                        except TypeError:
+                            continue
+
+                    clock_period = clock_period * clock_units_multiplier
+
+                    if period is None:
+                        period = clock_period
+                    else:
+                        period = min(period, clock_period)
+
+        if period is not None:
+            return period, None, [('input', 'constraint', 'sdc')]
+
+    if period is None:
+        keys = []
+        key_pin = None
+        # get clock information from defined clocks
+        for pin in chip.getkeys('datasheet', 'pin'):
+            for mode in chip.getkeys('datasheet', 'pin', pin, 'type'):
+                if chip.get('datasheet', 'pin', pin, 'type', mode) == 'clock':
+                    clock_period = min(chip.get('datasheet', 'pin', pin, 'tperiod', mode)) * 1e9
+
+                    if period is None:
+                        period = clock_period
+                        keys = [
+                            ('datasheet', 'pin', pin, 'type', mode),
+                            ('datasheet', 'pin', pin, 'tperiod', mode)
+                        ]
+                        key_pin = pin
+                    else:
+                        if clock_period < period:
+                            period = clock_period
+                            keys = [
+                                ('datasheet', 'pin', pin, 'type', mode),
+                                ('datasheet', 'pin', pin, 'tperiod', mode)
+                            ]
+                            key_pin = pin
+        return period, key_pin, keys
+
+    return None, None, []
+
+
+def add_clock_requirements(chip):
+    _, _, keys = __get_clock_data(chip)
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+    for key in keys:
+        chip.add('tool', tool, 'task', task, 'require', ','.join(key),
+                 step=step, index=index)
+
+
+def get_clock_period(chip, clock_units_multiplier=1):
+    period, name, _ = __get_clock_data(chip, clock_units_multiplier=clock_units_multiplier)
+    return name, period

siliconcompiler/tools/bambu/__init__.py

@@ -0,0 +1,32 @@
+'''
+The primary objective of the PandA project is to develop a usable framework that will
+enable the research of new ideas in the HW-SW Co-Design field.
+
+The PandA framework includes methodologies supporting the research on high-level synthesis
+of hardware accelerators, on parallelism extraction for embedded systems, on hardware/software
+partitioning and mapping, on metrics for performance estimation of embedded software
+applications and on dynamic reconfigurable devices.
+
+Documentation: https://github.com/ferrandi/PandA-bambu
+
+Sources: https://github.com/ferrandi/PandA-bambu
+
+Installation: https://panda.dei.polimi.it/?page_id=88
+'''
+
+from siliconcompiler.tools.bambu import convert
+
+
+####################################################################
+# Make Docs
+####################################################################
+def make_docs(chip):
+    convert.setup(chip)
+    return chip
+
+
+def parse_version(stdout):
+    # Long multiline output, but second-to-last line looks like:
+    # Version: PandA 0.9.6 - Revision 5e5e306b86383a7d85274d64977a3d71fdcff4fe-main
+    version_line = stdout.split('\n')[-3]
+    return version_line.split()[2]

siliconcompiler/tools/bambu/convert.py

@@ -1,9 +1,19 @@
 import os
+import re
 import shutil
-from siliconcompiler import utils
+from siliconcompiler.utils import sc_open
+from siliconcompiler.tools._common.asic import set_tool_task_var, set_tool_task_lib_var, get_mainlib
+from siliconcompiler.tools._common.asic_clock import get_clock_period, add_clock_requirements
 from siliconcompiler.tools._common import \
     add_frontend_requires, add_require_input, get_frontend_options, get_input_files, \
-    get_tool_task, has_input_files
+    get_tool_task, has_input_files, record_metric
+
+
+def make_docs(chip):
+    from siliconcompiler.targets import freepdk45_demo
+    chip.use(freepdk45_demo)
+    chip.input('<design>.c')
+    return setup(chip)
 
 
 def setup(chip):
@@ -11,13 +21,13 @@ def setup(chip):
     Performs high level synthesis to generate a verilog output
     '''
 
-    if not has_input_files(chip, 'input', 'hll', 'c'):
-        return "no files in [input,hll,c]"
+    if not has_input_files(chip, 'input', 'hll', 'c') and \
+       not has_input_files(chip, 'input', 'hll', 'llvm'):
+        return "no files in [input,hll,c] or [input,hll,llvm]"
 
-    tool = 'bambu'
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
-    _, task = get_tool_task(chip, step, index)
+    tool, task = get_tool_task(chip, step, index)
 
     # Standard Setup
     refdir = 'tools/' + tool
@@ -28,24 +38,41 @@ def setup(chip):
     chip.set('tool', tool, 'task', task, 'refdir', refdir,
              step=step, index=index,
              package='siliconcompiler', clobber=False)
-    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
-             step=step, index=index, clobber=False)
 
     # Input/Output requirements
     chip.add('tool', tool, 'task', task, 'output', chip.top() + '.v', step=step, index=index)
 
+    add_clock_requirements(chip)
+
     # Schema requirements
     add_require_input(chip, 'input', 'hll', 'c')
+    add_require_input(chip, 'input', 'hll', 'llvm')
     add_frontend_requires(chip, ['idir', 'define'])
 
+    set_tool_task_var(chip, 'device',
+                      schelp="Device to use during bambu synthesis")
+    set_tool_task_lib_var(chip, 'memorychannels', default_value=1,
+                          schelp="Number of memory channels available")
+
+    # Require clock conversion factor, from library units to ns
+    mainlib = get_mainlib(chip)
+    chip.add('tool', tool, 'task', task, 'require',
+             ','.join(['library', mainlib, 'option', 'var', 'bambu_clock_multiplier']),
+             step=step, index=index)
+
+    set_tool_task_var(chip, 'clock_multiplier',
+                      schelp="Clock multiplier used to convert library units to ns")
+
 
 ################################
 #  Custom runtime options
 ################################
 def runtime_options(chip):
-    cmdlist = []
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
 
-    cmdlist.append('--memory-allocation-policy=NO_BRAM')
+    cmdlist = []
 
     opts = get_frontend_options(chip, ['idir', 'define'])
 
@@ -55,11 +82,34 @@ def runtime_options(chip):
         cmdlist.append('-D' + value)
     for value in get_input_files(chip, 'input', 'hll', 'c'):
         cmdlist.append(value)
+    if not has_input_files(chip, 'input', 'hll', 'c'):
+        # Only use llvm if C is empty
+        for value in get_input_files(chip, 'input', 'hll', 'llvm'):
+            cmdlist.append(value)
 
+    cmdlist.append('--soft-float')
     cmdlist.append('--memory-allocation-policy=NO_BRAM')
 
-    step = chip.get('arg', 'step')
-    index = chip.get('arg', 'index')
+    mem_channels = int(chip.get('tool', tool, 'task', task, 'var', 'memorychannels',
+                                step=step, index=index)[0])
+    if mem_channels > 0:
+        cmdlist.append(f'--channels-number={mem_channels}')
+
+    mainlib = get_mainlib(chip)
+    clock_multiplier = float(chip.get('library', mainlib, 'option', 'var',
+                                      'bambu_clock_multiplier')[0])
+    clock_name, period = get_clock_period(chip, clock_units_multiplier=clock_multiplier)
+    if clock_name:
+        cmdlist.append(f'--clock-name={clock_name}')
+    if period:
+        cmdlist.append(f'--clock-period={period}')
+
+    cmdlist.append('--disable-function-proxy')
+
+    device = chip.get('tool', tool, 'task', task, 'var', 'device',
+                      step=step, index=index)
+    if device:
+        cmdlist.append(f'--device={device[0]}')
 
     cmdlist.append(f'--top-fname={chip.top(step, index)}')
 
@@ -76,3 +126,34 @@ def post_process(chip):
     index = chip.get('arg', 'index')
 
     shutil.copy2(f'{chip.top(step, index)}.v', os.path.join('outputs', f'{chip.top()}.v'))
+
+    ff = re.compile(fr"Total number of flip-flops in function {chip.top(step, index)}: (\d+)")
+    area = re.compile(r"Total estimated area: (\d+)")
+    fmax = re.compile(r"Estimated max frequency \(MHz\): (\d+\.?\d*)")
+    slack = re.compile(r"Minimum slack: (\d+\.?\d*)")
+
+    log_file = f"{step}.log"
+    with sc_open(log_file) as log:
+        for line in log:
+            ff_match = ff.findall(line)
+            area_match = area.findall(line)
+            fmax_match = fmax.findall(line)
+            slack_match = slack.findall(line)
+            if ff_match:
+                record_metric(chip, step, index, "registers", int(ff_match[0]), log_file)
+            if area_match:
+                record_metric(chip, step, index, "cellarea", float(area_match[0]), log_file,
+                              source_unit='um^2')
+            if fmax_match:
+                record_metric(chip, step, index, "fmax", float(fmax_match[0]), log_file,
+                              source_unit='MHz')
+            if slack_match:
+                slack_ns = float(slack_match[0])
+                if slack_ns >= 0:
+                    record_metric(chip, step, index, "setupwns", 0, log_file,
+                                  source_unit='ns')
+                else:
+                    record_metric(chip, step, index, "setupwns", slack_ns, log_file,
+                                  source_unit='ns')
+                record_metric(chip, step, index, "setupslack", slack_ns, log_file,
+                              source_unit='ns')

siliconcompiler/tools/bluespec/__init__.py

@@ -0,0 +1,35 @@
+'''
+Bluespec is a high-level hardware description language. It has a variety of
+advanced features including a powerful type system that can prevent errors
+prior to synthesis time, and its most distinguishing feature, Guarded Atomic
+Actions, allow you to define hardware components in a modular manner based
+on their invariants, and let the compiler pick a scheduler.
+
+Documentation: https://github.com/B-Lang-org/bsc#documentation
+
+Sources: https://github.com/B-Lang-org/bsc
+
+Installation: https://github.com/B-Lang-org/bsc#download
+'''
+
+from siliconcompiler.tools.bluespec import convert
+
+
+####################################################################
+# Make Docs
+####################################################################
+def make_docs(chip):
+    convert.setup(chip)
+    return chip
+
+
+################################
+# Setup Tool (pre executable)
+################################
+def parse_version(stdout):
+    # Examples:
+    # Bluespec Compiler, version 2021.12.1-27-g9a7d5e05 (build 9a7d5e05)
+    # Bluespec Compiler, version 2021.07 (build 4cac6eba)
+
+    long_version = stdout.split()[3]
+    return long_version.split('-')[0]

siliconcompiler/tools/bluespec/convert.py

@@ -8,6 +8,7 @@ from siliconcompiler import sc_open
 
 # Directory inside step/index dir to store bsc intermediate results.
 VLOG_DIR = 'verilog'
+BSC_DIR = 'bluespec'
 
 
 def setup(chip):
@@ -39,6 +40,7 @@ def setup(chip):
 
     # Input/Output requirements
     chip.add('tool', tool, 'task', task, 'output', chip.top() + '.v', step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', chip.top() + '.dot', step=step, index=index)
 
     # Schema requirements
     add_require_input(chip, 'input', 'hll', 'bsv')
@@ -50,9 +52,10 @@ def setup(chip):
 ################################
 def pre_process(chip):
     # bsc requires its output directory exists before being called.
-    if os.path.isdir(VLOG_DIR):
-        shutil.rmtree(VLOG_DIR)
-    os.makedirs(VLOG_DIR)
+    for path in (VLOG_DIR, BSC_DIR):
+        if os.path.isdir(path):
+            shutil.rmtree(path)
+        os.makedirs(path)
 
 
 ################################
@@ -68,7 +71,13 @@ def runtime_options(chip):
 
     cmdlist.append('-verilog')
     cmdlist.append(f'-vdir {VLOG_DIR}')
+    cmdlist.append(f'-bdir {BSC_DIR}')
+    cmdlist.append('-info-dir reports')
     cmdlist.append('-u')
+    cmdlist.append('-v')
+
+    cmdlist.append('-show-module-use')
+    cmdlist.append('-sched-dot')
 
     cmdlist.append(f'-g {chip.top(step, index)}')
 
@@ -95,10 +104,40 @@ def post_process(chip):
     ''' Tool specific function to run after step execution
     '''
 
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+
+    shutil.copyfile(f"reports/{chip.top(step, index)}_combined_full.dot",
+                    f"outputs/{chip.top()}.dot")
+
+    extra_modules = set()
+    use_file = os.path.join(VLOG_DIR, f"{chip.top(step, index)}.use")
+    if os.path.exists(use_file):
+        BSC_BASE = os.path.dirname(
+            os.path.dirname(
+                chip.get('record', 'toolpath', step=step, index=index)))
+        BSC_LIB = os.path.join(BSC_BASE, "lib", "Verilog")
+
+        with sc_open(use_file) as f:
+            for module in f:
+                module = module.strip()
+                mod_path = os.path.join(BSC_LIB, f"{module}.v")
+                if os.path.exists(mod_path):
+                    extra_modules.add(mod_path)
+                else:
+                    chip.logger.warn(f"Unable to find module {module} source files at: {BSC_LIB}")
+
     # bsc outputs each compiled module to its own Verilog file, so we
     # concatenate them all to create a pickled output we can pass along.
     design = chip.top()
     with open(os.path.join('outputs', f'{design}.v'), 'w') as pickled_vlog:
         for src in os.listdir(VLOG_DIR):
-            with sc_open(os.path.join(VLOG_DIR, src)) as vlog_mod:
-                pickled_vlog.write(vlog_mod.read())
+            if src.endswith(".v"):
+                with sc_open(os.path.join(VLOG_DIR, src)) as vlog_mod:
+                    pickled_vlog.write(vlog_mod.read())
+
+        pickled_vlog.write("\n")
+        pickled_vlog.write("// Bluespec imports\n\n")
+        for vfile in extra_modules:
+            with sc_open(os.path.join(BSC_LIB, vfile)) as vlog_mod:
+                pickled_vlog.write(vlog_mod.read() + "\n")

siliconcompiler/tools/graphviz/__init__.py

@@ -0,0 +1,12 @@
+'''
+Graphviz is open source graph visualization software.
+Graph visualization is a way of representing structural information as diagrams
+of abstract graphs and networks.
+It has important applications in networking, bioinformatics, software engineering,
+database and web design, machine learning, and in visual interfaces for other
+technical domains.
+'''
+
+
+def make_docs(chip):
+    return chip

siliconcompiler/tools/graphviz/screenshot.py

@@ -0,0 +1,48 @@
+import graphviz
+import os
+
+from siliconcompiler import sc_open
+from siliconcompiler.tools._common import get_tool_task
+
+
+def setup(chip):
+    '''
+    Generate a screenshot of a dot file
+    '''
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    chip.set('tool', tool, 'task', task, 'threads', 1, step=step, index=index)
+
+    chip.add('tool', tool, 'task', task, 'output', chip.top() + '.png', step=step, index=index)
+
+
+def run(chip):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    if os.path.exists(f'inputs/{chip.top()}.dot'):
+        file = f'inputs/{chip.top()}.dot'
+    elif os.path.exists(f'inputs/{chip.top()}.xdot'):
+        file = f'inputs/{chip.top()}.xdot'
+    elif chip.valid('tool', tool, 'task', task, 'var', 'show_filepath') and \
+            chip.get('tool', tool, 'task', task, 'var', 'show_filepath', step=step, index=index):
+        file = chip.get('tool', tool, 'task', task, 'var', 'show_filepath',
+                        step=step, index=index)[0]
+    else:
+        file = chip.find_files('input', 'image', 'dot', step=step, index=index)[0]
+
+    with sc_open(file) as dot:
+        dot_content = dot.read()
+
+    try:
+        dot = graphviz.Source(dot_content, format="png")
+        dot.render(filename=f"outputs/{chip.top()}", cleanup=True)
+        pass
+    except graphviz.ExecutableNotFound:
+        return 1
+
+    return 0

siliconcompiler/tools/graphviz/show.py

@@ -0,0 +1,20 @@
+from PIL import Image
+from siliconcompiler.tools.graphviz import screenshot
+
+
+def setup(chip):
+    '''
+    Show a graphviz dot file
+    '''
+
+    screenshot.setup(chip)
+
+
+def run(chip):
+    screenshot_ret = screenshot.run(chip)
+    if screenshot_ret != 0:
+        return screenshot_ret
+
+    Image.open(f"outputs/{chip.top()}.png").show()
+
+    return 0

siliconcompiler/tools/openroad/_apr.py

@@ -128,6 +128,8 @@ def extract_metrics(chip):
         "drvs": [
             "timing/drv_violators.rpt",
             "floating_nets.rpt",
+            "overdriven_nets.rpt",
+            "overdriven_nets_with_parallel.rpt",
             f"{chip.design}_antenna.rpt",
             f"{chip.design}_antenna_post_repair.rpt"
         ],
@@ -148,6 +150,10 @@ def extract_metrics(chip):
 
     metrics_file = "reports/metrics.json"
 
+    if not os.path.exists(metrics_file):
+        chip.logger.warning("OpenROAD metrics file is missing")
+        return
+
     def get_metric_sources(metric):
         metric_sources = [metrics_file]
         if metric in metric_reports:
@@ -277,6 +283,10 @@ def extract_metrics(chip):
                 'sc__metric__timing__drv__max_slew',
                 'sc__metric__timing__drv__max_cap',
                 'sc__metric__timing__drv__max_fanout',
+                'sc__metric__timing__drv__max_fanout',
+                'sc__metric__timing__drv__floating__nets',
+                'sc__metric__timing__drv__floating__pins',
+                'sc__metric__timing__drv__overdriven__nets',
                 'sc__metric__antenna__violating__nets',
                 'sc__metric__antenna__violating__pins']:
             if metric in metrics:
@@ -572,6 +582,13 @@ def define_rsz_params(chip):
                       default_value='100',
                       schelp='percentage of violating nets to attempt to repair (0 - 100)')
 
+    set_tool_task_var(chip, param_key='rsz_skip_recover_power',
+                      default_value=False,
+                      schelp='skip power recovery')
+    set_tool_task_var(chip, param_key='rsz_recover_power',
+                      default_value=100,
+                      schelp='percentage of paths to attempt to recover power (0 - 100)')
+
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
     tool, task = get_tool_task(chip, step, index)

siliconcompiler/tools/openroad/fillmetal_insertion.py

@@ -43,7 +43,6 @@ def setup(chip):
         'hold',
         'unconstrained',
         'clock_skew',
-        'power',
         'drv_violations',
         'fmax',
 

siliconcompiler/tools/openroad/init_floorplan.py

@@ -1,5 +1,5 @@
 from siliconcompiler.tools._common import input_provides, add_common_file, get_tool_task
-from siliconcompiler.tools._common.asic import set_tool_task_var
+from siliconcompiler.tools._common.asic import set_tool_task_var, get_mainlib
 
 from siliconcompiler.tools.openroad._apr import setup as apr_setup
 from siliconcompiler.tools.openroad._apr import set_reports, set_pnr_inputs, set_pnr_outputs
@@ -74,6 +74,8 @@ def setup(chip):
         'power'
     ])
 
+    mainlib = get_mainlib(chip)
+
     # Setup required
     for component in chip.getkeys('constraint', 'component'):
         for key in chip.getkeys('constraint', 'component', component):
@@ -92,6 +94,10 @@ def setup(chip):
             chip.add('tool', tool, 'task', task, 'require',
                      ','.join(['constraint', ifp]),
                      step=step, index=index)
+    if chip.valid('library', mainlib, 'option', 'file', 'openroad_tracks'):
+        chip.add('tool', tool, 'task', task, 'require',
+                 ','.join(['library', mainlib, 'option', 'file', 'openroad_tracks']),
+                 step=step, index=index)
 
 
 def pre_process(chip):

siliconcompiler/tools/openroad/macro_placement.py

@@ -40,10 +40,18 @@ def setup(chip):
 
     set_reports(chip, [
         'setup',
-        'unconstrained',
-        'power'
+        'unconstrained'
     ])
 
+    chip.set('tool', tool, 'task', task, 'file', 'rtlmp_constraints',
+             'contraints script for macro placement',
+             field='help')
+
+    if chip.get('tool', tool, 'task', task, 'file', 'rtlmp_constraints', step=step, index=index):
+        chip.add('tool', tool, 'task', task, 'require',
+                 ",".join(['tool', tool, 'task', task, 'file', 'rtlmp_constraints']),
+                 step=step, index=index)
+
 
 def pre_process(chip):
     step = chip.get('arg', 'step')

siliconcompiler/tools/openroad/pin_placement.py

@@ -38,7 +38,6 @@ def setup(chip):
     set_reports(chip, [
         'setup',
         'unconstrained',
-        'power',
 
         # Images
         'placement_density',

siliconcompiler/tools/openroad/power_grid.py

@@ -1,6 +1,7 @@
 from siliconcompiler import NodeStatus
 
 from siliconcompiler.tools._common import get_tool_task, has_pre_post_script
+from siliconcompiler.tools._common.asic import set_tool_task_var
 
 from siliconcompiler.tools.openroad._apr import setup as apr_setup
 from siliconcompiler.tools.openroad._apr import set_reports, set_pnr_inputs, set_pnr_outputs
@@ -39,6 +40,11 @@ def setup(chip):
     define_pdn_params(chip)
     define_psm_params(chip)
 
+    set_tool_task_var(chip, param_key='fixed_pin_keepout',
+                      default_value=0,
+                      schelp='if > 0, applies a blockage in multiples of the routing pitch '
+                             'to each fixed pin to ensure there is room for routing.')
+
     set_reports(chip, [])
 
 

siliconcompiler/tools/openroad/scripts/apr/preamble.tcl

@@ -91,5 +91,6 @@ if { [llength $openroad_dont_touch] > 0 } {
     # set don't touch list
     set_dont_touch $openroad_dont_touch
 }
-tee -file reports/dont_touch.start.rpt {report_dont_touch}
-tee -file reports/dont_use.start.rpt {report_dont_use}
+tee -quiet -file reports/dont_touch.start.rpt {report_dont_touch}
+tee -quiet -file reports/dont_use.start.rpt {report_dont_use}
+tee -file reports/global_connections.start.rpt {report_global_connect}

siliconcompiler/tools/openroad/scripts/apr/sc_clock_tree_synthesis.tcl

@@ -43,6 +43,8 @@ if { [llength [all_clocks]] > 0 } {
         -distance_between_buffers $cts_distance_between_buffers \
         {*}$sc_cts_arguments
 
+    tee -file reports/cts.rpt {report_cts}
+
     set_propagated_clock [all_clocks]
 
     estimate_parasitics -placement

siliconcompiler/tools/openroad/scripts/apr/sc_detailed_route.tcl

@@ -15,6 +15,8 @@ source -echo "$sc_refdir/apr/preamble.tcl"
 # Detailed Routing
 ###############################
 
+sc_setup_detailed_route
+
 set drt_arguments []
 if { [lindex [sc_cfg_tool_task_get {var} drt_disable_via_gen] 0] == "true" } {
     lappend drt_arguments "-disable_via_gen"