siliconcompiler 0.29.2__py3-none-any.whl → 0.29.4__py3-none-any.whl
This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
- siliconcompiler/_metadata.py +1 -1
- siliconcompiler/apps/sc_install.py +19 -4
- siliconcompiler/core.py +8 -3
- siliconcompiler/flowgraph.py +23 -5
- siliconcompiler/remote/client.py +3 -0
- siliconcompiler/scheduler/__init__.py +30 -12
- siliconcompiler/tools/__init__.py +1 -1
- siliconcompiler/tools/_common/asic.py +3 -0
- siliconcompiler/tools/_common/asic_clock.py +101 -0
- siliconcompiler/tools/bambu/__init__.py +32 -0
- siliconcompiler/tools/bambu/convert.py +93 -11
- siliconcompiler/tools/bluespec/convert.py +2 -1
- siliconcompiler/tools/chisel/convert.py +2 -1
- siliconcompiler/tools/genfasm/bitstream.py +2 -2
- siliconcompiler/tools/ghdl/convert.py +2 -2
- siliconcompiler/tools/gtkwave/show.py +2 -1
- siliconcompiler/tools/icarus/compile.py +2 -2
- siliconcompiler/tools/klayout/drc.py +2 -1
- siliconcompiler/tools/magic/magic.py +1 -1
- siliconcompiler/tools/netgen/lvs.py +2 -1
- siliconcompiler/tools/openroad/_apr.py +16 -4
- siliconcompiler/tools/openroad/fillmetal_insertion.py +0 -1
- siliconcompiler/tools/openroad/init_floorplan.py +7 -1
- siliconcompiler/tools/openroad/macro_placement.py +1 -2
- siliconcompiler/tools/openroad/pin_placement.py +0 -1
- siliconcompiler/tools/openroad/rdlroute.py +2 -2
- siliconcompiler/tools/openroad/scripts/apr/preamble.tcl +3 -2
- siliconcompiler/tools/openroad/scripts/apr/sc_init_floorplan.tcl +1 -0
- siliconcompiler/tools/openroad/scripts/apr/sc_macro_placement.tcl +78 -94
- siliconcompiler/tools/openroad/scripts/apr/sc_power_grid.tcl +12 -1
- siliconcompiler/tools/openroad/scripts/apr/sc_repair_timing.tcl +24 -0
- siliconcompiler/tools/openroad/scripts/common/procs.tcl +3 -2
- siliconcompiler/tools/openroad/scripts/common/read_input_files.tcl +1 -0
- siliconcompiler/tools/openroad/scripts/common/reports.tcl +4 -13
- siliconcompiler/tools/openroad/scripts/common/write_data.tcl +2 -5
- siliconcompiler/tools/openroad/scripts/common/write_data_physical.tcl +3 -0
- siliconcompiler/tools/openroad/scripts/common/write_data_timing.tcl +1 -0
- siliconcompiler/tools/openroad/scripts/sc_rdlroute.tcl +1 -1
- siliconcompiler/tools/opensta/__init__.py +2 -2
- siliconcompiler/tools/opensta/report_libraries.py +2 -2
- siliconcompiler/tools/opensta/timing.py +2 -1
- siliconcompiler/tools/slang/__init__.py +79 -2
- siliconcompiler/tools/slang/elaborate.py +46 -0
- siliconcompiler/tools/slang/lint.py +10 -76
- siliconcompiler/tools/surelog/parse.py +1 -1
- siliconcompiler/tools/sv2v/convert.py +2 -2
- siliconcompiler/tools/template/template.py +2 -2
- siliconcompiler/tools/verilator/verilator.py +3 -1
- siliconcompiler/tools/vivado/vivado.py +2 -1
- siliconcompiler/tools/vpr/place.py +2 -2
- siliconcompiler/tools/vpr/route.py +2 -2
- siliconcompiler/tools/vpr/show.py +2 -1
- siliconcompiler/tools/yosys/__init__.py +26 -23
- siliconcompiler/tools/yosys/procs.tcl +17 -0
- siliconcompiler/tools/yosys/syn_asic.py +20 -65
- siliconcompiler/tools/yosys/syn_asic.tcl +10 -51
- siliconcompiler/toolscripts/_tools.json +4 -4
- siliconcompiler/toolscripts/rhel8/install-slang.sh +0 -0
- siliconcompiler/toolscripts/rhel8/install-sv2v.sh +7 -1
- siliconcompiler/toolscripts/rhel8/install-yosys.sh +1 -1
- siliconcompiler/toolscripts/rhel9/install-openroad.sh +34 -0
- siliconcompiler/toolscripts/rhel9/install-slang.sh +0 -0
- siliconcompiler/toolscripts/rhel9/install-sv2v.sh +7 -1
- siliconcompiler/toolscripts/rhel9/install-yosys.sh +1 -1
- siliconcompiler/toolscripts/ubuntu20/install-slang.sh +0 -0
- siliconcompiler/toolscripts/ubuntu20/install-surelog.sh +1 -0
- siliconcompiler/toolscripts/ubuntu20/install-sv2v.sh +7 -1
- siliconcompiler/toolscripts/ubuntu20/install-yosys.sh +1 -1
- siliconcompiler/toolscripts/ubuntu22/install-surelog.sh +7 -1
- siliconcompiler/toolscripts/ubuntu22/install-sv2v.sh +7 -1
- siliconcompiler/toolscripts/ubuntu22/install-yosys.sh +1 -1
- siliconcompiler/toolscripts/ubuntu24/install-bambu.sh +3 -4
- siliconcompiler/toolscripts/ubuntu24/install-slang.sh +0 -0
- siliconcompiler/toolscripts/ubuntu24/install-surelog.sh +7 -1
- siliconcompiler/toolscripts/ubuntu24/install-sv2v.sh +7 -1
- siliconcompiler/toolscripts/ubuntu24/install-yosys.sh +1 -1
- siliconcompiler/utils/__init__.py +24 -0
- siliconcompiler/utils/logging.py +67 -0
- {siliconcompiler-0.29.2.dist-info → siliconcompiler-0.29.4.dist-info}/METADATA +8 -8
- {siliconcompiler-0.29.2.dist-info → siliconcompiler-0.29.4.dist-info}/RECORD +80 -75
- siliconcompiler/tools/bambu/bambu.py +0 -32
- {siliconcompiler-0.29.2.dist-info → siliconcompiler-0.29.4.dist-info}/LICENSE +0 -0
- {siliconcompiler-0.29.2.dist-info → siliconcompiler-0.29.4.dist-info}/WHEEL +0 -0
- {siliconcompiler-0.29.2.dist-info → siliconcompiler-0.29.4.dist-info}/entry_points.txt +0 -0
- {siliconcompiler-0.29.2.dist-info → siliconcompiler-0.29.4.dist-info}/top_level.txt +0 -0
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@@ -12,7 +12,9 @@ Installation: https://sv-lang.com/building.html
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'''
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import re
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from siliconcompiler import sc_open
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from siliconcompiler.tools._common import
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from siliconcompiler.tools._common import record_metric
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from siliconcompiler.tools._common import \
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get_frontend_options, get_input_files, get_tool_task
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################################
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def post_process(chip):
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step = chip.get('arg', 'step')
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index = chip.get('arg', 'index')
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tool, task = get_tool_task(chip, step, index)
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log = f'{step}.log'
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with sc_open(log) as f:
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if match:
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record_metric(chip, step, index, 'errors', match.group(1), log)
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record_metric(chip, step, index, 'warnings', match.group(2), log)
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def common_runtime_options(chip):
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options = []
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step = chip.get('arg', 'step')
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index = chip.get('arg', 'index')
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tool, task = get_tool_task(chip, step, index)
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options.extend(['-j', str(chip.get('tool', tool, 'task', task, 'threads',
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step=step, index=index))])
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opts = get_frontend_options(chip,
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['ydir',
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'idir',
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'vlib',
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'libext',
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'define',
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'param'])
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if opts['libext']:
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options.append(f'--libext {",".join(opts["libext"])}')
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#####################
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# Library directories
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#####################
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if opts['ydir']:
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options.append(f'-y {",".join(opts["ydir"])}')
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#####################
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# Library files
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#####################
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if opts['vlib']:
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options.append(f'-libfile {",".join(opts["vlib"])}')
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#####################
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# Include paths
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#####################
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if opts['idir']:
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options.append(f'--include-directory {",".join(opts["idir"])}')
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#######################
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# Variable Definitions
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#######################
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for value in opts['define']:
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options.append('-D ' + value)
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#######################
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# Command files
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#######################
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cmdfiles = get_input_files(chip, 'input', 'cmdfile', 'f')
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if cmdfiles:
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options.append(f'-F {",".join(cmdfiles)}')
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#######################
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# Sources
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#######################
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for value in get_input_files(chip, 'input', 'rtl', 'systemverilog'):
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options.append(value)
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for value in get_input_files(chip, 'input', 'rtl', 'verilog'):
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options.append(value)
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#######################
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# Top Module
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#######################
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options.append('--top ' + chip.top())
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###############################
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# Parameters (top module only)
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###############################
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# Set up user-provided parameters to ensure we elaborate the correct modules
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for param, value in opts['param']:
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value = value.replace('"', '\\"')
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options.append(f'-G {param}={value}')
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return options
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from siliconcompiler import utils
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from siliconcompiler.tools import slang
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from siliconcompiler.tools._common import \
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add_require_input, add_frontend_requires, get_tool_task, has_input_files
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def setup(chip):
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'''
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Elaborate verilog design files and generate a unified file.
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'''
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slang.setup(chip)
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step = chip.get('arg', 'step')
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index = chip.get('arg', 'index')
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tool, task = get_tool_task(chip, step, index)
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chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
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clobber=False, step=step, index=index)
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add_require_input(chip, 'input', 'rtl', 'verilog')
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add_require_input(chip, 'input', 'rtl', 'systemverilog')
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add_frontend_requires(chip, ['ydir', 'idir', 'vlib', 'libext', 'define', 'param'])
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chip.set('tool', tool, 'task', task, 'stdout', 'destination', 'output', step=step, index=index)
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chip.set('tool', tool, 'task', task, 'stdout', 'suffix', 'v', step=step, index=index)
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chip.set('tool', tool, 'task', task, 'output', __outputfile(chip), step=step, index=index)
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def runtime_options(chip):
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options = slang.common_runtime_options(chip)
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options.extend([
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"--preprocess",
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"--comments",
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"--ignore-unknown-modules",
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"--allow-use-before-declare"
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])
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return options
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def __outputfile(chip):
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is_systemverilog = has_input_files(chip, 'input', 'rtl', 'systemverilog')
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if is_systemverilog:
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return f'{chip.top()}.sv'
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return f'{chip.top()}.v'
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Lint system verilog
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'''
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from siliconcompiler import utils
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from siliconcompiler.tools import slang
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from siliconcompiler.tools._common import \
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add_require_input, add_frontend_requires,
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import os
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add_require_input, add_frontend_requires, get_tool_task
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'''
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Lint system verilog
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'''
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slang.setup(chip)
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step = chip.get('arg', 'step')
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tool, task = get_tool_task(chip, step, index)
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chip.set('tool', tool, 'task', task, 'threads',
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chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
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clobber=False, step=step, index=index)
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step=step, index=index))])
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#####################
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#####################
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#####################
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#####################
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#####################
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#####################
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# Top Module
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options.extend([
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])
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# Runtime parameters.
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chip.set('tool', tool, 'task', task, 'threads',
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chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
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import
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from siliconcompiler import utils
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# Since we run sv2v after the import/preprocess step, there should be no
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Installation: https://
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'''
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import
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# Required for script based tools
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'''
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import os
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from siliconcompiler import utils
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from siliconcompiler import SiliconCompilerError
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from siliconcompiler.tools.vpr import vpr
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@@ -21,7 +21,7 @@ def setup(chip, clobber=True):
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step=step, index=index, clobber=False)
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design = chip.top()
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import os
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from siliconcompiler import utils
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@@ -30,7 +30,7 @@ def setup(chip, clobber=True):
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step=step, index=index, clobber=clobber)
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# TO-DO: PRIOROTIZE the post-routing packing results?
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@@ -1,4 +1,5 @@
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1
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import os
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from siliconcompiler import utils
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3
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from siliconcompiler import SiliconCompilerError
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from siliconcompiler.tools.vpr import vpr
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from siliconcompiler.tools._common import get_tool_task
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@@ -16,7 +17,7 @@ def setup(chip, clobber=True):
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step=step, index=index, clobber=False)
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@@ -12,7 +12,7 @@ Sources: https://github.com/YosysHQ/yosys
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Installation: https://github.com/YosysHQ/yosys
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'''
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import os
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import re
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import json
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from siliconcompiler import sc_open
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@@ -107,28 +107,31 @@ def syn_post_process(chip):
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step = chip.get('arg', 'step')
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if os.path.exists("reports/stat.json"):
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+
with sc_open("reports/stat.json") as f:
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+
metrics = json.load(f)
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+
if "design" in metrics:
|
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+
metrics = metrics["design"]
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+
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+
if "area" in metrics:
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+
record_metric(chip, step, index, 'cellarea',
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+
float(metrics["area"]),
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+
"reports/stat.json",
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|
+
source_unit='um^2')
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|
+
if "num_cells" in metrics:
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+
record_metric(chip, step, index, 'cells',
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+
metrics["num_cells"],
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+
"reports/stat.json")
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+
if "num_wire_bits" in metrics:
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+
record_metric(chip, step, index, 'nets',
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|
+
metrics["num_wire_bits"],
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|
+
"reports/stat.json")
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|
+
if "num_port_bits" in metrics:
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130
|
+
record_metric(chip, step, index, 'pins',
|
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+
metrics["num_port_bits"],
|
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+
"reports/stat.json")
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+
else:
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|
+
chip.logger.warning("Yosys cell statistics are missing")
|
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135
|
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133
136
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registers = None
|
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with sc_open(f"{step}.log") as f:
|
|
@@ -52,3 +52,20 @@ proc sc_apply_params { } {
|
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52
52
|
}
|
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53
53
|
}
|
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54
54
|
}
|
|
55
|
+
|
|
56
|
+
proc sc_get_scratchpad { name } {
|
|
57
|
+
yosys echo off
|
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58
|
+
set value [yosys tee -q -s result.string scratchpad -get $name]
|
|
59
|
+
yosys echo on
|
|
60
|
+
|
|
61
|
+
return $value
|
|
62
|
+
}
|
|
63
|
+
|
|
64
|
+
proc sc_load_plugin { name } {
|
|
65
|
+
catch { yosys tee -q -s sc.load.test plugin -i $name }
|
|
66
|
+
set load_test [sc_get_scratchpad sc.load.test]
|
|
67
|
+
if { [string first "ERROR" $load_test] == -1 } {
|
|
68
|
+
return 1
|
|
69
|
+
}
|
|
70
|
+
return 0
|
|
71
|
+
}
|
|
@@ -8,6 +8,7 @@ from siliconcompiler import sc_open
|
|
|
8
8
|
from siliconcompiler import utils
|
|
9
9
|
from siliconcompiler.tools._common.asic import set_tool_task_var, get_libraries, get_mainlib, \
|
|
10
10
|
CellArea
|
|
11
|
+
from siliconcompiler.tools._common.asic_clock import get_clock_period
|
|
11
12
|
from siliconcompiler.tools._common import get_tool_task
|
|
12
13
|
|
|
13
14
|
|
|
@@ -75,12 +76,11 @@ def setup_asic(chip):
|
|
|
75
76
|
# set default control knobs
|
|
76
77
|
mainlib = get_mainlib(chip)
|
|
77
78
|
for option, value in [
|
|
78
|
-
('flatten',
|
|
79
|
-
('auto_flatten',
|
|
80
|
-
('
|
|
81
|
-
('
|
|
82
|
-
('
|
|
83
|
-
('add_buffers', "true")]:
|
|
79
|
+
('flatten', True),
|
|
80
|
+
('auto_flatten', True),
|
|
81
|
+
('hier_threshold', 1000),
|
|
82
|
+
('autoname', True),
|
|
83
|
+
('add_buffers', True)]:
|
|
84
84
|
chip.set('tool', tool, 'task', task, 'var', option, value,
|
|
85
85
|
step=step, index=index, clobber=False)
|
|
86
86
|
chip.add('tool', tool, 'task', task, 'require',
|
|
@@ -185,6 +185,14 @@ def setup_asic(chip):
|
|
|
185
185
|
'Instance limit for the number of cells in a module to preserve.',
|
|
186
186
|
field='help')
|
|
187
187
|
|
|
188
|
+
chip.set('tool', tool, 'task', task, 'var', 'hierarchy_separator',
|
|
189
|
+
'control the hierarchy separator used during design flattening', field='help')
|
|
190
|
+
chip.set('tool', tool, 'task', task, 'var', 'hierarchy_separator', '/',
|
|
191
|
+
step=step, index=index, clobber=False)
|
|
192
|
+
chip.add('tool', tool, 'task', task, 'require',
|
|
193
|
+
','.join(['tool', tool, 'task', task, 'var', 'hierarchy_separator']),
|
|
194
|
+
step=step, index=index)
|
|
195
|
+
|
|
188
196
|
set_tool_task_var(chip, 'map_clockgates',
|
|
189
197
|
default_value=False,
|
|
190
198
|
schelp='Map clockgates during synthesis.')
|
|
@@ -379,11 +387,9 @@ def _get_synthesis_library_key(chip, lib, corners):
|
|
|
379
387
|
|
|
380
388
|
|
|
381
389
|
def get_abc_period(chip):
|
|
382
|
-
|
|
383
|
-
tool = 'yosys'
|
|
384
390
|
step = chip.get('arg', 'step')
|
|
385
391
|
index = chip.get('arg', 'index')
|
|
386
|
-
|
|
392
|
+
tool, task = get_tool_task(chip, step, index)
|
|
387
393
|
|
|
388
394
|
mainlib = get_mainlib(chip)
|
|
389
395
|
|
|
@@ -392,67 +398,16 @@ def get_abc_period(chip):
|
|
|
392
398
|
if abc_clock_period:
|
|
393
399
|
return abc_clock_period[0]
|
|
394
400
|
|
|
395
|
-
period = None
|
|
396
|
-
|
|
397
401
|
abc_clock_multiplier = float(chip.get('library', mainlib, 'option', 'var',
|
|
398
402
|
'yosys_abc_clock_multiplier')[0])
|
|
399
403
|
|
|
400
|
-
|
|
401
|
-
|
|
402
|
-
if
|
|
403
|
-
for sdc in chip.find_files('input', 'constraint', 'sdc', step=step, index=index):
|
|
404
|
-
lines = []
|
|
405
|
-
with sc_open(sdc) as f:
|
|
406
|
-
lines = f.read().splitlines()
|
|
407
|
-
|
|
408
|
-
# collect simple variables in case clock is specified with a variable
|
|
409
|
-
re_var = r"[A-Za-z0-9_]+"
|
|
410
|
-
re_num = r"[0-9\.]+"
|
|
411
|
-
sdc_vars = {}
|
|
412
|
-
for line in lines:
|
|
413
|
-
tcl_variable = re.findall(fr"^\s*set\s+({re_var})\s+({re_num})", line)
|
|
414
|
-
if tcl_variable:
|
|
415
|
-
var_name, var_value = tcl_variable[0]
|
|
416
|
-
sdc_vars[f'${var_name}'] = float(var_value)
|
|
417
|
-
|
|
418
|
-
# TODO: handle line continuations
|
|
419
|
-
for line in lines:
|
|
420
|
-
clock_period = re.findall(fr"create_clock\s.*-period\s+({re_num}|\${re_var})",
|
|
421
|
-
line)
|
|
422
|
-
if clock_period:
|
|
423
|
-
clock_period = clock_period[0]
|
|
424
|
-
if clock_period[0] == '$':
|
|
425
|
-
if clock_period in sdc_vars:
|
|
426
|
-
clock_period = sdc_vars[clock_period]
|
|
427
|
-
else:
|
|
428
|
-
chip.logger.warning('Unable to identify clock period from '
|
|
429
|
-
f'{clock_period}.')
|
|
430
|
-
continue
|
|
431
|
-
else:
|
|
432
|
-
clock_period = float(clock_period)
|
|
433
|
-
|
|
434
|
-
clock_period = clock_period * abc_clock_multiplier
|
|
435
|
-
|
|
436
|
-
if period is None:
|
|
437
|
-
period = clock_period
|
|
438
|
-
else:
|
|
439
|
-
period = min(period, clock_period)
|
|
440
|
-
|
|
441
|
-
if period is None:
|
|
442
|
-
# get clock information from defined clocks
|
|
443
|
-
for pin in chip.getkeys('datasheet', 'pin'):
|
|
444
|
-
for mode in chip.getkeys('datasheet', 'pin', pin, 'type'):
|
|
445
|
-
if chip.get('datasheet', 'pin', pin, 'type', mode) == 'clock':
|
|
446
|
-
clock_period = min(chip.get('datasheet', 'pin', pin, 'tperiod', mode)) * 1e12
|
|
447
|
-
|
|
448
|
-
if period is None:
|
|
449
|
-
period = clock_period
|
|
450
|
-
else:
|
|
451
|
-
period = min(period, clock_period)
|
|
452
|
-
|
|
453
|
-
if period is None:
|
|
404
|
+
_, period = get_clock_period(chip,
|
|
405
|
+
clock_units_multiplier=abc_clock_multiplier / 1000)
|
|
406
|
+
if not period:
|
|
454
407
|
return None
|
|
455
408
|
|
|
409
|
+
period *= 1000
|
|
410
|
+
|
|
456
411
|
abc_clock_derating = chip.get('tool', tool, 'task', task, 'var', 'abc_clock_derating',
|
|
457
412
|
step=step, index=index)
|
|
458
413
|
if abc_clock_derating:
|