siliconcompiler 0.29.2__py3-none-any.whl → 0.29.4__py3-none-any.whl

This diff represents the content of publicly available package versions that have been released to one of the supported registries. The information contained in this diff is provided for informational purposes only and reflects changes between package versions as they appear in their respective public registries.
Files changed (85) hide show
  1. siliconcompiler/_metadata.py +1 -1
  2. siliconcompiler/apps/sc_install.py +19 -4
  3. siliconcompiler/core.py +8 -3
  4. siliconcompiler/flowgraph.py +23 -5
  5. siliconcompiler/remote/client.py +3 -0
  6. siliconcompiler/scheduler/__init__.py +30 -12
  7. siliconcompiler/tools/__init__.py +1 -1
  8. siliconcompiler/tools/_common/asic.py +3 -0
  9. siliconcompiler/tools/_common/asic_clock.py +101 -0
  10. siliconcompiler/tools/bambu/__init__.py +32 -0
  11. siliconcompiler/tools/bambu/convert.py +93 -11
  12. siliconcompiler/tools/bluespec/convert.py +2 -1
  13. siliconcompiler/tools/chisel/convert.py +2 -1
  14. siliconcompiler/tools/genfasm/bitstream.py +2 -2
  15. siliconcompiler/tools/ghdl/convert.py +2 -2
  16. siliconcompiler/tools/gtkwave/show.py +2 -1
  17. siliconcompiler/tools/icarus/compile.py +2 -2
  18. siliconcompiler/tools/klayout/drc.py +2 -1
  19. siliconcompiler/tools/magic/magic.py +1 -1
  20. siliconcompiler/tools/netgen/lvs.py +2 -1
  21. siliconcompiler/tools/openroad/_apr.py +16 -4
  22. siliconcompiler/tools/openroad/fillmetal_insertion.py +0 -1
  23. siliconcompiler/tools/openroad/init_floorplan.py +7 -1
  24. siliconcompiler/tools/openroad/macro_placement.py +1 -2
  25. siliconcompiler/tools/openroad/pin_placement.py +0 -1
  26. siliconcompiler/tools/openroad/rdlroute.py +2 -2
  27. siliconcompiler/tools/openroad/scripts/apr/preamble.tcl +3 -2
  28. siliconcompiler/tools/openroad/scripts/apr/sc_init_floorplan.tcl +1 -0
  29. siliconcompiler/tools/openroad/scripts/apr/sc_macro_placement.tcl +78 -94
  30. siliconcompiler/tools/openroad/scripts/apr/sc_power_grid.tcl +12 -1
  31. siliconcompiler/tools/openroad/scripts/apr/sc_repair_timing.tcl +24 -0
  32. siliconcompiler/tools/openroad/scripts/common/procs.tcl +3 -2
  33. siliconcompiler/tools/openroad/scripts/common/read_input_files.tcl +1 -0
  34. siliconcompiler/tools/openroad/scripts/common/reports.tcl +4 -13
  35. siliconcompiler/tools/openroad/scripts/common/write_data.tcl +2 -5
  36. siliconcompiler/tools/openroad/scripts/common/write_data_physical.tcl +3 -0
  37. siliconcompiler/tools/openroad/scripts/common/write_data_timing.tcl +1 -0
  38. siliconcompiler/tools/openroad/scripts/sc_rdlroute.tcl +1 -1
  39. siliconcompiler/tools/opensta/__init__.py +2 -2
  40. siliconcompiler/tools/opensta/report_libraries.py +2 -2
  41. siliconcompiler/tools/opensta/timing.py +2 -1
  42. siliconcompiler/tools/slang/__init__.py +79 -2
  43. siliconcompiler/tools/slang/elaborate.py +46 -0
  44. siliconcompiler/tools/slang/lint.py +10 -76
  45. siliconcompiler/tools/surelog/parse.py +1 -1
  46. siliconcompiler/tools/sv2v/convert.py +2 -2
  47. siliconcompiler/tools/template/template.py +2 -2
  48. siliconcompiler/tools/verilator/verilator.py +3 -1
  49. siliconcompiler/tools/vivado/vivado.py +2 -1
  50. siliconcompiler/tools/vpr/place.py +2 -2
  51. siliconcompiler/tools/vpr/route.py +2 -2
  52. siliconcompiler/tools/vpr/show.py +2 -1
  53. siliconcompiler/tools/yosys/__init__.py +26 -23
  54. siliconcompiler/tools/yosys/procs.tcl +17 -0
  55. siliconcompiler/tools/yosys/syn_asic.py +20 -65
  56. siliconcompiler/tools/yosys/syn_asic.tcl +10 -51
  57. siliconcompiler/toolscripts/_tools.json +4 -4
  58. siliconcompiler/toolscripts/rhel8/install-slang.sh +0 -0
  59. siliconcompiler/toolscripts/rhel8/install-sv2v.sh +7 -1
  60. siliconcompiler/toolscripts/rhel8/install-yosys.sh +1 -1
  61. siliconcompiler/toolscripts/rhel9/install-openroad.sh +34 -0
  62. siliconcompiler/toolscripts/rhel9/install-slang.sh +0 -0
  63. siliconcompiler/toolscripts/rhel9/install-sv2v.sh +7 -1
  64. siliconcompiler/toolscripts/rhel9/install-yosys.sh +1 -1
  65. siliconcompiler/toolscripts/ubuntu20/install-slang.sh +0 -0
  66. siliconcompiler/toolscripts/ubuntu20/install-surelog.sh +1 -0
  67. siliconcompiler/toolscripts/ubuntu20/install-sv2v.sh +7 -1
  68. siliconcompiler/toolscripts/ubuntu20/install-yosys.sh +1 -1
  69. siliconcompiler/toolscripts/ubuntu22/install-surelog.sh +7 -1
  70. siliconcompiler/toolscripts/ubuntu22/install-sv2v.sh +7 -1
  71. siliconcompiler/toolscripts/ubuntu22/install-yosys.sh +1 -1
  72. siliconcompiler/toolscripts/ubuntu24/install-bambu.sh +3 -4
  73. siliconcompiler/toolscripts/ubuntu24/install-slang.sh +0 -0
  74. siliconcompiler/toolscripts/ubuntu24/install-surelog.sh +7 -1
  75. siliconcompiler/toolscripts/ubuntu24/install-sv2v.sh +7 -1
  76. siliconcompiler/toolscripts/ubuntu24/install-yosys.sh +1 -1
  77. siliconcompiler/utils/__init__.py +24 -0
  78. siliconcompiler/utils/logging.py +67 -0
  79. {siliconcompiler-0.29.2.dist-info → siliconcompiler-0.29.4.dist-info}/METADATA +8 -8
  80. {siliconcompiler-0.29.2.dist-info → siliconcompiler-0.29.4.dist-info}/RECORD +80 -75
  81. siliconcompiler/tools/bambu/bambu.py +0 -32
  82. {siliconcompiler-0.29.2.dist-info → siliconcompiler-0.29.4.dist-info}/LICENSE +0 -0
  83. {siliconcompiler-0.29.2.dist-info → siliconcompiler-0.29.4.dist-info}/WHEEL +0 -0
  84. {siliconcompiler-0.29.2.dist-info → siliconcompiler-0.29.4.dist-info}/entry_points.txt +0 -0
  85. {siliconcompiler-0.29.2.dist-info → siliconcompiler-0.29.4.dist-info}/top_level.txt +0 -0
@@ -12,7 +12,9 @@ Installation: https://sv-lang.com/building.html
12
12
  '''
13
13
  import re
14
14
  from siliconcompiler import sc_open
15
- from siliconcompiler.tools._common import get_tool_task, record_metric
15
+ from siliconcompiler.tools._common import record_metric
16
+ from siliconcompiler.tools._common import \
17
+ get_frontend_options, get_input_files, get_tool_task
16
18
 
17
19
 
18
20
  ################################
@@ -38,7 +40,6 @@ def parse_version(stdout):
38
40
  def post_process(chip):
39
41
  step = chip.get('arg', 'step')
40
42
  index = chip.get('arg', 'index')
41
- tool, task = get_tool_task(chip, step, index)
42
43
 
43
44
  log = f'{step}.log'
44
45
  with sc_open(log) as f:
@@ -47,3 +48,79 @@ def post_process(chip):
47
48
  if match:
48
49
  record_metric(chip, step, index, 'errors', match.group(1), log)
49
50
  record_metric(chip, step, index, 'warnings', match.group(2), log)
51
+
52
+
53
+ def common_runtime_options(chip):
54
+ options = []
55
+
56
+ step = chip.get('arg', 'step')
57
+ index = chip.get('arg', 'index')
58
+ tool, task = get_tool_task(chip, step, index)
59
+
60
+ options.extend(['-j', str(chip.get('tool', tool, 'task', task, 'threads',
61
+ step=step, index=index))])
62
+
63
+ opts = get_frontend_options(chip,
64
+ ['ydir',
65
+ 'idir',
66
+ 'vlib',
67
+ 'libext',
68
+ 'define',
69
+ 'param'])
70
+
71
+ if opts['libext']:
72
+ options.append(f'--libext {",".join(opts["libext"])}')
73
+
74
+ #####################
75
+ # Library directories
76
+ #####################
77
+ if opts['ydir']:
78
+ options.append(f'-y {",".join(opts["ydir"])}')
79
+
80
+ #####################
81
+ # Library files
82
+ #####################
83
+ if opts['vlib']:
84
+ options.append(f'-libfile {",".join(opts["vlib"])}')
85
+
86
+ #####################
87
+ # Include paths
88
+ #####################
89
+ if opts['idir']:
90
+ options.append(f'--include-directory {",".join(opts["idir"])}')
91
+
92
+ #######################
93
+ # Variable Definitions
94
+ #######################
95
+ for value in opts['define']:
96
+ options.append('-D ' + value)
97
+
98
+ #######################
99
+ # Command files
100
+ #######################
101
+ cmdfiles = get_input_files(chip, 'input', 'cmdfile', 'f')
102
+ if cmdfiles:
103
+ options.append(f'-F {",".join(cmdfiles)}')
104
+
105
+ #######################
106
+ # Sources
107
+ #######################
108
+ for value in get_input_files(chip, 'input', 'rtl', 'systemverilog'):
109
+ options.append(value)
110
+ for value in get_input_files(chip, 'input', 'rtl', 'verilog'):
111
+ options.append(value)
112
+
113
+ #######################
114
+ # Top Module
115
+ #######################
116
+ options.append('--top ' + chip.top())
117
+
118
+ ###############################
119
+ # Parameters (top module only)
120
+ ###############################
121
+ # Set up user-provided parameters to ensure we elaborate the correct modules
122
+ for param, value in opts['param']:
123
+ value = value.replace('"', '\\"')
124
+ options.append(f'-G {param}={value}')
125
+
126
+ return options
@@ -0,0 +1,46 @@
1
+ from siliconcompiler import utils
2
+ from siliconcompiler.tools import slang
3
+ from siliconcompiler.tools._common import \
4
+ add_require_input, add_frontend_requires, get_tool_task, has_input_files
5
+
6
+
7
+ def setup(chip):
8
+ '''
9
+ Elaborate verilog design files and generate a unified file.
10
+ '''
11
+ slang.setup(chip)
12
+
13
+ step = chip.get('arg', 'step')
14
+ index = chip.get('arg', 'index')
15
+ tool, task = get_tool_task(chip, step, index)
16
+
17
+ chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
18
+ clobber=False, step=step, index=index)
19
+
20
+ add_require_input(chip, 'input', 'rtl', 'verilog')
21
+ add_require_input(chip, 'input', 'rtl', 'systemverilog')
22
+ add_frontend_requires(chip, ['ydir', 'idir', 'vlib', 'libext', 'define', 'param'])
23
+
24
+ chip.set('tool', tool, 'task', task, 'stdout', 'destination', 'output', step=step, index=index)
25
+ chip.set('tool', tool, 'task', task, 'stdout', 'suffix', 'v', step=step, index=index)
26
+
27
+ chip.set('tool', tool, 'task', task, 'output', __outputfile(chip), step=step, index=index)
28
+
29
+
30
+ def runtime_options(chip):
31
+ options = slang.common_runtime_options(chip)
32
+ options.extend([
33
+ "--preprocess",
34
+ "--comments",
35
+ "--ignore-unknown-modules",
36
+ "--allow-use-before-declare"
37
+ ])
38
+
39
+ return options
40
+
41
+
42
+ def __outputfile(chip):
43
+ is_systemverilog = has_input_files(chip, 'input', 'rtl', 'systemverilog')
44
+ if is_systemverilog:
45
+ return f'{chip.top()}.sv'
46
+ return f'{chip.top()}.v'
@@ -1,20 +1,20 @@
1
- '''
2
- Lint system verilog
3
- '''
1
+ from siliconcompiler import utils
4
2
  from siliconcompiler.tools import slang
5
3
  from siliconcompiler.tools._common import \
6
- add_require_input, add_frontend_requires, get_frontend_options, get_input_files, get_tool_task
7
- import os
4
+ add_require_input, add_frontend_requires, get_tool_task
8
5
 
9
6
 
10
7
  def setup(chip):
8
+ '''
9
+ Lint system verilog
10
+ '''
11
11
  slang.setup(chip)
12
12
 
13
13
  step = chip.get('arg', 'step')
14
14
  index = chip.get('arg', 'index')
15
15
  tool, task = get_tool_task(chip, step, index)
16
16
 
17
- chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
17
+ chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
18
18
  clobber=False, step=step, index=index)
19
19
 
20
20
  add_require_input(chip, 'input', 'rtl', 'verilog')
@@ -23,76 +23,10 @@ def setup(chip):
23
23
 
24
24
 
25
25
  def runtime_options(chip):
26
- options = ["-lint-only"]
27
-
28
- step = chip.get('arg', 'step')
29
- index = chip.get('arg', 'index')
30
- tool, task = get_tool_task(chip, step, index)
31
-
32
- options.extend(['-j', str(chip.get('tool', tool, 'task', task, 'threads',
33
- step=step, index=index))])
34
-
35
- opts = get_frontend_options(chip,
36
- ['ydir',
37
- 'idir',
38
- 'vlib',
39
- 'libext',
40
- 'define',
41
- 'param'])
42
-
43
- if opts['libext']:
44
- options.append(f'--libext {",".join(opts["libext"])}')
45
-
46
- #####################
47
- # Library directories
48
- #####################
49
- if opts['ydir']:
50
- options.append(f'-y {",".join(opts["ydir"])}')
51
-
52
- #####################
53
- # Library files
54
- #####################
55
- if opts['vlib']:
56
- options.append(f'-libfile {",".join(opts["vlib"])}')
57
-
58
- #####################
59
- # Include paths
60
- #####################
61
- if opts['idir']:
62
- options.append(f'--include-directory {",".join(opts["idir"])}')
63
-
64
- #######################
65
- # Variable Definitions
66
- #######################
67
- for value in opts['define']:
68
- options.append('-D ' + value)
69
-
70
- #######################
71
- # Command files
72
- #######################
73
- cmdfiles = get_input_files(chip, 'input', 'cmdfile', 'f')
74
- if cmdfiles:
75
- options.append(f'-F {",".join(cmdfiles)}')
76
-
77
- #######################
78
- # Sources
79
- #######################
80
- for value in get_input_files(chip, 'input', 'rtl', 'systemverilog'):
81
- options.append(value)
82
- for value in get_input_files(chip, 'input', 'rtl', 'verilog'):
83
- options.append(value)
84
-
85
- #######################
86
- # Top Module
87
- #######################
88
- options.append('--top ' + chip.top())
89
-
90
- ###############################
91
- # Parameters (top module only)
92
- ###############################
93
- # Set up user-provided parameters to ensure we elaborate the correct modules
94
- for param, value in opts['param']:
95
- options.append(f'-G {param}={value}')
26
+ options = slang.common_runtime_options(chip)
27
+ options.extend([
28
+ "--lint-only"
29
+ ])
96
30
 
97
31
  return options
98
32
 
@@ -28,7 +28,7 @@ def setup(chip):
28
28
  _, task = get_tool_task(chip, step, index)
29
29
 
30
30
  # Runtime parameters.
31
- chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
31
+ chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
32
32
  step=step, index=index, clobber=False)
33
33
 
34
34
  # Input/Output requirements
@@ -1,4 +1,4 @@
1
- import os
1
+ from siliconcompiler import utils
2
2
  from siliconcompiler.tools._common import input_provides
3
3
 
4
4
 
@@ -23,7 +23,7 @@ def setup(chip):
23
23
  chip.set('tool', tool, 'vswitch', '--numeric-version')
24
24
  chip.set('tool', tool, 'version', '>=0.0.9', clobber=False)
25
25
 
26
- chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
26
+ chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
27
27
  step=step, index=index, clobber=False)
28
28
 
29
29
  # Since we run sv2v after the import/preprocess step, there should be no
@@ -8,7 +8,7 @@ Sources: https://
8
8
  Installation: https://
9
9
  '''
10
10
 
11
- import os
11
+ from siliconcompiler import utils
12
12
  import siliconcompiler
13
13
  from siliconcompiler.tools._common import get_tool_task
14
14
 
@@ -60,7 +60,7 @@ def setup(chip):
60
60
 
61
61
  chip.set('tool', tool, 'task', task, 'option', options,
62
62
  step=step, index=index, clobber=False)
63
- chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
63
+ chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
64
64
  step=step, index=index, clobber=False)
65
65
 
66
66
  # Required for script based tools
@@ -24,6 +24,7 @@ Installation: https://verilator.org/guide/latest/install.html
24
24
  '''
25
25
 
26
26
  import os
27
+ from siliconcompiler import utils
27
28
  from siliconcompiler.tools._common import (
28
29
  add_frontend_requires,
29
30
  get_frontend_options,
@@ -59,7 +60,7 @@ def setup(chip):
59
60
 
60
61
  # Common to all tasks
61
62
  # Max threads
62
- chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
63
+ chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
63
64
  step=step, index=index, clobber=False)
64
65
 
65
66
  # Basic warning and error grep check on logfile
@@ -136,6 +137,7 @@ def runtime_options(chip):
136
137
  cmdlist.append(value)
137
138
 
138
139
  for param, value in frontend_opts['param']:
140
+ value = value.replace('"', '\\"')
139
141
  cmdlist.append(f'-G{param}={value}')
140
142
 
141
143
  if os.path.isfile(f'inputs/{design}.v'):
@@ -8,6 +8,7 @@ Documentation: https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/
8
8
  import json
9
9
  import os
10
10
  import re
11
+ from siliconcompiler import utils
11
12
  from siliconcompiler import sc_open
12
13
  from siliconcompiler.tools._common import record_metric
13
14
 
@@ -47,7 +48,7 @@ def setup_task(chip, task):
47
48
  chip.set('tool', tool, 'task', task, 'refdir', refdir, step=step, index=index,
48
49
  package='siliconcompiler', clobber=False)
49
50
  chip.set('tool', tool, 'task', task, 'script', script, step=step, index=index, clobber=False)
50
- chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
51
+ chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
51
52
  step=step, index=index, clobber=False)
52
53
  chip.set('tool', tool, 'task', task, 'option', option, step=step, index=index, clobber=False)
53
54
 
@@ -1,5 +1,5 @@
1
- import os
2
1
  import shutil
2
+ from siliconcompiler import utils
3
3
  from siliconcompiler import SiliconCompilerError
4
4
  from siliconcompiler.tools.vpr import vpr
5
5
  from siliconcompiler.tools.vpr._json_constraint import load_constraints_map
@@ -21,7 +21,7 @@ def setup(chip, clobber=True):
21
21
 
22
22
  vpr.setup_tool(chip, clobber=clobber)
23
23
 
24
- chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
24
+ chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
25
25
  step=step, index=index, clobber=False)
26
26
 
27
27
  design = chip.top()
@@ -1,6 +1,6 @@
1
- import os
2
1
  import shutil
3
2
 
3
+ from siliconcompiler import utils
4
4
  from siliconcompiler.tools.vpr import vpr
5
5
  from siliconcompiler.tools._common import get_tool_task
6
6
 
@@ -30,7 +30,7 @@ def setup(chip, clobber=True):
30
30
  ",".join(['tool', tool, 'task', task, 'var', 'max_router_iterations']),
31
31
  step=step, index=index)
32
32
 
33
- chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
33
+ chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
34
34
  step=step, index=index, clobber=clobber)
35
35
 
36
36
  # TO-DO: PRIOROTIZE the post-routing packing results?
@@ -1,4 +1,5 @@
1
1
  import os
2
+ from siliconcompiler import utils
2
3
  from siliconcompiler import SiliconCompilerError
3
4
  from siliconcompiler.tools.vpr import vpr
4
5
  from siliconcompiler.tools._common import get_tool_task
@@ -16,7 +17,7 @@ def setup(chip, clobber=True):
16
17
 
17
18
  vpr.setup_tool(chip, clobber=clobber)
18
19
 
19
- chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
20
+ chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
20
21
  step=step, index=index, clobber=False)
21
22
 
22
23
 
@@ -12,7 +12,7 @@ Sources: https://github.com/YosysHQ/yosys
12
12
 
13
13
  Installation: https://github.com/YosysHQ/yosys
14
14
  '''
15
-
15
+ import os
16
16
  import re
17
17
  import json
18
18
  from siliconcompiler import sc_open
@@ -107,28 +107,31 @@ def syn_post_process(chip):
107
107
  step = chip.get('arg', 'step')
108
108
  index = chip.get('arg', 'index')
109
109
 
110
- with sc_open("reports/stat.json") as f:
111
- metrics = json.load(f)
112
- if "design" in metrics:
113
- metrics = metrics["design"]
114
-
115
- if "area" in metrics:
116
- record_metric(chip, step, index, 'cellarea',
117
- float(metrics["area"]),
118
- "reports/stat.json",
119
- source_unit='um^2')
120
- if "num_cells" in metrics:
121
- record_metric(chip, step, index, 'cells',
122
- metrics["num_cells"],
123
- "reports/stat.json")
124
- if "num_wire_bits" in metrics:
125
- record_metric(chip, step, index, 'nets',
126
- metrics["num_wire_bits"],
127
- "reports/stat.json")
128
- if "num_port_bits" in metrics:
129
- record_metric(chip, step, index, 'pins',
130
- metrics["num_port_bits"],
131
- "reports/stat.json")
110
+ if os.path.exists("reports/stat.json"):
111
+ with sc_open("reports/stat.json") as f:
112
+ metrics = json.load(f)
113
+ if "design" in metrics:
114
+ metrics = metrics["design"]
115
+
116
+ if "area" in metrics:
117
+ record_metric(chip, step, index, 'cellarea',
118
+ float(metrics["area"]),
119
+ "reports/stat.json",
120
+ source_unit='um^2')
121
+ if "num_cells" in metrics:
122
+ record_metric(chip, step, index, 'cells',
123
+ metrics["num_cells"],
124
+ "reports/stat.json")
125
+ if "num_wire_bits" in metrics:
126
+ record_metric(chip, step, index, 'nets',
127
+ metrics["num_wire_bits"],
128
+ "reports/stat.json")
129
+ if "num_port_bits" in metrics:
130
+ record_metric(chip, step, index, 'pins',
131
+ metrics["num_port_bits"],
132
+ "reports/stat.json")
133
+ else:
134
+ chip.logger.warning("Yosys cell statistics are missing")
132
135
 
133
136
  registers = None
134
137
  with sc_open(f"{step}.log") as f:
@@ -52,3 +52,20 @@ proc sc_apply_params { } {
52
52
  }
53
53
  }
54
54
  }
55
+
56
+ proc sc_get_scratchpad { name } {
57
+ yosys echo off
58
+ set value [yosys tee -q -s result.string scratchpad -get $name]
59
+ yosys echo on
60
+
61
+ return $value
62
+ }
63
+
64
+ proc sc_load_plugin { name } {
65
+ catch { yosys tee -q -s sc.load.test plugin -i $name }
66
+ set load_test [sc_get_scratchpad sc.load.test]
67
+ if { [string first "ERROR" $load_test] == -1 } {
68
+ return 1
69
+ }
70
+ return 0
71
+ }
@@ -8,6 +8,7 @@ from siliconcompiler import sc_open
8
8
  from siliconcompiler import utils
9
9
  from siliconcompiler.tools._common.asic import set_tool_task_var, get_libraries, get_mainlib, \
10
10
  CellArea
11
+ from siliconcompiler.tools._common.asic_clock import get_clock_period
11
12
  from siliconcompiler.tools._common import get_tool_task
12
13
 
13
14
 
@@ -75,12 +76,11 @@ def setup_asic(chip):
75
76
  # set default control knobs
76
77
  mainlib = get_mainlib(chip)
77
78
  for option, value in [
78
- ('flatten', "true"),
79
- ('auto_flatten', "true"),
80
- ('hier_iterations', "10"),
81
- ('hier_threshold', "1000"),
82
- ('autoname', "true"),
83
- ('add_buffers', "true")]:
79
+ ('flatten', True),
80
+ ('auto_flatten', True),
81
+ ('hier_threshold', 1000),
82
+ ('autoname', True),
83
+ ('add_buffers', True)]:
84
84
  chip.set('tool', tool, 'task', task, 'var', option, value,
85
85
  step=step, index=index, clobber=False)
86
86
  chip.add('tool', tool, 'task', task, 'require',
@@ -185,6 +185,14 @@ def setup_asic(chip):
185
185
  'Instance limit for the number of cells in a module to preserve.',
186
186
  field='help')
187
187
 
188
+ chip.set('tool', tool, 'task', task, 'var', 'hierarchy_separator',
189
+ 'control the hierarchy separator used during design flattening', field='help')
190
+ chip.set('tool', tool, 'task', task, 'var', 'hierarchy_separator', '/',
191
+ step=step, index=index, clobber=False)
192
+ chip.add('tool', tool, 'task', task, 'require',
193
+ ','.join(['tool', tool, 'task', task, 'var', 'hierarchy_separator']),
194
+ step=step, index=index)
195
+
188
196
  set_tool_task_var(chip, 'map_clockgates',
189
197
  default_value=False,
190
198
  schelp='Map clockgates during synthesis.')
@@ -379,11 +387,9 @@ def _get_synthesis_library_key(chip, lib, corners):
379
387
 
380
388
 
381
389
  def get_abc_period(chip):
382
-
383
- tool = 'yosys'
384
390
  step = chip.get('arg', 'step')
385
391
  index = chip.get('arg', 'index')
386
- _, task = get_tool_task(chip, step, index)
392
+ tool, task = get_tool_task(chip, step, index)
387
393
 
388
394
  mainlib = get_mainlib(chip)
389
395
 
@@ -392,67 +398,16 @@ def get_abc_period(chip):
392
398
  if abc_clock_period:
393
399
  return abc_clock_period[0]
394
400
 
395
- period = None
396
-
397
401
  abc_clock_multiplier = float(chip.get('library', mainlib, 'option', 'var',
398
402
  'yosys_abc_clock_multiplier')[0])
399
403
 
400
- # get clock information from sdc files
401
- # TODO: fix for fpga/asic differentiation later
402
- if chip.valid('input', 'constraint', 'sdc'):
403
- for sdc in chip.find_files('input', 'constraint', 'sdc', step=step, index=index):
404
- lines = []
405
- with sc_open(sdc) as f:
406
- lines = f.read().splitlines()
407
-
408
- # collect simple variables in case clock is specified with a variable
409
- re_var = r"[A-Za-z0-9_]+"
410
- re_num = r"[0-9\.]+"
411
- sdc_vars = {}
412
- for line in lines:
413
- tcl_variable = re.findall(fr"^\s*set\s+({re_var})\s+({re_num})", line)
414
- if tcl_variable:
415
- var_name, var_value = tcl_variable[0]
416
- sdc_vars[f'${var_name}'] = float(var_value)
417
-
418
- # TODO: handle line continuations
419
- for line in lines:
420
- clock_period = re.findall(fr"create_clock\s.*-period\s+({re_num}|\${re_var})",
421
- line)
422
- if clock_period:
423
- clock_period = clock_period[0]
424
- if clock_period[0] == '$':
425
- if clock_period in sdc_vars:
426
- clock_period = sdc_vars[clock_period]
427
- else:
428
- chip.logger.warning('Unable to identify clock period from '
429
- f'{clock_period}.')
430
- continue
431
- else:
432
- clock_period = float(clock_period)
433
-
434
- clock_period = clock_period * abc_clock_multiplier
435
-
436
- if period is None:
437
- period = clock_period
438
- else:
439
- period = min(period, clock_period)
440
-
441
- if period is None:
442
- # get clock information from defined clocks
443
- for pin in chip.getkeys('datasheet', 'pin'):
444
- for mode in chip.getkeys('datasheet', 'pin', pin, 'type'):
445
- if chip.get('datasheet', 'pin', pin, 'type', mode) == 'clock':
446
- clock_period = min(chip.get('datasheet', 'pin', pin, 'tperiod', mode)) * 1e12
447
-
448
- if period is None:
449
- period = clock_period
450
- else:
451
- period = min(period, clock_period)
452
-
453
- if period is None:
404
+ _, period = get_clock_period(chip,
405
+ clock_units_multiplier=abc_clock_multiplier / 1000)
406
+ if not period:
454
407
  return None
455
408
 
409
+ period *= 1000
410
+
456
411
  abc_clock_derating = chip.get('tool', tool, 'task', task, 'var', 'abc_clock_derating',
457
412
  step=step, index=index)
458
413
  if abc_clock_derating: