siliconcompiler 0.29.2__py3-none-any.whl → 0.29.4__py3-none-any.whl

siliconcompiler/tools/gtkwave/show.py

@@ -3,6 +3,7 @@ import os
 from siliconcompiler.tools.gtkwave import setup as tool_setup
 from siliconcompiler.tools._common import \
     add_require_input, get_tool_task, input_provides
+from siliconcompiler import utils
 
 
 def setup(chip):
@@ -16,7 +17,7 @@ def setup(chip):
     index = chip.get('arg', 'index')
     tool, task = get_tool_task(chip, step, index)
 
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index)
 
     chip.set('tool', tool, 'task', task, 'refdir',

siliconcompiler/tools/icarus/compile.py

@@ -1,7 +1,7 @@
-import os
 from siliconcompiler.tools._common import \
     add_require_input, add_frontend_requires, get_input_files, get_frontend_options, \
     get_tool_task
+from siliconcompiler import utils
 
 
 def setup(chip):
@@ -20,7 +20,7 @@ def setup(chip):
     chip.set('tool', tool, 'vswitch', '-V')
     chip.set('tool', tool, 'version', '>=10.3', clobber=False)
 
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=False)
 
     chip.set('tool', tool, 'task', task, 'var', 'verilog_generation',

siliconcompiler/tools/klayout/drc.py

@@ -7,6 +7,7 @@ from siliconcompiler.tools._common.asic import set_tool_task_var, get_tool_task_
 
 from siliconcompiler.tools.klayout.klayout import setup as setup_tool
 import xml.etree.ElementTree as ET
+from siliconcompiler import utils
 
 
 def make_docs(chip):
@@ -35,7 +36,7 @@ def setup(chip):
     chip.set('tool', tool, 'task', task, 'option', option,
              step=step, index=index, clobber=clobber)
 
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=clobber)
 
     chip.add('tool', tool, 'task', task, 'require', 'option,pdk')

siliconcompiler/tools/magic/magic.py

@@ -47,7 +47,7 @@ def setup(chip):
     chip.set('tool', tool, 'version', '>=8.3.196', clobber=False)
     chip.set('tool', tool, 'format', 'tcl')
 
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=False)
     chip.set('tool', tool, 'task', task, 'refdir', refdir,
              step=step, index=index,

siliconcompiler/tools/netgen/lvs.py

@@ -1,5 +1,6 @@
 import os
 
+from siliconcompiler import utils
 from siliconcompiler.tools.netgen import count_lvs
 from siliconcompiler import sc_open
 from siliconcompiler.tools._common import get_tool_task, record_metric
@@ -24,7 +25,7 @@ def setup(chip):
     chip.set('tool', tool, 'version', '>=1.5.192', clobber=False)
     chip.set('tool', tool, 'format', 'tcl')
 
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=False)
     chip.set('tool', tool, 'task', task, 'refdir', refdir,
              step=step, index=index,

siliconcompiler/tools/openroad/_apr.py

@@ -16,7 +16,7 @@ def setup(chip, exit=True):
     index = chip.get('arg', 'index')
     tool, task = get_tool_task(chip, step, index)
 
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index)
 
     pdkname = chip.get('option', 'pdk')
@@ -148,6 +148,10 @@ def extract_metrics(chip):
 
     metrics_file = "reports/metrics.json"
 
+    if not os.path.exists(metrics_file):
+        chip.logger.warning("OpenROAD metrics file is missing")
+        return
+
     def get_metric_sources(metric):
         metric_sources = [metrics_file]
         if metric in metric_reports:
@@ -572,6 +576,13 @@ def define_rsz_params(chip):
                       default_value='100',
                       schelp='percentage of violating nets to attempt to repair (0 - 100)')
 
+    set_tool_task_var(chip, param_key='rsz_skip_recover_power',
+                      default_value=False,
+                      schelp='skip power recovery')
+    set_tool_task_var(chip, param_key='rsz_recover_power',
+                      default_value=100,
+                      schelp='percentage of paths to attempt to recover power (0 - 100)')
+
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
     tool, task = get_tool_task(chip, step, index)
@@ -792,6 +803,10 @@ def define_psm_params(chip):
              'list of nets to skip power grid analysis on',
              field='help')
 
+    chip.set('tool', tool, 'task', task, 'var', 'psm_allow_missing_terminal_nets',
+             'list of nets where a missing terminal is acceptable',
+             field='help')
+
 
 def define_fin_params(chip):
     set_tool_task_var(chip, param_key='fin_add_fill',
@@ -810,9 +825,6 @@ def define_mpl_params(chip):
                       schelp='macro channel to use when performing automated '
                              'macro placement ([x, y] in microns)')
 
-    set_tool_task_var(chip, param_key='rtlmp_enable',
-                      default_value=True,
-                      schelp='true/false, enables the RTLMP macro placement')
     set_tool_task_var(chip, param_key='rtlmp_min_instances',
                       schelp='minimum number of instances to use while clustering for '
                              'macro placement')

siliconcompiler/tools/openroad/fillmetal_insertion.py

@@ -43,7 +43,6 @@ def setup(chip):
         'hold',
         'unconstrained',
         'clock_skew',
-        'power',
         'drv_violations',
         'fmax',
 

siliconcompiler/tools/openroad/init_floorplan.py

@@ -1,5 +1,5 @@
 from siliconcompiler.tools._common import input_provides, add_common_file, get_tool_task
-from siliconcompiler.tools._common.asic import set_tool_task_var
+from siliconcompiler.tools._common.asic import set_tool_task_var, get_mainlib
 
 from siliconcompiler.tools.openroad._apr import setup as apr_setup
 from siliconcompiler.tools.openroad._apr import set_reports, set_pnr_inputs, set_pnr_outputs
@@ -74,6 +74,8 @@ def setup(chip):
         'power'
     ])
 
+    mainlib = get_mainlib(chip)
+
     # Setup required
     for component in chip.getkeys('constraint', 'component'):
         for key in chip.getkeys('constraint', 'component', component):
@@ -92,6 +94,10 @@ def setup(chip):
             chip.add('tool', tool, 'task', task, 'require',
                      ','.join(['constraint', ifp]),
                      step=step, index=index)
+    if chip.valid('library', mainlib, 'option', 'file', 'openroad_tracks'):
+        chip.add('tool', tool, 'task', task, 'require',
+                 ','.join(['library', mainlib, 'option', 'file', 'openroad_tracks']),
+                 step=step, index=index)
 
 
 def pre_process(chip):

siliconcompiler/tools/openroad/macro_placement.py

@@ -40,8 +40,7 @@ def setup(chip):
 
     set_reports(chip, [
         'setup',
-        'unconstrained',
-        'power'
+        'unconstrained'
     ])
 
 

siliconcompiler/tools/openroad/pin_placement.py

@@ -38,7 +38,6 @@ def setup(chip):
     set_reports(chip, [
         'setup',
         'unconstrained',
-        'power',
 
         # Images
         'placement_density',

siliconcompiler/tools/openroad/rdlroute.py

@@ -1,5 +1,6 @@
 import os
 
+from siliconcompiler import utils
 from siliconcompiler.tools._common import input_provides, get_tool_task
 from siliconcompiler.tools._common.asic import set_tool_task_var
 from siliconcompiler.tools.openroad._apr import build_pex_corners
@@ -44,7 +45,7 @@ def setup(chip):
              package='siliconcompiler')
     chip.set('tool', tool, 'task', task, 'script', script,
              step=step, index=index)
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=False)
 
     if chip.get('option', 'nodisplay'):
@@ -83,7 +84,6 @@ def setup(chip):
                  ','.join(['input', 'netlist', 'verilog']),
                  step=step, index=index)
 
-    chip.add('tool', tool, 'task', task, 'output', design + '.sdc', step=step, index=index)
     chip.add('tool', tool, 'task', task, 'output', design + '.vg', step=step, index=index)
     chip.add('tool', tool, 'task', task, 'output', design + '.def', step=step, index=index)
     chip.add('tool', tool, 'task', task, 'output', design + '.odb', step=step, index=index)

siliconcompiler/tools/openroad/scripts/apr/preamble.tcl

@@ -91,5 +91,6 @@ if { [llength $openroad_dont_touch] > 0 } {
     # set don't touch list
     set_dont_touch $openroad_dont_touch
 }
-tee -file reports/dont_touch.start.rpt {report_dont_touch}
-tee -file reports/dont_use.start.rpt {report_dont_use}
+tee -quiet -file reports/dont_touch.start.rpt {report_dont_touch}
+tee -quiet -file reports/dont_use.start.rpt {report_dont_use}
+tee -file reports/global_connections.start.rpt {report_global_connect}

siliconcompiler/tools/openroad/scripts/apr/sc_init_floorplan.tcl

@@ -25,6 +25,7 @@ if { [sc_cfg_tool_task_exists {file} global_connect] } {
         source $global_connect
     }
 }
+tee -file reports/global_connections.rpt {report_global_connect}
 
 ###############################
 # Initialize floorplan

siliconcompiler/tools/openroad/scripts/apr/sc_macro_placement.tcl

@@ -14,104 +14,88 @@ source -echo "$sc_refdir/apr/preamble.tcl"
 # Need to check if we have any macros before performing macro placement,
 # since we get an error otherwise.
 if { [sc_design_has_unplaced_macros] } {
-    if { [lindex [sc_cfg_tool_task_get var rtlmp_enable] 0] == "true" } {
-        ###############################
-        # Macro placement
-        ###############################
+    ###############################
+    # Macro placement
+    ###############################
 
-        lassign [sc_cfg_tool_task_get var macro_place_halo] halo_x halo_y
+    lassign [sc_cfg_tool_task_get var macro_place_halo] halo_x halo_y
 
-        set rtlmp_args []
-        set rtlmp_max_levels [lindex [sc_cfg_tool_task_get var rtlmp_max_levels] 0]
-        if { $rtlmp_max_levels != "" } {
-            lappend rtlmp_args -max_num_level $rtlmp_max_levels
-        }
-        set rtlmp_min_instances [lindex [sc_cfg_tool_task_get var rtlmp_min_instances] 0]
-        if { $rtlmp_min_instances != "" } {
-            lappend rtlmp_args -min_num_inst $rtlmp_min_instances
-        }
-        set rtlmp_max_instances [lindex [sc_cfg_tool_task_get var rtlmp_max_instances] 0]
-        if { $rtlmp_max_instances != "" } {
-            lappend rtlmp_args -max_num_inst $rtlmp_max_instances
-        }
-        set rtlmp_min_macros [lindex [sc_cfg_tool_task_get var rtlmp_min_macros] 0]
-        if { $rtlmp_min_macros != "" } {
-            lappend rtlmp_args -min_num_macro $rtlmp_min_macros
-        }
-        set rtlmp_max_macros [lindex [sc_cfg_tool_task_get var rtlmp_max_macros] 0]
-        if { $rtlmp_max_macros != "" } {
-            lappend rtlmp_args -max_num_macro $rtlmp_max_macros
-        }
-        set rtlmp_min_aspect_ratio [lindex [sc_cfg_tool_task_get var rtlmp_min_aspect_ratio] 0]
-        if { $rtlmp_min_aspect_ratio != "" } {
-            lappend rtlmp_args -min_ar $rtlmp_min_aspect_ratio
-        }
-        set rtlmp_fence [sc_cfg_tool_task_get var rtlmp_fence]
-        if { $rtlmp_fence != "" } {
-            lappend rtlmp_args -fence_lx [lindex $rtlmp_fence 0]
-            lappend rtlmp_args -fence_ly [lindex $rtlmp_fence 1]
-            lappend rtlmp_args -fence_ux [lindex $rtlmp_fence 2]
-            lappend rtlmp_args -fence_uy [lindex $rtlmp_fence 3]
-        }
-        set rtlmp_bus_planning [lindex [sc_cfg_tool_task_get var rtlmp_bus_planning] 0]
-        if { $rtlmp_bus_planning == "true" } {
-            lappend rtlmp_args -bus_planning
-        }
-        set rtlmp_target_dead_space [lindex [sc_cfg_tool_task_get var rtlmp_target_dead_space] 0]
-        if { $rtlmp_target_dead_space != "" } {
-            lappend rtlmp_args -target_dead_space $rtlmp_target_dead_space
-        }
-
-        set rtlmp_area_weight [lindex [sc_cfg_tool_task_get var rtlmp_area_weight] 0]
-        if { $rtlmp_area_weight != "" } {
-            lappend rtlmp_args -area_weight $rtlmp_area_weight
-        }
-        set rtlmp_outline_weight [lindex [sc_cfg_tool_task_get var rtlmp_outline_weight] 0]
-        if { $rtlmp_outline_weight != "" } {
-            lappend rtlmp_args -outline_weight $rtlmp_outline_weight
-        }
-        set rtlmp_wirelength_weight [lindex [sc_cfg_tool_task_get var rtlmp_wirelength_weight] 0]
-        if { $rtlmp_wirelength_weight != "" } {
-            lappend rtlmp_args -wirelength_weight $rtlmp_wirelength_weight
-        }
-        set rtlmp_guidance_weight [lindex [sc_cfg_tool_task_get var rtlmp_guidance_weight] 0]
-        if { $rtlmp_guidance_weight != "" } {
-            lappend rtlmp_args -guidance_weight $rtlmp_guidance_weight
-        }
-        set rtlmp_fence_weight [lindex [sc_cfg_tool_task_get var rtlmp_fence_weight] 0]
-        if { $rtlmp_fence_weight != "" } {
-            lappend rtlmp_args -fence_weight $rtlmp_fence_weight
-        }
-        set rtlmp_notch_weight [lindex [sc_cfg_tool_task_get var rtlmp_notch_weight] 0]
-        if { $rtlmp_notch_weight != "" } {
-            lappend rtlmp_args -notch_weight $rtlmp_notch_weight
-        }
-        set rtlmp_blockage_weight [lindex [sc_cfg_tool_task_get var rtlmp_blockage_weight] 0]
-        if { $rtlmp_blockage_weight != "" } {
-            lappend rtlmp_args -blockage_weight $rtlmp_blockage_weight
-        }
-
-        rtl_macro_placer \
-            -report_directory reports/rtlmp \
-            -halo_width $halo_x \
-            -halo_height $halo_y \
-            -target_util [sc_global_placement_density] \
-            {*}$rtlmp_args
-    } else {
-        ###############################
-        # TDMS Global Placement
-        ###############################
-
-        sc_global_placement -disable_routability_driven
-
-        ###############################
-        # Macro placement
-        ###############################
+    set rtlmp_args []
+    set rtlmp_max_levels [lindex [sc_cfg_tool_task_get var rtlmp_max_levels] 0]
+    if { $rtlmp_max_levels != "" } {
+        lappend rtlmp_args -max_num_level $rtlmp_max_levels
+    }
+    set rtlmp_min_instances [lindex [sc_cfg_tool_task_get var rtlmp_min_instances] 0]
+    if { $rtlmp_min_instances != "" } {
+        lappend rtlmp_args -min_num_inst $rtlmp_min_instances
+    }
+    set rtlmp_max_instances [lindex [sc_cfg_tool_task_get var rtlmp_max_instances] 0]
+    if { $rtlmp_max_instances != "" } {
+        lappend rtlmp_args -max_num_inst $rtlmp_max_instances
+    }
+    set rtlmp_min_macros [lindex [sc_cfg_tool_task_get var rtlmp_min_macros] 0]
+    if { $rtlmp_min_macros != "" } {
+        lappend rtlmp_args -min_num_macro $rtlmp_min_macros
+    }
+    set rtlmp_max_macros [lindex [sc_cfg_tool_task_get var rtlmp_max_macros] 0]
+    if { $rtlmp_max_macros != "" } {
+        lappend rtlmp_args -max_num_macro $rtlmp_max_macros
+    }
+    set rtlmp_min_aspect_ratio [lindex [sc_cfg_tool_task_get var rtlmp_min_aspect_ratio] 0]
+    if { $rtlmp_min_aspect_ratio != "" } {
+        lappend rtlmp_args -min_ar $rtlmp_min_aspect_ratio
+    }
+    set rtlmp_fence [sc_cfg_tool_task_get var rtlmp_fence]
+    if { $rtlmp_fence != "" } {
+        lappend rtlmp_args -fence_lx [lindex $rtlmp_fence 0]
+        lappend rtlmp_args -fence_ly [lindex $rtlmp_fence 1]
+        lappend rtlmp_args -fence_ux [lindex $rtlmp_fence 2]
+        lappend rtlmp_args -fence_uy [lindex $rtlmp_fence 3]
+    }
+    set rtlmp_bus_planning [lindex [sc_cfg_tool_task_get var rtlmp_bus_planning] 0]
+    if { $rtlmp_bus_planning == "true" } {
+        lappend rtlmp_args -bus_planning
+    }
+    set rtlmp_target_dead_space [lindex [sc_cfg_tool_task_get var rtlmp_target_dead_space] 0]
+    if { $rtlmp_target_dead_space != "" } {
+        lappend rtlmp_args -target_dead_space $rtlmp_target_dead_space
+    }
 
-        macro_placement \
-            -halo [sc_cfg_tool_task_get var macro_place_halo] \
-            -channel [sc_cfg_tool_task_get var macro_place_channel]
+    set rtlmp_area_weight [lindex [sc_cfg_tool_task_get var rtlmp_area_weight] 0]
+    if { $rtlmp_area_weight != "" } {
+        lappend rtlmp_args -area_weight $rtlmp_area_weight
+    }
+    set rtlmp_outline_weight [lindex [sc_cfg_tool_task_get var rtlmp_outline_weight] 0]
+    if { $rtlmp_outline_weight != "" } {
+        lappend rtlmp_args -outline_weight $rtlmp_outline_weight
+    }
+    set rtlmp_wirelength_weight [lindex [sc_cfg_tool_task_get var rtlmp_wirelength_weight] 0]
+    if { $rtlmp_wirelength_weight != "" } {
+        lappend rtlmp_args -wirelength_weight $rtlmp_wirelength_weight
     }
+    set rtlmp_guidance_weight [lindex [sc_cfg_tool_task_get var rtlmp_guidance_weight] 0]
+    if { $rtlmp_guidance_weight != "" } {
+        lappend rtlmp_args -guidance_weight $rtlmp_guidance_weight
+    }
+    set rtlmp_fence_weight [lindex [sc_cfg_tool_task_get var rtlmp_fence_weight] 0]
+    if { $rtlmp_fence_weight != "" } {
+        lappend rtlmp_args -fence_weight $rtlmp_fence_weight
+    }
+    set rtlmp_notch_weight [lindex [sc_cfg_tool_task_get var rtlmp_notch_weight] 0]
+    if { $rtlmp_notch_weight != "" } {
+        lappend rtlmp_args -notch_weight $rtlmp_notch_weight
+    }
+    set rtlmp_blockage_weight [lindex [sc_cfg_tool_task_get var rtlmp_blockage_weight] 0]
+    if { $rtlmp_blockage_weight != "" } {
+        lappend rtlmp_args -blockage_weight $rtlmp_blockage_weight
+    }
+
+    rtl_macro_placer \
+        -report_directory reports/rtlmp \
+        -halo_width $halo_x \
+        -halo_height $halo_y \
+        -target_util [sc_global_placement_density] \
+        {*}$rtlmp_args
 }
 
 sc_print_macro_information

siliconcompiler/tools/openroad/scripts/apr/sc_power_grid.tcl

@@ -33,6 +33,7 @@ foreach pdnconfig [sc_cfg_tool_task_get {file} pdn_config] {
 
     lappend pdn_files $pdnconfig
 }
+tee -quiet -file reports/power_grid_configuration.rpt {pdngen -report_only}
 pdngen -failed_via_report "reports/${sc_design}_pdngen_failed_vias.rpt"
 
 ###############################
@@ -47,10 +48,20 @@ foreach net [sc_supply_nets] {
 
 foreach net [sc_psm_check_nets] {
     puts "Check supply net: $net"
+
+    set check_args []
+    if {
+        [sc_check_version 18610] &&
+        [sc_cfg_tool_task_check_in_list $net var psm_allow_missing_terminal_nets]
+    } {
+        lappend check_args -dont_require_terminals
+    }
+
     check_power_grid \
         -floorplanning \
         -error_file "reports/power_grid_${net}.rpt" \
-        -net $net
+        -net $net \
+        {*}$check_args
 }
 
 ###############################

siliconcompiler/tools/openroad/scripts/apr/sc_repair_timing.tcl

@@ -20,6 +20,7 @@ set rsz_hold_slack_margin [lindex [sc_cfg_tool_task_get {var} rsz_hold_slack_mar
 set rsz_slew_margin [lindex [sc_cfg_tool_task_get {var} rsz_slew_margin] 0]
 set rsz_cap_margin [lindex [sc_cfg_tool_task_get {var} rsz_cap_margin] 0]
 set rsz_repair_tns [lindex [sc_cfg_tool_task_get {var} rsz_repair_tns] 0]
+set rsz_recover_power [lindex [sc_cfg_tool_task_get {var} rsz_recover_power] 0]
 
 set repair_timing_args []
 if { [lindex [sc_cfg_tool_task_get {var} rsz_skip_pin_swap] 0] == "true" } {
@@ -77,6 +78,29 @@ if { [lindex [sc_cfg_tool_task_get var rsz_skip_hold_repair] 0] != "true" } {
     sc_set_dont_use
 }
 
+if { [lindex [sc_cfg_tool_task_get var rsz_skip_recover_power] 0] != "true" } {
+    ###############################
+    # Recover power
+    ###############################
+
+    estimate_parasitics -placement
+
+    # Enable cells
+    sc_set_dont_use -hold -scanchain -multibit -report dont_use.repair_timing.power
+
+    repair_timing \
+        -recover_power $rsz_recover_power \
+        -verbose \
+        -setup_margin $rsz_setup_slack_margin \
+        -hold_margin $rsz_hold_slack_margin \
+        {*}$repair_timing_args
+
+    sc_detailed_placement
+
+    # Restore dont use
+    sc_set_dont_use
+}
+
 global_connect
 
 # estimate for metrics

siliconcompiler/tools/openroad/scripts/common/procs.tcl

@@ -581,7 +581,7 @@ proc sc_setup_sta { } {
 
     # Check timing setup
     if { [sc_cfg_tool_task_check_in_list check_setup var reports] } {
-        check_setup
+        tee -file "reports/check_timing_setup.rpt" {check_setup -verbose}
     }
 
     if { [llength [all_clocks]] == 0 } {
@@ -758,6 +758,7 @@ proc sc_set_dont_use { args } {
     }
 
     if { [info exists keys(-report)] } {
-        tee -file reports/$keys(-report).rpt {report_dont_use}
+        puts "Dont use report: reports/$keys(-report).rpt"
+        tee -quiet -file reports/$keys(-report).rpt {report_dont_use}
     }
 }

siliconcompiler/tools/openroad/scripts/common/read_input_files.tcl

@@ -56,4 +56,5 @@ if { [sc_has_input_files odb "input layout odb"] } {
             source $global_connect
         }
     }
+    tee -file reports/global_connections.rpt {report_global_connect}
 }

siliconcompiler/tools/openroad/scripts/common/reports.tcl

@@ -98,6 +98,10 @@ if { [sc_cfg_tool_task_check_in_list fmax var reports] } {
     }
 }
 
+if { [llength [all_clocks]] > 0 } {
+    tee -file "reports/timing/clocks.rpt" {report_clock_properties}
+}
+
 # get logic depth of design
 utl::metric_int "design__logic__depth" [sc_count_logic_depth]
 
@@ -164,17 +168,4 @@ foreach markerdb [[ord::get_db_block] getMarkerCategories] {
 
 utl::push_metrics_stage "sc__cellarea__{}"
 tee -file reports/cell_usage.rpt {report_cell_usage -verbose}
-
-foreach modinst [[ord::get_db_block] getModInsts] {
-    tee -quiet -append -file reports/cell_usage.rpt { puts "" }
-    tee -quiet -append -file reports/cell_usage.rpt {
-    puts "########################################################"
-}
-    tee -quiet -append -file reports/cell_usage.rpt { puts "" }
-
-    utl::metric "design__instance__name__in_module:[[$modinst getMaster] getName]" \
-        [$modinst getHierarchicalName]
-    tee -quiet -append -file reports/cell_usage.rpt \
-        "report_cell_usage -verbose [$modinst getHierarchicalName]"
-}
 utl::pop_metrics_stage

siliconcompiler/tools/openroad/scripts/common/write_data.tcl

@@ -1,5 +1,2 @@
-write_db "outputs/${sc_design}.odb"
-write_sdc "outputs/${sc_design}.sdc"
-
-write_def "outputs/${sc_design}.def"
-write_verilog -include_pwr_gnd "outputs/${sc_design}.vg"
+source "$sc_refdir/common/write_data_physical.tcl"
+source "$sc_refdir/common/write_data_timing.tcl"

siliconcompiler/tools/openroad/scripts/common/write_data_physical.tcl

@@ -0,0 +1,3 @@
+write_db "outputs/${sc_design}.odb"
+write_def "outputs/${sc_design}.def"
+write_verilog -include_pwr_gnd "outputs/${sc_design}.vg"

siliconcompiler/tools/openroad/scripts/common/write_data_timing.tcl

@@ -0,0 +1 @@
+write_sdc "outputs/${sc_design}.sdc"

siliconcompiler/tools/openroad/scripts/sc_rdlroute.tcl

@@ -180,5 +180,5 @@ utl::pop_metrics_stage
 ###############################
 
 utl::push_metrics_stage "sc__write__{}"
-source "$sc_refdir/common/write_data.tcl"
+source "$sc_refdir/common/write_data_physical.tcl"
 utl::pop_metrics_stage

siliconcompiler/tools/opensta/__init__.py

@@ -8,7 +8,7 @@ Sources: https://github.com/The-OpenROAD-Project/OpenSTA
 Installation: https://github.com/The-OpenROAD-Project/OpenSTA (also installed with OpenROAD)
 '''
 
-import os
+from siliconcompiler import utils
 from siliconcompiler.tools.openroad._apr import get_library_timing_keypaths
 from siliconcompiler.tools._common import get_tool_task
 from siliconcompiler.tools._common.asic import get_libraries
@@ -43,7 +43,7 @@ def setup(chip):
     chip.set('tool', tool, 'task', task, 'refdir', 'tools/opensta/scripts',
              step=step, index=index,
              package='siliconcompiler', clobber=False)
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=False)
 
     if delaymodel != 'nldm':

siliconcompiler/tools/opensta/report_libraries.py

@@ -1,4 +1,4 @@
-import os
+from siliconcompiler import utils
 from siliconcompiler.tools.opensta import setup as tool_setup
 from siliconcompiler.tools.opensta import runtime_options as tool_runtime_options
 from siliconcompiler.tools._common import get_tool_task
@@ -17,7 +17,7 @@ def setup(chip):
     chip.set('tool', tool, 'task', task, 'script', 'sc_report_libraries.tcl',
              step=step, index=index, clobber=False)
 
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index)
 
 

siliconcompiler/tools/opensta/timing.py

@@ -1,5 +1,6 @@
 import os
 import re
+from siliconcompiler import utils
 from siliconcompiler import sc_open, SiliconCompilerError
 from siliconcompiler.tools.opensta import setup as tool_setup
 from siliconcompiler.tools.opensta import runtime_options as tool_runtime_options
@@ -22,7 +23,7 @@ def setup(chip):
     chip.set('tool', tool, 'task', task, 'script', 'sc_timing.tcl',
              step=step, index=index, clobber=False)
 
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index)
 
     design = chip.top()