siliconcompiler 0.29.2__py3-none-any.whl → 0.29.3__py3-none-any.whl

siliconcompiler/tools/openroad/scripts/common/write_data_physical.tcl

@@ -0,0 +1,3 @@
+write_db "outputs/${sc_design}.odb"
+write_def "outputs/${sc_design}.def"
+write_verilog -include_pwr_gnd "outputs/${sc_design}.vg"

siliconcompiler/tools/openroad/scripts/common/write_data_timing.tcl

@@ -0,0 +1 @@
+write_sdc "outputs/${sc_design}.sdc"

siliconcompiler/tools/openroad/scripts/sc_rdlroute.tcl

@@ -180,5 +180,5 @@ utl::pop_metrics_stage
 ###############################
 
 utl::push_metrics_stage "sc__write__{}"
-source "$sc_refdir/common/write_data.tcl"
+source "$sc_refdir/common/write_data_physical.tcl"
 utl::pop_metrics_stage

siliconcompiler/tools/opensta/__init__.py

@@ -8,7 +8,7 @@ Sources: https://github.com/The-OpenROAD-Project/OpenSTA
 Installation: https://github.com/The-OpenROAD-Project/OpenSTA (also installed with OpenROAD)
 '''
 
-import os
+from siliconcompiler import utils
 from siliconcompiler.tools.openroad._apr import get_library_timing_keypaths
 from siliconcompiler.tools._common import get_tool_task
 from siliconcompiler.tools._common.asic import get_libraries
@@ -43,7 +43,7 @@ def setup(chip):
     chip.set('tool', tool, 'task', task, 'refdir', 'tools/opensta/scripts',
              step=step, index=index,
              package='siliconcompiler', clobber=False)
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=False)
 
     if delaymodel != 'nldm':

siliconcompiler/tools/opensta/report_libraries.py

@@ -1,4 +1,4 @@
-import os
+from siliconcompiler import utils
 from siliconcompiler.tools.opensta import setup as tool_setup
 from siliconcompiler.tools.opensta import runtime_options as tool_runtime_options
 from siliconcompiler.tools._common import get_tool_task
@@ -17,7 +17,7 @@ def setup(chip):
     chip.set('tool', tool, 'task', task, 'script', 'sc_report_libraries.tcl',
              step=step, index=index, clobber=False)
 
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index)
 
 

siliconcompiler/tools/opensta/timing.py

@@ -1,5 +1,6 @@
 import os
 import re
+from siliconcompiler import utils
 from siliconcompiler import sc_open, SiliconCompilerError
 from siliconcompiler.tools.opensta import setup as tool_setup
 from siliconcompiler.tools.opensta import runtime_options as tool_runtime_options
@@ -22,7 +23,7 @@ def setup(chip):
     chip.set('tool', tool, 'task', task, 'script', 'sc_timing.tcl',
              step=step, index=index, clobber=False)
 
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index)
 
     design = chip.top()

siliconcompiler/tools/slang/__init__.py

@@ -12,7 +12,9 @@ Installation: https://sv-lang.com/building.html
 '''
 import re
 from siliconcompiler import sc_open
-from siliconcompiler.tools._common import get_tool_task, record_metric
+from siliconcompiler.tools._common import record_metric
+from siliconcompiler.tools._common import \
+    get_frontend_options, get_input_files, get_tool_task
 
 
 ################################
@@ -38,7 +40,6 @@ def parse_version(stdout):
 def post_process(chip):
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
-    tool, task = get_tool_task(chip, step, index)
 
     log = f'{step}.log'
     with sc_open(log) as f:
@@ -47,3 +48,78 @@ def post_process(chip):
             if match:
                 record_metric(chip, step, index, 'errors', match.group(1), log)
                 record_metric(chip, step, index, 'warnings', match.group(2), log)
+
+
+def common_runtime_options(chip):
+    options = []
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    options.extend(['-j', str(chip.get('tool', tool, 'task', task, 'threads',
+                              step=step, index=index))])
+
+    opts = get_frontend_options(chip,
+                                ['ydir',
+                                 'idir',
+                                 'vlib',
+                                 'libext',
+                                 'define',
+                                 'param'])
+
+    if opts['libext']:
+        options.append(f'--libext {",".join(opts["libext"])}')
+
+    #####################
+    # Library directories
+    #####################
+    if opts['ydir']:
+        options.append(f'-y {",".join(opts["ydir"])}')
+
+    #####################
+    # Library files
+    #####################
+    if opts['vlib']:
+        options.append(f'-libfile {",".join(opts["vlib"])}')
+
+    #####################
+    # Include paths
+    #####################
+    if opts['idir']:
+        options.append(f'--include-directory {",".join(opts["idir"])}')
+
+    #######################
+    # Variable Definitions
+    #######################
+    for value in opts['define']:
+        options.append('-D ' + value)
+
+    #######################
+    # Command files
+    #######################
+    cmdfiles = get_input_files(chip, 'input', 'cmdfile', 'f')
+    if cmdfiles:
+        options.append(f'-F {",".join(cmdfiles)}')
+
+    #######################
+    # Sources
+    #######################
+    for value in get_input_files(chip, 'input', 'rtl', 'systemverilog'):
+        options.append(value)
+    for value in get_input_files(chip, 'input', 'rtl', 'verilog'):
+        options.append(value)
+
+    #######################
+    # Top Module
+    #######################
+    options.append('--top ' + chip.top())
+
+    ###############################
+    # Parameters (top module only)
+    ###############################
+    # Set up user-provided parameters to ensure we elaborate the correct modules
+    for param, value in opts['param']:
+        options.append(f'-G {param}={value}')
+
+    return options

siliconcompiler/tools/slang/elaborate.py

@@ -0,0 +1,46 @@
+from siliconcompiler import utils
+from siliconcompiler.tools import slang
+from siliconcompiler.tools._common import \
+    add_require_input, add_frontend_requires, get_tool_task, has_input_files
+
+
+def setup(chip):
+    '''
+    Elaborate verilog design files and generate a unified file.
+    '''
+    slang.setup(chip)
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
+             clobber=False, step=step, index=index)
+
+    add_require_input(chip, 'input', 'rtl', 'verilog')
+    add_require_input(chip, 'input', 'rtl', 'systemverilog')
+    add_frontend_requires(chip, ['ydir', 'idir', 'vlib', 'libext', 'define', 'param'])
+
+    chip.set('tool', tool, 'task', task, 'stdout', 'destination', 'output', step=step, index=index)
+    chip.set('tool', tool, 'task', task, 'stdout', 'suffix', 'v', step=step, index=index)
+
+    chip.set('tool', tool, 'task', task, 'output', __outputfile(chip), step=step, index=index)
+
+
+def runtime_options(chip):
+    options = slang.common_runtime_options(chip)
+    options.extend([
+        "--preprocess",
+        "--comments",
+        "--ignore-unknown-modules",
+        "--allow-use-before-declare"
+    ])
+
+    return options
+
+
+def __outputfile(chip):
+    is_systemverilog = has_input_files(chip, 'input', 'rtl', 'systemverilog')
+    if is_systemverilog:
+        return f'{chip.top()}.sv'
+    return f'{chip.top()}.v'

siliconcompiler/tools/slang/lint.py

@@ -1,20 +1,20 @@
-'''
-Lint system verilog
-'''
+from siliconcompiler import utils
 from siliconcompiler.tools import slang
 from siliconcompiler.tools._common import \
-    add_require_input, add_frontend_requires, get_frontend_options, get_input_files, get_tool_task
-import os
+    add_require_input, add_frontend_requires, get_tool_task
 
 
 def setup(chip):
+    '''
+    Lint system verilog
+    '''
     slang.setup(chip)
 
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
     tool, task = get_tool_task(chip, step, index)
 
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              clobber=False, step=step, index=index)
 
     add_require_input(chip, 'input', 'rtl', 'verilog')
@@ -23,76 +23,10 @@ def setup(chip):
 
 
 def runtime_options(chip):
-    options = ["-lint-only"]
-
-    step = chip.get('arg', 'step')
-    index = chip.get('arg', 'index')
-    tool, task = get_tool_task(chip, step, index)
-
-    options.extend(['-j', str(chip.get('tool', tool, 'task', task, 'threads',
-                              step=step, index=index))])
-
-    opts = get_frontend_options(chip,
-                                ['ydir',
-                                 'idir',
-                                 'vlib',
-                                 'libext',
-                                 'define',
-                                 'param'])
-
-    if opts['libext']:
-        options.append(f'--libext {",".join(opts["libext"])}')
-
-    #####################
-    # Library directories
-    #####################
-    if opts['ydir']:
-        options.append(f'-y {",".join(opts["ydir"])}')
-
-    #####################
-    # Library files
-    #####################
-    if opts['vlib']:
-        options.append(f'-libfile {",".join(opts["vlib"])}')
-
-    #####################
-    # Include paths
-    #####################
-    if opts['idir']:
-        options.append(f'--include-directory {",".join(opts["idir"])}')
-
-    #######################
-    # Variable Definitions
-    #######################
-    for value in opts['define']:
-        options.append('-D ' + value)
-
-    #######################
-    # Command files
-    #######################
-    cmdfiles = get_input_files(chip, 'input', 'cmdfile', 'f')
-    if cmdfiles:
-        options.append(f'-F {",".join(cmdfiles)}')
-
-    #######################
-    # Sources
-    #######################
-    for value in get_input_files(chip, 'input', 'rtl', 'systemverilog'):
-        options.append(value)
-    for value in get_input_files(chip, 'input', 'rtl', 'verilog'):
-        options.append(value)
-
-    #######################
-    # Top Module
-    #######################
-    options.append('--top ' + chip.top())
-
-    ###############################
-    # Parameters (top module only)
-    ###############################
-    # Set up user-provided parameters to ensure we elaborate the correct modules
-    for param, value in opts['param']:
-        options.append(f'-G {param}={value}')
+    options = slang.common_runtime_options(chip)
+    options.extend([
+        "--lint-only"
+    ])
 
     return options
 

siliconcompiler/tools/surelog/parse.py

@@ -28,7 +28,7 @@ def setup(chip):
     _, task = get_tool_task(chip, step, index)
 
     # Runtime parameters.
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=False)
 
     # Input/Output requirements

siliconcompiler/tools/sv2v/convert.py

@@ -1,4 +1,4 @@
-import os
+from siliconcompiler import utils
 from siliconcompiler.tools._common import input_provides
 
 
@@ -23,7 +23,7 @@ def setup(chip):
     chip.set('tool', tool, 'vswitch', '--numeric-version')
     chip.set('tool', tool, 'version', '>=0.0.9', clobber=False)
 
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=False)
 
     # Since we run sv2v after the import/preprocess step, there should be no

siliconcompiler/tools/template/template.py

@@ -8,7 +8,7 @@ Sources: https://
 Installation: https://
 '''
 
-import os
+from siliconcompiler import utils
 import siliconcompiler
 from siliconcompiler.tools._common import get_tool_task
 
@@ -60,7 +60,7 @@ def setup(chip):
 
     chip.set('tool', tool, 'task', task, 'option', options,
              step=step, index=index, clobber=False)
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=False)
 
     # Required for script based tools

siliconcompiler/tools/verilator/verilator.py

@@ -24,6 +24,7 @@ Installation: https://verilator.org/guide/latest/install.html
 '''
 
 import os
+from siliconcompiler import utils
 from siliconcompiler.tools._common import (
     add_frontend_requires,
     get_frontend_options,
@@ -59,7 +60,7 @@ def setup(chip):
 
     # Common to all tasks
     # Max threads
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=False)
 
     # Basic warning and error grep check on logfile

siliconcompiler/tools/vivado/vivado.py

@@ -8,6 +8,7 @@ Documentation: https://www.amd.com/en/products/software/adaptive-socs-and-fpgas/
 import json
 import os
 import re
+from siliconcompiler import utils
 from siliconcompiler import sc_open
 from siliconcompiler.tools._common import record_metric
 
@@ -47,7 +48,7 @@ def setup_task(chip, task):
     chip.set('tool', tool, 'task', task, 'refdir', refdir, step=step, index=index,
              package='siliconcompiler', clobber=False)
     chip.set('tool', tool, 'task', task, 'script', script, step=step, index=index, clobber=False)
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=False)
     chip.set('tool', tool, 'task', task, 'option', option, step=step, index=index, clobber=False)
 

siliconcompiler/tools/vpr/place.py

@@ -1,5 +1,5 @@
-import os
 import shutil
+from siliconcompiler import utils
 from siliconcompiler import SiliconCompilerError
 from siliconcompiler.tools.vpr import vpr
 from siliconcompiler.tools.vpr._json_constraint import load_constraints_map
@@ -21,7 +21,7 @@ def setup(chip, clobber=True):
 
     vpr.setup_tool(chip, clobber=clobber)
 
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=False)
 
     design = chip.top()

siliconcompiler/tools/vpr/route.py

@@ -1,6 +1,6 @@
-import os
 import shutil
 
+from siliconcompiler import utils
 from siliconcompiler.tools.vpr import vpr
 from siliconcompiler.tools._common import get_tool_task
 
@@ -30,7 +30,7 @@ def setup(chip, clobber=True):
              ",".join(['tool', tool, 'task', task, 'var', 'max_router_iterations']),
              step=step, index=index)
 
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=clobber)
 
     # TO-DO: PRIOROTIZE the post-routing packing results?

siliconcompiler/tools/vpr/show.py

@@ -1,4 +1,5 @@
 import os
+from siliconcompiler import utils
 from siliconcompiler import SiliconCompilerError
 from siliconcompiler.tools.vpr import vpr
 from siliconcompiler.tools._common import get_tool_task
@@ -16,7 +17,7 @@ def setup(chip, clobber=True):
 
     vpr.setup_tool(chip, clobber=clobber)
 
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=False)
 
 

siliconcompiler/tools/yosys/syn_asic.py

@@ -185,6 +185,14 @@ def setup_asic(chip):
              'Instance limit for the number of cells in a module to preserve.',
              field='help')
 
+    chip.set('tool', tool, 'task', task, 'var', 'hierarchy_separator',
+             'control the hierarchy separator used during design flattening', field='help')
+    chip.set('tool', tool, 'task', task, 'var', 'hierarchy_separator', '/',
+             step=step, index=index, clobber=False)
+    chip.add('tool', tool, 'task', task, 'require',
+             ','.join(['tool', tool, 'task', task, 'var', 'hierarchy_separator']),
+             step=step, index=index)
+
     set_tool_task_var(chip, 'map_clockgates',
                       default_value=False,
                       schelp='Map clockgates during synthesis.')

siliconcompiler/tools/yosys/syn_asic.tcl

@@ -233,6 +233,10 @@ if { [sc_cfg_tool_task_exists file synth_extra_map] } {
     }
 }
 
+# Specify hierarchy separator
+yosys scratchpad \
+    -set flatten.separator "[lindex [sc_cfg_tool_task_get var hierarchy_separator] 0]"
+
 # Start synthesis
 yosys synth {*}$synth_args -top $sc_design -run begin:fine
 

siliconcompiler/toolscripts/_tools.json

@@ -1,7 +1,7 @@
 {
   "openroad": {
     "git-url": "https://github.com/The-OpenROAD-Project/OpenROAD.git",
-    "git-commit": "beba944a7c9eaface2ae88040ac721272b22e9d3",
+    "git-commit": "44e36144112da6b2a3bb346ca0d0b692b6d117ca",
     "docker-cmds": [
       "# Remove OR-Tools files",
       "RUN rm -f $SC_PREFIX/Makefile $SC_PREFIX/README.md",
@@ -36,7 +36,7 @@
     "auto-update": false
   },
   "klayout": {
-    "version": "0.29.10",
+    "version": "0.29.11",
     "git-url": "https://github.com/KLayout/klayout.git",
     "docker-skip": true,
     "auto-update": true,
@@ -91,7 +91,7 @@
   },
   "yosys": {
     "git-url": "https://github.com/YosysHQ/yosys.git",
-    "git-commit": "v0.48",
+    "git-commit": "v0.49",
     "version-prefix": "",
     "auto-update": true
   },

siliconcompiler/toolscripts/rhel8/install-sv2v.sh

@@ -11,7 +11,13 @@ cd deps
 sudo yum group install -y "Development Tools"
 sudo yum install -y gmp-devel xz
 
-curl -sSL https://get.haskellstack.org/ | sh -s - -f
+haskell_args=""
+if [ ! -z ${PREFIX} ]; then
+    haskell_args="-d $PREFIX"
+    export PATH="$PREFIX:$PATH"
+fi
+
+curl -sSL https://get.haskellstack.org/ | sh -s - -f $haskell_args
 
 git clone $(python3 ${src_path}/_tools.py --tool sv2v --field git-url) sv2v
 cd sv2v

siliconcompiler/toolscripts/rhel9/install-sv2v.sh

@@ -11,7 +11,13 @@ cd deps
 sudo yum group install -y "Development Tools"
 sudo yum install -y gmp-devel xz
 
-curl -sSL https://get.haskellstack.org/ | sh -s - -f
+haskell_args=""
+if [ ! -z ${PREFIX} ]; then
+    haskell_args="-d $PREFIX"
+    export PATH="$PREFIX:$PATH"
+fi
+
+curl -sSL https://get.haskellstack.org/ | sh -s - -f $haskell_args
 
 git clone $(python3 ${src_path}/_tools.py --tool sv2v --field git-url) sv2v
 cd sv2v

siliconcompiler/toolscripts/ubuntu20/install-surelog.sh

@@ -16,6 +16,7 @@ cd deps
 
 python3 -m venv .surelog --clear
 . .surelog/bin/activate
+python3 -m pip install --upgrade pip
 python3 -m pip install cmake
 python3 -m pip install orderedmultidict
 

siliconcompiler/toolscripts/ubuntu20/install-sv2v.sh

@@ -10,7 +10,13 @@ cd deps
 
 sudo apt-get install -y curl
 
-curl -sSL https://get.haskellstack.org/ | sh
+haskell_args=""
+if [ ! -z ${PREFIX} ]; then
+    haskell_args="-d $PREFIX"
+    export PATH="$PREFIX:$PATH"
+fi
+
+curl -sSL https://get.haskellstack.org/ | sh -s - -f $haskell_args
 
 git clone $(python3 ${src_path}/_tools.py --tool sv2v --field git-url) sv2v
 cd sv2v

siliconcompiler/toolscripts/ubuntu22/install-surelog.sh

@@ -14,12 +14,18 @@ sudo apt-get install -y build-essential cmake git pkg-config \
 mkdir -p deps
 cd deps
 
+python3 -m venv .surelog --clear
+. .surelog/bin/activate
+python3 -m pip install --upgrade pip
+python3 -m pip install cmake
+python3 -m pip install orderedmultidict
+
 git clone $(python3 ${src_path}/_tools.py --tool surelog --field git-url) surelog
 cd surelog
 git checkout $(python3 ${src_path}/_tools.py --tool surelog --field git-commit)
 git submodule update --init --recursive
 
 make -j$(nproc)
-sudo make install
+sudo -E PATH="$PATH" make install
 
 cd -

siliconcompiler/toolscripts/ubuntu22/install-sv2v.sh

@@ -10,7 +10,13 @@ cd deps
 
 sudo apt-get install -y curl
 
-curl -sSL https://get.haskellstack.org/ | sh
+haskell_args=""
+if [ ! -z ${PREFIX} ]; then
+    haskell_args="-d $PREFIX"
+    export PATH="$PREFIX:$PATH"
+fi
+
+curl -sSL https://get.haskellstack.org/ | sh -s - -f $haskell_args
 
 git clone $(python3 ${src_path}/_tools.py --tool sv2v --field git-url) sv2v
 cd sv2v

siliconcompiler/toolscripts/ubuntu24/install-bambu.sh

@@ -12,9 +12,8 @@ sudo apt-get install -y autoconf autoconf-archive automake libtool \
     libfl-dev
 sudo apt-get install -y \
     gcc-11 gcc-11-multilib g++-11 g++-11-multilib \
-    llvm-11 llvm-11-dev libllvm11 \
-    gfortran-10 gfortran-10-multilib \
-    clang-11 libclang-11-dev
+    llvm-16 llvm-16-dev libllvm16 \
+    clang-16 libclang-16-dev
 
 mkdir -p deps
 cd deps
@@ -38,7 +37,7 @@ make -f Makefile.init
 mkdir obj
 cd obj
 
-../configure --enable-release --disable-flopoco --with-opt-level=2 $args
+CC=$(which gcc-11) CXX=$(which g++-11) ../configure --enable-release --disable-flopoco --with-opt-level=2 $args
 make -j$(nproc)
 make install
 

siliconcompiler/toolscripts/ubuntu24/install-surelog.sh

@@ -14,12 +14,18 @@ sudo apt-get install -y build-essential cmake git pkg-config \
 mkdir -p deps
 cd deps
 
+python3 -m venv .surelog --clear
+. .surelog/bin/activate
+python3 -m pip install --upgrade pip
+python3 -m pip install cmake
+python3 -m pip install orderedmultidict
+
 git clone $(python3 ${src_path}/_tools.py --tool surelog --field git-url) surelog
 cd surelog
 git checkout $(python3 ${src_path}/_tools.py --tool surelog --field git-commit)
 git submodule update --init --recursive
 
 make -j$(nproc)
-sudo make install
+sudo -E PATH="$PATH" make install
 
 cd -