siliconcompiler 0.29.2__py3-none-any.whl → 0.29.3__py3-none-any.whl

siliconcompiler/_metadata.py

@@ -1,5 +1,5 @@
 # Version number following semver standard.
-version = '0.29.2'
+version = '0.29.3'
 
 # Default server address for remote runs, if unspecified.
 default_server = 'https://server.siliconcompiler.com'

siliconcompiler/apps/sc_install.py

@@ -168,7 +168,7 @@ To system debugging information (this should only be used to debug):
     parser = argparse.ArgumentParser(
         prog=progname,
         description=description,
-        formatter_class=argparse.RawDescriptionHelpFormatter)
+        formatter_class=argparse.ArgumentDefaultsHelpFormatter)
 
     tools = _get_tools_list()
 

siliconcompiler/core.py

@@ -21,6 +21,7 @@ from siliconcompiler.remote import client
 from siliconcompiler.schema import Schema, SCHEMA_VERSION
 from siliconcompiler.schema import utils as schema_utils
 from siliconcompiler import utils
+from siliconcompiler.utils.logging import LoggerFormatter, ColorStreamFormatter
 from siliconcompiler import _metadata
 from siliconcompiler import NodeStatus, SiliconCompilerError
 from siliconcompiler.report import _show_summary_table
@@ -225,7 +226,8 @@ class Chip:
         else:
             in_run = False
 
-        log_format = ['%(levelname)-7s']
+        level_format = '%(levelname)-7s'
+        log_format = [level_format]
         if loglevel == 'debug':
             log_format.append('%(funcName)-10s')
             log_format.append('%(lineno)-4s')
@@ -261,14 +263,17 @@ class Chip:
             log_formatprefix = ""
 
         log_format.append('%(message)s')
-        logformat = log_formatprefix + ' | '.join(log_format)
+        stream_logformat = log_formatprefix + ' | '.join(log_format[1:])
 
         if not self.logger.hasHandlers():
             stream_handler = logging.StreamHandler(stream=sys.stdout)
             self.logger.addHandler(stream_handler)
 
         for handler in self.logger.handlers:
-            formatter = logging.Formatter(logformat)
+            if ColorStreamFormatter.supports_color(handler):
+                formatter = ColorStreamFormatter(log_formatprefix, level_format, stream_logformat)
+            else:
+                formatter = LoggerFormatter(log_formatprefix, level_format, stream_logformat)
             handler.setFormatter(formatter)
 
         self.logger.setLevel(schema_utils.translate_loglevel(loglevel))

siliconcompiler/flowgraph.py

@@ -205,18 +205,36 @@ def _get_flowgraph_execution_order(chip, flow, reverse=False):
             else:
                 ex_map.setdefault((istep, iindex), set()).add((step, index))
 
+    rev_ex_map = {}
+    for node, edges in ex_map.items():
+        for step, index in edges:
+            rev_ex_map.setdefault((step, index), set()).add(node)
+
     # Collect execution order of nodes
     if reverse:
         order = [set(_get_flowgraph_exit_nodes(chip, flow))]
     else:
         order = [set(_get_flowgraph_entry_nodes(chip, flow))]
 
+    visited = set()
     while True:
         next_level = set()
-        for step, index in order[-1]:
-            if (step, index) in ex_map and \
-               not any([(step, index) in v for v in ex_map.values()]):
-                next_level.update(ex_map.pop((step, index)))
+        next_visited = set()
+        for step, index in sorted(order[-1]):
+            if (step, index) not in rev_ex_map:
+                # No edges so assume inputs are okay
+                inputs_valid = True
+            else:
+                inputs_valid = all([node in visited for node in rev_ex_map[(step, index)]])
+
+            if inputs_valid:
+                next_visited.add((step, index))
+                if (step, index) in ex_map:
+                    next_level.update(ex_map.pop((step, index)))
+            else:
+                next_level.add((step, index))
+
+        visited.update(next_visited)
 
         if not next_level:
             break
@@ -233,7 +251,7 @@ def _get_flowgraph_execution_order(chip, flow, reverse=False):
 
     exec_order.reverse()
 
-    return exec_order
+    return [sorted(level) for level in exec_order]
 
 
 def get_executed_nodes(chip, flow):

siliconcompiler/scheduler/__init__.py

@@ -55,6 +55,10 @@ def _get_callback(hook):
     return None
 
 
+# Max lines to print from failed node log
+_failed_log_lines = 20
+
+
 ###############################################################################
 class SiliconCompilerTimeout(Exception):
     ''' Minimal Exception wrapper used to raise sc timeout errors.
@@ -833,6 +837,8 @@ def _run_executable_or_builtin(chip, step, index, version, toolpath, workdir, ru
     is_stderr_log = chip.get('tool', tool, 'task', task, 'stderr', 'destination',
                              step=step, index=index) == 'log' and stderr_file != stdout_file
 
+    chip.logger.info(f'Running in {workdir}')
+
     retcode = 0
     cmdlist = []
     cmd_args = []
@@ -877,7 +883,6 @@ def _run_executable_or_builtin(chip, step, index, version, toolpath, workdir, ru
         # Make record of tool options
         __record_tool(chip, step, index, version, toolpath, cmd_args)
 
-        chip.logger.info('Running in %s', workdir)
         chip.logger.info('%s', printable_cmd)
         timeout = chip.get('option', 'timeout', step=step, index=index)
         logfile = step + '.log'
@@ -988,10 +993,10 @@ def _run_executable_or_builtin(chip, step, index, version, toolpath, workdir, ru
         msg = f'Command failed with code {retcode}.'
         if logfile:
             if quiet:
-                # Print last 10 lines of log when in quiet mode
+                # Print last N lines of log when in quiet mode
                 with sc_open(logfile) as logfd:
                     loglines = logfd.read().splitlines()
-                    for logline in loglines[-10:]:
+                    for logline in loglines[-_failed_log_lines:]:
                         chip.logger.error(logline)
                 # No log file for pure-Python tools.
             msg += f' See log file {os.path.abspath(logfile)}'
@@ -1239,6 +1244,13 @@ def _finalizenode(chip, step, index, replay):
 
     if not is_skipped:
         _check_logfile(chip, step, index, quiet, run_func)
+
+    # Report metrics
+    for metric in ['errors', 'warnings']:
+        val = chip.get('metric', metric, step=step, index=index)
+        if val is not None:
+            chip.logger.info(f'Number of {metric}: {val}')
+
     _hash_files(chip, step, index)
 
     # Capture wall runtime and cpu cores
@@ -1535,12 +1547,13 @@ def _check_node_dependencies(chip, node, deps, deps_was_successful):
 def _launch_nodes(chip, nodes_to_run, processes, local_processes):
     running_nodes = {}
     max_parallel_run = chip.get('option', 'scheduler', 'maxnodes')
-    max_threads = os.cpu_count()
+    max_cores = utils.get_cores(chip)
+    max_threads = utils.get_cores(chip)
     if not max_parallel_run:
-        max_parallel_run = max_threads
+        max_parallel_run = utils.get_cores(chip)
 
-    # clip max parallel jobs to 1 <= jobs <= max_threads
-    max_parallel_run = max(1, min(max_parallel_run, max_threads))
+    # clip max parallel jobs to 1 <= jobs <= max_cores
+    max_parallel_run = max(1, min(max_parallel_run, max_cores))
 
     def allow_start(node):
         if node not in local_processes:
@@ -1561,7 +1574,7 @@ def _launch_nodes(chip, nodes_to_run, processes, local_processes):
         # clamp to max_parallel to avoid getting locked up
         requested_threads = max(1, min(requested_threads, max_threads))
 
-        if requested_threads + sum(running_nodes.values()) > max_threads:
+        if requested_threads + sum(running_nodes.values()) > max_cores:
             # delay until there are enough core available
             return False, 0
 
@@ -2062,7 +2075,6 @@ def check_logfile(chip, jobname=None, step=None, index='0',
                             chip.logger.info(f'{suffix}: {line_with_num}')
 
     for suffix in ordered_suffixes:
-        chip.logger.info(f'Number of {suffix}: {matches[suffix]}')
         checks[suffix]['report'].close()
 
     return matches

siliconcompiler/tools/bambu/convert.py

@@ -1,5 +1,6 @@
 import os
 import shutil
+from siliconcompiler import utils
 from siliconcompiler.tools._common import \
     add_frontend_requires, add_require_input, get_frontend_options, get_input_files, \
     get_tool_task, has_input_files
@@ -27,7 +28,7 @@ def setup(chip):
     chip.set('tool', tool, 'task', task, 'refdir', refdir,
              step=step, index=index,
              package='siliconcompiler', clobber=False)
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=False)
 
     # Input/Output requirements

siliconcompiler/tools/bluespec/convert.py

@@ -3,6 +3,7 @@ import shutil
 from siliconcompiler.tools._common import \
     add_require_input, add_frontend_requires, get_frontend_options, get_input_files, \
     get_tool_task, has_input_files
+from siliconcompiler import utils
 from siliconcompiler import sc_open
 
 # Directory inside step/index dir to store bsc intermediate results.
@@ -33,7 +34,7 @@ def setup(chip):
     chip.set('tool', tool, 'task', task, 'refdir', refdir,
              step=step, index=index,
              package='siliconcompiler', clobber=False)
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=False)
 
     # Input/Output requirements

siliconcompiler/tools/chisel/convert.py

@@ -3,6 +3,7 @@ import shutil
 import glob
 from siliconcompiler.tools._common import add_frontend_requires, get_tool_task, has_input_files
 from siliconcompiler import sc_open, SiliconCompilerError
+from siliconcompiler import utils
 
 
 def setup(chip):
@@ -28,7 +29,7 @@ def setup(chip):
     chip.set('tool', tool, 'task', task, 'refdir', refdir,
              step=step, index=index,
              package='siliconcompiler', clobber=False)
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=False)
 
     chip.set('tool', tool, 'task', task, 'option', ['-batch',

siliconcompiler/tools/genfasm/bitstream.py

@@ -1,5 +1,5 @@
-import os
 import shutil
+from siliconcompiler import utils
 from siliconcompiler.tools.genfasm import genfasm
 from siliconcompiler.tools.vpr import vpr
 from siliconcompiler.tools._common import get_tool_task
@@ -15,7 +15,7 @@ def setup(chip):
     index = chip.get('arg', 'index')
     tool, task = get_tool_task(chip, step, index)
 
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=False)
 
     chip.set('tool', tool, 'task', task, 'regex', 'warnings', "^Warning",

siliconcompiler/tools/ghdl/convert.py

@@ -1,6 +1,6 @@
-import os
 from siliconcompiler.tools._common import add_require_input, add_frontend_requires, \
     get_input_files, get_tool_task, has_input_files
+from siliconcompiler import utils
 
 
 def setup(chip):
@@ -23,7 +23,7 @@ def setup(chip):
     chip.set('tool', tool, 'vswitch', '--version')
     chip.set('tool', tool, 'version', '>=4.0.0-dev', clobber=clobber)
 
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=clobber)
     chip.set('tool', tool, 'task', task, 'option', '',
              step=step, index=index, clobber=clobber)

siliconcompiler/tools/gtkwave/show.py

@@ -3,6 +3,7 @@ import os
 from siliconcompiler.tools.gtkwave import setup as tool_setup
 from siliconcompiler.tools._common import \
     add_require_input, get_tool_task, input_provides
+from siliconcompiler import utils
 
 
 def setup(chip):
@@ -16,7 +17,7 @@ def setup(chip):
     index = chip.get('arg', 'index')
     tool, task = get_tool_task(chip, step, index)
 
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index)
 
     chip.set('tool', tool, 'task', task, 'refdir',

siliconcompiler/tools/icarus/compile.py

@@ -1,7 +1,7 @@
-import os
 from siliconcompiler.tools._common import \
     add_require_input, add_frontend_requires, get_input_files, get_frontend_options, \
     get_tool_task
+from siliconcompiler import utils
 
 
 def setup(chip):
@@ -20,7 +20,7 @@ def setup(chip):
     chip.set('tool', tool, 'vswitch', '-V')
     chip.set('tool', tool, 'version', '>=10.3', clobber=False)
 
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=False)
 
     chip.set('tool', tool, 'task', task, 'var', 'verilog_generation',

siliconcompiler/tools/klayout/drc.py

@@ -7,6 +7,7 @@ from siliconcompiler.tools._common.asic import set_tool_task_var, get_tool_task_
 
 from siliconcompiler.tools.klayout.klayout import setup as setup_tool
 import xml.etree.ElementTree as ET
+from siliconcompiler import utils
 
 
 def make_docs(chip):
@@ -35,7 +36,7 @@ def setup(chip):
     chip.set('tool', tool, 'task', task, 'option', option,
              step=step, index=index, clobber=clobber)
 
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=clobber)
 
     chip.add('tool', tool, 'task', task, 'require', 'option,pdk')

siliconcompiler/tools/magic/magic.py

@@ -47,7 +47,7 @@ def setup(chip):
     chip.set('tool', tool, 'version', '>=8.3.196', clobber=False)
     chip.set('tool', tool, 'format', 'tcl')
 
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=False)
     chip.set('tool', tool, 'task', task, 'refdir', refdir,
              step=step, index=index,

siliconcompiler/tools/netgen/lvs.py

@@ -1,5 +1,6 @@
 import os
 
+from siliconcompiler import utils
 from siliconcompiler.tools.netgen import count_lvs
 from siliconcompiler import sc_open
 from siliconcompiler.tools._common import get_tool_task, record_metric
@@ -24,7 +25,7 @@ def setup(chip):
     chip.set('tool', tool, 'version', '>=1.5.192', clobber=False)
     chip.set('tool', tool, 'format', 'tcl')
 
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=False)
     chip.set('tool', tool, 'task', task, 'refdir', refdir,
              step=step, index=index,

siliconcompiler/tools/openroad/_apr.py

@@ -16,7 +16,7 @@ def setup(chip, exit=True):
     index = chip.get('arg', 'index')
     tool, task = get_tool_task(chip, step, index)
 
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index)
 
     pdkname = chip.get('option', 'pdk')
@@ -792,6 +792,10 @@ def define_psm_params(chip):
              'list of nets to skip power grid analysis on',
              field='help')
 
+    chip.set('tool', tool, 'task', task, 'var', 'psm_allow_missing_terminal_nets',
+             'list of nets where a missing terminal is acceptable',
+             field='help')
+
 
 def define_fin_params(chip):
     set_tool_task_var(chip, param_key='fin_add_fill',
@@ -810,9 +814,6 @@ def define_mpl_params(chip):
                       schelp='macro channel to use when performing automated '
                              'macro placement ([x, y] in microns)')
 
-    set_tool_task_var(chip, param_key='rtlmp_enable',
-                      default_value=True,
-                      schelp='true/false, enables the RTLMP macro placement')
     set_tool_task_var(chip, param_key='rtlmp_min_instances',
                       schelp='minimum number of instances to use while clustering for '
                              'macro placement')

siliconcompiler/tools/openroad/rdlroute.py

@@ -1,5 +1,6 @@
 import os
 
+from siliconcompiler import utils
 from siliconcompiler.tools._common import input_provides, get_tool_task
 from siliconcompiler.tools._common.asic import set_tool_task_var
 from siliconcompiler.tools.openroad._apr import build_pex_corners
@@ -44,7 +45,7 @@ def setup(chip):
              package='siliconcompiler')
     chip.set('tool', tool, 'task', task, 'script', script,
              step=step, index=index)
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=False)
 
     if chip.get('option', 'nodisplay'):
@@ -83,7 +84,6 @@ def setup(chip):
                  ','.join(['input', 'netlist', 'verilog']),
                  step=step, index=index)
 
-    chip.add('tool', tool, 'task', task, 'output', design + '.sdc', step=step, index=index)
     chip.add('tool', tool, 'task', task, 'output', design + '.vg', step=step, index=index)
     chip.add('tool', tool, 'task', task, 'output', design + '.def', step=step, index=index)
     chip.add('tool', tool, 'task', task, 'output', design + '.odb', step=step, index=index)

siliconcompiler/tools/openroad/scripts/apr/sc_macro_placement.tcl

@@ -14,104 +14,88 @@ source -echo "$sc_refdir/apr/preamble.tcl"
 # Need to check if we have any macros before performing macro placement,
 # since we get an error otherwise.
 if { [sc_design_has_unplaced_macros] } {
-    if { [lindex [sc_cfg_tool_task_get var rtlmp_enable] 0] == "true" } {
-        ###############################
-        # Macro placement
-        ###############################
+    ###############################
+    # Macro placement
+    ###############################
 
-        lassign [sc_cfg_tool_task_get var macro_place_halo] halo_x halo_y
+    lassign [sc_cfg_tool_task_get var macro_place_halo] halo_x halo_y
 
-        set rtlmp_args []
-        set rtlmp_max_levels [lindex [sc_cfg_tool_task_get var rtlmp_max_levels] 0]
-        if { $rtlmp_max_levels != "" } {
-            lappend rtlmp_args -max_num_level $rtlmp_max_levels
-        }
-        set rtlmp_min_instances [lindex [sc_cfg_tool_task_get var rtlmp_min_instances] 0]
-        if { $rtlmp_min_instances != "" } {
-            lappend rtlmp_args -min_num_inst $rtlmp_min_instances
-        }
-        set rtlmp_max_instances [lindex [sc_cfg_tool_task_get var rtlmp_max_instances] 0]
-        if { $rtlmp_max_instances != "" } {
-            lappend rtlmp_args -max_num_inst $rtlmp_max_instances
-        }
-        set rtlmp_min_macros [lindex [sc_cfg_tool_task_get var rtlmp_min_macros] 0]
-        if { $rtlmp_min_macros != "" } {
-            lappend rtlmp_args -min_num_macro $rtlmp_min_macros
-        }
-        set rtlmp_max_macros [lindex [sc_cfg_tool_task_get var rtlmp_max_macros] 0]
-        if { $rtlmp_max_macros != "" } {
-            lappend rtlmp_args -max_num_macro $rtlmp_max_macros
-        }
-        set rtlmp_min_aspect_ratio [lindex [sc_cfg_tool_task_get var rtlmp_min_aspect_ratio] 0]
-        if { $rtlmp_min_aspect_ratio != "" } {
-            lappend rtlmp_args -min_ar $rtlmp_min_aspect_ratio
-        }
-        set rtlmp_fence [sc_cfg_tool_task_get var rtlmp_fence]
-        if { $rtlmp_fence != "" } {
-            lappend rtlmp_args -fence_lx [lindex $rtlmp_fence 0]
-            lappend rtlmp_args -fence_ly [lindex $rtlmp_fence 1]
-            lappend rtlmp_args -fence_ux [lindex $rtlmp_fence 2]
-            lappend rtlmp_args -fence_uy [lindex $rtlmp_fence 3]
-        }
-        set rtlmp_bus_planning [lindex [sc_cfg_tool_task_get var rtlmp_bus_planning] 0]
-        if { $rtlmp_bus_planning == "true" } {
-            lappend rtlmp_args -bus_planning
-        }
-        set rtlmp_target_dead_space [lindex [sc_cfg_tool_task_get var rtlmp_target_dead_space] 0]
-        if { $rtlmp_target_dead_space != "" } {
-            lappend rtlmp_args -target_dead_space $rtlmp_target_dead_space
-        }
-
-        set rtlmp_area_weight [lindex [sc_cfg_tool_task_get var rtlmp_area_weight] 0]
-        if { $rtlmp_area_weight != "" } {
-            lappend rtlmp_args -area_weight $rtlmp_area_weight
-        }
-        set rtlmp_outline_weight [lindex [sc_cfg_tool_task_get var rtlmp_outline_weight] 0]
-        if { $rtlmp_outline_weight != "" } {
-            lappend rtlmp_args -outline_weight $rtlmp_outline_weight
-        }
-        set rtlmp_wirelength_weight [lindex [sc_cfg_tool_task_get var rtlmp_wirelength_weight] 0]
-        if { $rtlmp_wirelength_weight != "" } {
-            lappend rtlmp_args -wirelength_weight $rtlmp_wirelength_weight
-        }
-        set rtlmp_guidance_weight [lindex [sc_cfg_tool_task_get var rtlmp_guidance_weight] 0]
-        if { $rtlmp_guidance_weight != "" } {
-            lappend rtlmp_args -guidance_weight $rtlmp_guidance_weight
-        }
-        set rtlmp_fence_weight [lindex [sc_cfg_tool_task_get var rtlmp_fence_weight] 0]
-        if { $rtlmp_fence_weight != "" } {
-            lappend rtlmp_args -fence_weight $rtlmp_fence_weight
-        }
-        set rtlmp_notch_weight [lindex [sc_cfg_tool_task_get var rtlmp_notch_weight] 0]
-        if { $rtlmp_notch_weight != "" } {
-            lappend rtlmp_args -notch_weight $rtlmp_notch_weight
-        }
-        set rtlmp_blockage_weight [lindex [sc_cfg_tool_task_get var rtlmp_blockage_weight] 0]
-        if { $rtlmp_blockage_weight != "" } {
-            lappend rtlmp_args -blockage_weight $rtlmp_blockage_weight
-        }
-
-        rtl_macro_placer \
-            -report_directory reports/rtlmp \
-            -halo_width $halo_x \
-            -halo_height $halo_y \
-            -target_util [sc_global_placement_density] \
-            {*}$rtlmp_args
-    } else {
-        ###############################
-        # TDMS Global Placement
-        ###############################
-
-        sc_global_placement -disable_routability_driven
-
-        ###############################
-        # Macro placement
-        ###############################
+    set rtlmp_args []
+    set rtlmp_max_levels [lindex [sc_cfg_tool_task_get var rtlmp_max_levels] 0]
+    if { $rtlmp_max_levels != "" } {
+        lappend rtlmp_args -max_num_level $rtlmp_max_levels
+    }
+    set rtlmp_min_instances [lindex [sc_cfg_tool_task_get var rtlmp_min_instances] 0]
+    if { $rtlmp_min_instances != "" } {
+        lappend rtlmp_args -min_num_inst $rtlmp_min_instances
+    }
+    set rtlmp_max_instances [lindex [sc_cfg_tool_task_get var rtlmp_max_instances] 0]
+    if { $rtlmp_max_instances != "" } {
+        lappend rtlmp_args -max_num_inst $rtlmp_max_instances
+    }
+    set rtlmp_min_macros [lindex [sc_cfg_tool_task_get var rtlmp_min_macros] 0]
+    if { $rtlmp_min_macros != "" } {
+        lappend rtlmp_args -min_num_macro $rtlmp_min_macros
+    }
+    set rtlmp_max_macros [lindex [sc_cfg_tool_task_get var rtlmp_max_macros] 0]
+    if { $rtlmp_max_macros != "" } {
+        lappend rtlmp_args -max_num_macro $rtlmp_max_macros
+    }
+    set rtlmp_min_aspect_ratio [lindex [sc_cfg_tool_task_get var rtlmp_min_aspect_ratio] 0]
+    if { $rtlmp_min_aspect_ratio != "" } {
+        lappend rtlmp_args -min_ar $rtlmp_min_aspect_ratio
+    }
+    set rtlmp_fence [sc_cfg_tool_task_get var rtlmp_fence]
+    if { $rtlmp_fence != "" } {
+        lappend rtlmp_args -fence_lx [lindex $rtlmp_fence 0]
+        lappend rtlmp_args -fence_ly [lindex $rtlmp_fence 1]
+        lappend rtlmp_args -fence_ux [lindex $rtlmp_fence 2]
+        lappend rtlmp_args -fence_uy [lindex $rtlmp_fence 3]
+    }
+    set rtlmp_bus_planning [lindex [sc_cfg_tool_task_get var rtlmp_bus_planning] 0]
+    if { $rtlmp_bus_planning == "true" } {
+        lappend rtlmp_args -bus_planning
+    }
+    set rtlmp_target_dead_space [lindex [sc_cfg_tool_task_get var rtlmp_target_dead_space] 0]
+    if { $rtlmp_target_dead_space != "" } {
+        lappend rtlmp_args -target_dead_space $rtlmp_target_dead_space
+    }
 
-        macro_placement \
-            -halo [sc_cfg_tool_task_get var macro_place_halo] \
-            -channel [sc_cfg_tool_task_get var macro_place_channel]
+    set rtlmp_area_weight [lindex [sc_cfg_tool_task_get var rtlmp_area_weight] 0]
+    if { $rtlmp_area_weight != "" } {
+        lappend rtlmp_args -area_weight $rtlmp_area_weight
+    }
+    set rtlmp_outline_weight [lindex [sc_cfg_tool_task_get var rtlmp_outline_weight] 0]
+    if { $rtlmp_outline_weight != "" } {
+        lappend rtlmp_args -outline_weight $rtlmp_outline_weight
+    }
+    set rtlmp_wirelength_weight [lindex [sc_cfg_tool_task_get var rtlmp_wirelength_weight] 0]
+    if { $rtlmp_wirelength_weight != "" } {
+        lappend rtlmp_args -wirelength_weight $rtlmp_wirelength_weight
     }
+    set rtlmp_guidance_weight [lindex [sc_cfg_tool_task_get var rtlmp_guidance_weight] 0]
+    if { $rtlmp_guidance_weight != "" } {
+        lappend rtlmp_args -guidance_weight $rtlmp_guidance_weight
+    }
+    set rtlmp_fence_weight [lindex [sc_cfg_tool_task_get var rtlmp_fence_weight] 0]
+    if { $rtlmp_fence_weight != "" } {
+        lappend rtlmp_args -fence_weight $rtlmp_fence_weight
+    }
+    set rtlmp_notch_weight [lindex [sc_cfg_tool_task_get var rtlmp_notch_weight] 0]
+    if { $rtlmp_notch_weight != "" } {
+        lappend rtlmp_args -notch_weight $rtlmp_notch_weight
+    }
+    set rtlmp_blockage_weight [lindex [sc_cfg_tool_task_get var rtlmp_blockage_weight] 0]
+    if { $rtlmp_blockage_weight != "" } {
+        lappend rtlmp_args -blockage_weight $rtlmp_blockage_weight
+    }
+
+    rtl_macro_placer \
+        -report_directory reports/rtlmp \
+        -halo_width $halo_x \
+        -halo_height $halo_y \
+        -target_util [sc_global_placement_density] \
+        {*}$rtlmp_args
 }
 
 sc_print_macro_information

siliconcompiler/tools/openroad/scripts/apr/sc_power_grid.tcl

@@ -47,10 +47,20 @@ foreach net [sc_supply_nets] {
 
 foreach net [sc_psm_check_nets] {
     puts "Check supply net: $net"
+
+    set check_args []
+    if {
+        [sc_check_version 18610] &&
+        [sc_cfg_tool_task_check_in_list $net var psm_allow_missing_terminal_nets]
+    } {
+        lappend check_args -dont_require_terminals
+    }
+
     check_power_grid \
         -floorplanning \
         -error_file "reports/power_grid_${net}.rpt" \
-        -net $net
+        -net $net \
+        {*}$check_args
 }
 
 ###############################

siliconcompiler/tools/openroad/scripts/common/procs.tcl

@@ -581,7 +581,7 @@ proc sc_setup_sta { } {
 
     # Check timing setup
     if { [sc_cfg_tool_task_check_in_list check_setup var reports] } {
-        check_setup
+        tee -file "reports/check_timing_setup.rpt" {check_setup -verbose}
     }
 
     if { [llength [all_clocks]] == 0 } {

siliconcompiler/tools/openroad/scripts/common/reports.tcl

@@ -98,6 +98,10 @@ if { [sc_cfg_tool_task_check_in_list fmax var reports] } {
     }
 }
 
+if { [llength [all_clocks]] > 0 } {
+    tee -file "reports/timing/clocks.rpt" {report_clock_properties}
+}
+
 # get logic depth of design
 utl::metric_int "design__logic__depth" [sc_count_logic_depth]
 

siliconcompiler/tools/openroad/scripts/common/write_data.tcl

@@ -1,5 +1,2 @@
-write_db "outputs/${sc_design}.odb"
-write_sdc "outputs/${sc_design}.sdc"
-
-write_def "outputs/${sc_design}.def"
-write_verilog -include_pwr_gnd "outputs/${sc_design}.vg"
+source "$sc_refdir/common/write_data_physical.tcl"
+source "$sc_refdir/common/write_data_timing.tcl"