siliconcompiler 0.29.1__py3-none-any.whl → 0.29.3__py3-none-any.whl

siliconcompiler/tools/openroad/_apr.py

@@ -5,7 +5,7 @@ from siliconcompiler import utils
 from siliconcompiler.tools._common import input_provides, add_common_file, \
     get_tool_task, record_metric
 from siliconcompiler.tools._common.asic import get_mainlib, set_tool_task_var, get_libraries, \
-    CellArea
+    CellArea, set_tool_task_lib_var
 from siliconcompiler.tools.openroad import setup as tool_setup
 
 
@@ -16,7 +16,7 @@ def setup(chip, exit=True):
     index = chip.get('arg', 'index')
     tool, task = get_tool_task(chip, step, index)
 
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index)
 
     pdkname = chip.get('option', 'pdk')
@@ -792,6 +792,10 @@ def define_psm_params(chip):
              'list of nets to skip power grid analysis on',
              field='help')
 
+    chip.set('tool', tool, 'task', task, 'var', 'psm_allow_missing_terminal_nets',
+             'list of nets where a missing terminal is acceptable',
+             field='help')
+
 
 def define_fin_params(chip):
     set_tool_task_var(chip, param_key='fin_add_fill',
@@ -810,9 +814,6 @@ def define_mpl_params(chip):
                       schelp='macro channel to use when performing automated '
                              'macro placement ([x, y] in microns)')
 
-    set_tool_task_var(chip, param_key='rtlmp_enable',
-                      default_value=True,
-                      schelp='true/false, enables the RTLMP macro placement')
     set_tool_task_var(chip, param_key='rtlmp_min_instances',
                       schelp='minimum number of instances to use while clustering for '
                              'macro placement')
@@ -894,6 +895,14 @@ def define_ord_params(chip):
                       require=['key'],
                       schelp='number of Y bins to use for heatmap image generation')
 
+    set_tool_task_lib_var(chip, param_key='scan_chain_cells',
+                          default_value=None,
+                          schelp='cells to use for scan chain insertion')
+
+    set_tool_task_lib_var(chip, param_key='multibit_ff_cells',
+                          default_value=None,
+                          schelp='multibit flipflop cells')
+
 
 def define_ord_files(chip):
     step = chip.get('arg', 'step')

siliconcompiler/tools/openroad/global_placement.py

@@ -1,9 +1,11 @@
 from siliconcompiler.tools._common import get_tool_task
 from siliconcompiler.tools.openroad._apr import setup as apr_setup
-from siliconcompiler.tools.openroad._apr import set_reports, set_pnr_inputs, set_pnr_outputs
+from siliconcompiler.tools.openroad._apr import set_reports, set_pnr_inputs, set_pnr_outputs, \
+    set_tool_task_var
 from siliconcompiler.tools.openroad._apr import \
     define_ord_params, define_sta_params, define_sdc_params, \
-    define_gpl_params, define_grt_params, define_rsz_params
+    define_gpl_params, define_grt_params, define_rsz_params, \
+    define_ppl_params
 from siliconcompiler.tools.openroad._apr import build_pex_corners, define_ord_files
 from siliconcompiler.tools.openroad._apr import extract_metrics
 
@@ -35,6 +37,7 @@ def setup(chip):
     define_gpl_params(chip)
     define_grt_params(chip)
     define_rsz_params(chip)
+    define_ppl_params(chip)
 
     set_reports(chip, [
         'setup',
@@ -48,6 +51,24 @@ def setup(chip):
         'power_density'
     ])
 
+    set_tool_task_var(chip, param_key='enable_multibit_clustering',
+                      default_value=False,
+                      schelp='true/false, when true multibit clustering will be performed.')
+
+    set_tool_task_var(chip, param_key='enable_scan_chains',
+                      default_value=False,
+                      schelp='true/false, when true scan chains will be inserted.')
+
+    set_tool_task_var(chip, param_key='scan_enable_port_pattern',
+                      schelp='pattern of the scan chain enable port.',
+                      skip=['pdk', 'lib'])
+    set_tool_task_var(chip, param_key='scan_in_port_pattern',
+                      schelp='pattern of the scan chain in port.',
+                      skip=['pdk', 'lib'])
+    set_tool_task_var(chip, param_key='scan_out_port_pattern',
+                      schelp='pattern of the scan chain out port.',
+                      skip=['pdk', 'lib'])
+
 
 def pre_process(chip):
     define_ord_files(chip)

siliconcompiler/tools/openroad/rdlroute.py

@@ -1,5 +1,6 @@
 import os
 
+from siliconcompiler import utils
 from siliconcompiler.tools._common import input_provides, get_tool_task
 from siliconcompiler.tools._common.asic import set_tool_task_var
 from siliconcompiler.tools.openroad._apr import build_pex_corners
@@ -44,7 +45,7 @@ def setup(chip):
              package='siliconcompiler')
     chip.set('tool', tool, 'task', task, 'script', script,
              step=step, index=index)
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=False)
 
     if chip.get('option', 'nodisplay'):
@@ -83,7 +84,6 @@ def setup(chip):
                  ','.join(['input', 'netlist', 'verilog']),
                  step=step, index=index)
 
-    chip.add('tool', tool, 'task', task, 'output', design + '.sdc', step=step, index=index)
     chip.add('tool', tool, 'task', task, 'output', design + '.vg', step=step, index=index)
     chip.add('tool', tool, 'task', task, 'output', design + '.def', step=step, index=index)
     chip.add('tool', tool, 'task', task, 'output', design + '.odb', step=step, index=index)

siliconcompiler/tools/openroad/scripts/apr/sc_clock_tree_synthesis.tcl

@@ -17,7 +17,7 @@ source -echo "$sc_refdir/apr/preamble.tcl"
 ###############################
 
 if { [llength [all_clocks]] > 0 } {
-    sc_set_dont_use -clock
+    sc_set_dont_use -clock -report dont_use.clock_tree_synthesis
 
     # Clone clock tree inverters next to register loads
     # so cts does not try to buffer the inverted clocks.

siliconcompiler/tools/openroad/scripts/apr/sc_global_placement.tcl

@@ -11,16 +11,79 @@ source ./sc_manifest.tcl > /dev/null
 set sc_refdir [sc_cfg_tool_task_get refdir]
 source -echo "$sc_refdir/apr/preamble.tcl"
 
+set dont_use_args []
+
+if { [lindex [sc_cfg_tool_task_get var enable_scan_chains] 0] == "true" } {
+    lappend dont_use_args -scanchain
+}
+if { [lindex [sc_cfg_tool_task_get var enable_multibit_clustering] 0] == "true" } {
+    lappend dont_use_args -multibit
+}
+
+sc_set_dont_use {*}$dont_use_args -report dont_use.global_placement
+
+###############################
+# Scan Chain Preparation
+###############################
+
+if { [lindex [sc_cfg_tool_task_get var enable_scan_chains] 0] == "true" } {
+    set dft_args []
+    if { [sc_cfg_tool_task_get var scan_in_port_pattern] != [] } {
+        lappend dft_args -scan_in_name_pattern \
+            [lindex [sc_cfg_tool_task_get var scan_in_port_pattern] 0]
+    }
+    if { [sc_cfg_tool_task_get var scan_out_port_pattern] != [] } {
+        lappend dft_args -scan_out_name_pattern \
+            [lindex [sc_cfg_tool_task_get var scan_out_port_pattern] 0]
+    }
+    if { [sc_cfg_tool_task_get var scan_enable_port_pattern] != [] } {
+        lappend dft_args -scan_enable_name_pattern \
+            [lindex [sc_cfg_tool_task_get var scan_enable_port_pattern] 0]
+    }
+
+    set_dft_config -clock_mixing clock_mix {*}$dft_args
+    tee -file reports/scan_chain_config.rpt {report_dft_config}
+    scan_replace
+}
+
+###############################
+# Perform multi-bit clustering
+###############################
+
+if { [lindex [sc_cfg_tool_task_get var enable_multibit_clustering] 0] == "true" } {
+    cluster_flops
+}
+
 ###############################
 # Global Placement
 ###############################
 
 sc_global_placement
 
-estimate_parasitics -placement
+###############################
+# Scan Chain Finalize
+###############################
+
+if { [lindex [sc_cfg_tool_task_get var enable_scan_chains] 0] == "true" } {
+    tee -file reports/scan_chain.rpt {preview_dft -verbose}
+    insert_dft
+
+    set new_ios [sc_get_unplaced_io_nets]
+    if { [llength $new_ios] > 0 } {
+        foreach net $new_ios {
+            utl::report "New IO net [$net getName]"
+        }
+        utl::warn FLW 1 "Scan chain generated new ports, rerunning pin placement"
+        sc_pin_placement
+    }
+}
 
 ###############################
 # Task Postamble
 ###############################
 
+sc_set_dont_use
+
+estimate_parasitics -placement
+
 source -echo "$sc_refdir/apr/postamble.tcl"

siliconcompiler/tools/openroad/scripts/apr/sc_macro_placement.tcl

@@ -14,104 +14,88 @@ source -echo "$sc_refdir/apr/preamble.tcl"
 # Need to check if we have any macros before performing macro placement,
 # since we get an error otherwise.
 if { [sc_design_has_unplaced_macros] } {
-    if { [lindex [sc_cfg_tool_task_get var rtlmp_enable] 0] == "true" } {
-        ###############################
-        # Macro placement
-        ###############################
+    ###############################
+    # Macro placement
+    ###############################
 
-        lassign [sc_cfg_tool_task_get var macro_place_halo] halo_x halo_y
+    lassign [sc_cfg_tool_task_get var macro_place_halo] halo_x halo_y
 
-        set rtlmp_args []
-        set rtlmp_max_levels [lindex [sc_cfg_tool_task_get var rtlmp_max_levels] 0]
-        if { $rtlmp_max_levels != "" } {
-            lappend rtlmp_args -max_num_level $rtlmp_max_levels
-        }
-        set rtlmp_min_instances [lindex [sc_cfg_tool_task_get var rtlmp_min_instances] 0]
-        if { $rtlmp_min_instances != "" } {
-            lappend rtlmp_args -min_num_inst $rtlmp_min_instances
-        }
-        set rtlmp_max_instances [lindex [sc_cfg_tool_task_get var rtlmp_max_instances] 0]
-        if { $rtlmp_max_instances != "" } {
-            lappend rtlmp_args -max_num_inst $rtlmp_max_instances
-        }
-        set rtlmp_min_macros [lindex [sc_cfg_tool_task_get var rtlmp_min_macros] 0]
-        if { $rtlmp_min_macros != "" } {
-            lappend rtlmp_args -min_num_macro $rtlmp_min_macros
-        }
-        set rtlmp_max_macros [lindex [sc_cfg_tool_task_get var rtlmp_max_macros] 0]
-        if { $rtlmp_max_macros != "" } {
-            lappend rtlmp_args -max_num_macro $rtlmp_max_macros
-        }
-        set rtlmp_min_aspect_ratio [lindex [sc_cfg_tool_task_get var rtlmp_min_aspect_ratio] 0]
-        if { $rtlmp_min_aspect_ratio != "" } {
-            lappend rtlmp_args -min_ar $rtlmp_min_aspect_ratio
-        }
-        set rtlmp_fence [sc_cfg_tool_task_get var rtlmp_fence]
-        if { $rtlmp_fence != "" } {
-            lappend rtlmp_args -fence_lx [lindex $rtlmp_fence 0]
-            lappend rtlmp_args -fence_ly [lindex $rtlmp_fence 1]
-            lappend rtlmp_args -fence_ux [lindex $rtlmp_fence 2]
-            lappend rtlmp_args -fence_uy [lindex $rtlmp_fence 3]
-        }
-        set rtlmp_bus_planning [lindex [sc_cfg_tool_task_get var rtlmp_bus_planning] 0]
-        if { $rtlmp_bus_planning == "true" } {
-            lappend rtlmp_args -bus_planning
-        }
-        set rtlmp_target_dead_space [lindex [sc_cfg_tool_task_get var rtlmp_target_dead_space] 0]
-        if { $rtlmp_target_dead_space != "" } {
-            lappend rtlmp_args -target_dead_space $rtlmp_target_dead_space
-        }
-
-        set rtlmp_area_weight [lindex [sc_cfg_tool_task_get var rtlmp_area_weight] 0]
-        if { $rtlmp_area_weight != "" } {
-            lappend rtlmp_args -area_weight $rtlmp_area_weight
-        }
-        set rtlmp_outline_weight [lindex [sc_cfg_tool_task_get var rtlmp_outline_weight] 0]
-        if { $rtlmp_outline_weight != "" } {
-            lappend rtlmp_args -outline_weight $rtlmp_outline_weight
-        }
-        set rtlmp_wirelength_weight [lindex [sc_cfg_tool_task_get var rtlmp_wirelength_weight] 0]
-        if { $rtlmp_wirelength_weight != "" } {
-            lappend rtlmp_args -wirelength_weight $rtlmp_wirelength_weight
-        }
-        set rtlmp_guidance_weight [lindex [sc_cfg_tool_task_get var rtlmp_guidance_weight] 0]
-        if { $rtlmp_guidance_weight != "" } {
-            lappend rtlmp_args -guidance_weight $rtlmp_guidance_weight
-        }
-        set rtlmp_fence_weight [lindex [sc_cfg_tool_task_get var rtlmp_fence_weight] 0]
-        if { $rtlmp_fence_weight != "" } {
-            lappend rtlmp_args -fence_weight $rtlmp_fence_weight
-        }
-        set rtlmp_notch_weight [lindex [sc_cfg_tool_task_get var rtlmp_notch_weight] 0]
-        if { $rtlmp_notch_weight != "" } {
-            lappend rtlmp_args -notch_weight $rtlmp_notch_weight
-        }
-        set rtlmp_blockage_weight [lindex [sc_cfg_tool_task_get var rtlmp_blockage_weight] 0]
-        if { $rtlmp_blockage_weight != "" } {
-            lappend rtlmp_args -blockage_weight $rtlmp_blockage_weight
-        }
-
-        rtl_macro_placer \
-            -report_directory reports/rtlmp \
-            -halo_width $halo_x \
-            -halo_height $halo_y \
-            -target_util [sc_global_placement_density] \
-            {*}$rtlmp_args
-    } else {
-        ###############################
-        # TDMS Global Placement
-        ###############################
-
-        sc_global_placement -disable_routability_driven
-
-        ###############################
-        # Macro placement
-        ###############################
+    set rtlmp_args []
+    set rtlmp_max_levels [lindex [sc_cfg_tool_task_get var rtlmp_max_levels] 0]
+    if { $rtlmp_max_levels != "" } {
+        lappend rtlmp_args -max_num_level $rtlmp_max_levels
+    }
+    set rtlmp_min_instances [lindex [sc_cfg_tool_task_get var rtlmp_min_instances] 0]
+    if { $rtlmp_min_instances != "" } {
+        lappend rtlmp_args -min_num_inst $rtlmp_min_instances
+    }
+    set rtlmp_max_instances [lindex [sc_cfg_tool_task_get var rtlmp_max_instances] 0]
+    if { $rtlmp_max_instances != "" } {
+        lappend rtlmp_args -max_num_inst $rtlmp_max_instances
+    }
+    set rtlmp_min_macros [lindex [sc_cfg_tool_task_get var rtlmp_min_macros] 0]
+    if { $rtlmp_min_macros != "" } {
+        lappend rtlmp_args -min_num_macro $rtlmp_min_macros
+    }
+    set rtlmp_max_macros [lindex [sc_cfg_tool_task_get var rtlmp_max_macros] 0]
+    if { $rtlmp_max_macros != "" } {
+        lappend rtlmp_args -max_num_macro $rtlmp_max_macros
+    }
+    set rtlmp_min_aspect_ratio [lindex [sc_cfg_tool_task_get var rtlmp_min_aspect_ratio] 0]
+    if { $rtlmp_min_aspect_ratio != "" } {
+        lappend rtlmp_args -min_ar $rtlmp_min_aspect_ratio
+    }
+    set rtlmp_fence [sc_cfg_tool_task_get var rtlmp_fence]
+    if { $rtlmp_fence != "" } {
+        lappend rtlmp_args -fence_lx [lindex $rtlmp_fence 0]
+        lappend rtlmp_args -fence_ly [lindex $rtlmp_fence 1]
+        lappend rtlmp_args -fence_ux [lindex $rtlmp_fence 2]
+        lappend rtlmp_args -fence_uy [lindex $rtlmp_fence 3]
+    }
+    set rtlmp_bus_planning [lindex [sc_cfg_tool_task_get var rtlmp_bus_planning] 0]
+    if { $rtlmp_bus_planning == "true" } {
+        lappend rtlmp_args -bus_planning
+    }
+    set rtlmp_target_dead_space [lindex [sc_cfg_tool_task_get var rtlmp_target_dead_space] 0]
+    if { $rtlmp_target_dead_space != "" } {
+        lappend rtlmp_args -target_dead_space $rtlmp_target_dead_space
+    }
 
-        macro_placement \
-            -halo [sc_cfg_tool_task_get var macro_place_halo] \
-            -channel [sc_cfg_tool_task_get var macro_place_channel]
+    set rtlmp_area_weight [lindex [sc_cfg_tool_task_get var rtlmp_area_weight] 0]
+    if { $rtlmp_area_weight != "" } {
+        lappend rtlmp_args -area_weight $rtlmp_area_weight
+    }
+    set rtlmp_outline_weight [lindex [sc_cfg_tool_task_get var rtlmp_outline_weight] 0]
+    if { $rtlmp_outline_weight != "" } {
+        lappend rtlmp_args -outline_weight $rtlmp_outline_weight
+    }
+    set rtlmp_wirelength_weight [lindex [sc_cfg_tool_task_get var rtlmp_wirelength_weight] 0]
+    if { $rtlmp_wirelength_weight != "" } {
+        lappend rtlmp_args -wirelength_weight $rtlmp_wirelength_weight
     }
+    set rtlmp_guidance_weight [lindex [sc_cfg_tool_task_get var rtlmp_guidance_weight] 0]
+    if { $rtlmp_guidance_weight != "" } {
+        lappend rtlmp_args -guidance_weight $rtlmp_guidance_weight
+    }
+    set rtlmp_fence_weight [lindex [sc_cfg_tool_task_get var rtlmp_fence_weight] 0]
+    if { $rtlmp_fence_weight != "" } {
+        lappend rtlmp_args -fence_weight $rtlmp_fence_weight
+    }
+    set rtlmp_notch_weight [lindex [sc_cfg_tool_task_get var rtlmp_notch_weight] 0]
+    if { $rtlmp_notch_weight != "" } {
+        lappend rtlmp_args -notch_weight $rtlmp_notch_weight
+    }
+    set rtlmp_blockage_weight [lindex [sc_cfg_tool_task_get var rtlmp_blockage_weight] 0]
+    if { $rtlmp_blockage_weight != "" } {
+        lappend rtlmp_args -blockage_weight $rtlmp_blockage_weight
+    }
+
+    rtl_macro_placer \
+        -report_directory reports/rtlmp \
+        -halo_width $halo_x \
+        -halo_height $halo_y \
+        -target_util [sc_global_placement_density] \
+        {*}$rtlmp_args
 }
 
 sc_print_macro_information

siliconcompiler/tools/openroad/scripts/apr/sc_power_grid.tcl

@@ -47,10 +47,20 @@ foreach net [sc_supply_nets] {
 
 foreach net [sc_psm_check_nets] {
     puts "Check supply net: $net"
+
+    set check_args []
+    if {
+        [sc_check_version 18610] &&
+        [sc_cfg_tool_task_check_in_list $net var psm_allow_missing_terminal_nets]
+    } {
+        lappend check_args -dont_require_terminals
+    }
+
     check_power_grid \
         -floorplanning \
         -error_file "reports/power_grid_${net}.rpt" \
-        -net $net
+        -net $net \
+        {*}$check_args
 }
 
 ###############################

siliconcompiler/tools/openroad/scripts/apr/sc_repair_design.tcl

@@ -28,6 +28,8 @@ estimate_parasitics -placement
 # Repair DRVs
 ###############################
 
+sc_set_dont_use -scanchain -multibit -report dont_use.repair_drv
+
 set repair_design_args []
 
 set rsz_cap_margin [lindex [sc_cfg_tool_task_get {var} rsz_cap_margin] 0]
@@ -43,6 +45,8 @@ repair_design \
     -verbose \
     {*}$repair_design_args
 
+sc_set_dont_use
+
 ###############################
 # Tie-off cell insertion
 ###############################

siliconcompiler/tools/openroad/scripts/apr/sc_repair_timing.tcl

@@ -34,6 +34,9 @@ if { [lindex [sc_cfg_tool_task_get var rsz_skip_setup_repair] 0] != "true" } {
     # Setup Repair
     ###############################
 
+    # Enable ffs for resizing
+    sc_set_dont_use -scanchain -multibit -report dont_use.repair_timing.setup
+
     estimate_parasitics -placement
 
     repair_timing \
@@ -45,6 +48,9 @@ if { [lindex [sc_cfg_tool_task_get var rsz_skip_setup_repair] 0] != "true" } {
         {*}$repair_timing_args
 
     sc_detailed_placement
+
+    # Restore dont use
+    sc_set_dont_use
 }
 
 if { [lindex [sc_cfg_tool_task_get var rsz_skip_hold_repair] 0] != "true" } {
@@ -55,7 +61,7 @@ if { [lindex [sc_cfg_tool_task_get var rsz_skip_hold_repair] 0] != "true" } {
     estimate_parasitics -placement
 
     # Enable hold cells
-    sc_set_dont_use -hold
+    sc_set_dont_use -hold -scanchain -multibit -report dont_use.repair_timing.hold
 
     repair_timing \
         -hold \

siliconcompiler/tools/openroad/scripts/common/procs.tcl

@@ -300,6 +300,23 @@ proc sc_bterm_has_placed_io { net } {
     return false
 }
 
+###########################
+# Get nets with unplaced bterms
+###########################
+
+proc sc_get_unplaced_io_nets { } {
+    set nets []
+    foreach bterm [[ord::get_db_block] getBTerms] {
+        if {
+            [$bterm getFirstPinPlacementStatus] == "UNPLACED" ||
+            [$bterm getFirstPinPlacementStatus] == "NONE"
+        } {
+            lappend nets [$bterm getNet]
+        }
+    }
+    return $nets
+}
+
 ###########################
 # Find nets regex
 ###########################
@@ -564,7 +581,7 @@ proc sc_setup_sta { } {
 
     # Check timing setup
     if { [sc_cfg_tool_task_check_in_list check_setup var reports] } {
-        check_setup
+        tee -file "reports/check_timing_setup.rpt" {check_setup -verbose}
     }
 
     if { [llength [all_clocks]] == 0 } {
@@ -701,13 +718,17 @@ proc sc_set_gui_title { } {
 
 proc sc_set_dont_use { args } {
     sta::parse_key_args "sc_set_dont_use" args \
-        keys {} \
-        flags {-hold -clock}
+        keys {-report} \
+        flags {-hold -clock -multibit -scanchain}
 
     sta::check_argc_eq0 "sc_set_dont_use" $args
 
     global sc_mainlib
 
+    if { [sc_check_version 18171] } {
+        reset_dont_use
+    }
+
     set_dont_use [sc_cfg_get library $sc_mainlib asic cells dontuse]
 
     set clk_groups "clkbuf clkgate clklogic"
@@ -724,4 +745,19 @@ proc sc_set_dont_use { args } {
             unset_dont_use [sc_cfg_get library $sc_mainlib asic cells $group]
         }
     }
+    if { [info exists flags(-clock)] } {
+        foreach group $clk_groups {
+            unset_dont_use [sc_cfg_get library $sc_mainlib asic cells $group]
+        }
+    }
+    if { [info exists flags(-multibit)] } {
+        unset_dont_use [sc_cfg_tool_task_get var multibit_ff_cells]
+    }
+    if { [info exists flags(-scanchain)] } {
+        unset_dont_use [sc_cfg_tool_task_get var scan_chain_cells]
+    }
+
+    if { [info exists keys(-report)] } {
+        tee -file reports/$keys(-report).rpt {report_dont_use}
+    }
 }

siliconcompiler/tools/openroad/scripts/common/reports.tcl

@@ -98,6 +98,10 @@ if { [sc_cfg_tool_task_check_in_list fmax var reports] } {
     }
 }
 
+if { [llength [all_clocks]] > 0 } {
+    tee -file "reports/timing/clocks.rpt" {report_clock_properties}
+}
+
 # get logic depth of design
 utl::metric_int "design__logic__depth" [sc_count_logic_depth]
 

siliconcompiler/tools/openroad/scripts/common/write_data.tcl

@@ -1,5 +1,2 @@
-write_db "outputs/${sc_design}.odb"
-write_sdc "outputs/${sc_design}.sdc"
-
-write_def "outputs/${sc_design}.def"
-write_verilog -include_pwr_gnd "outputs/${sc_design}.vg"
+source "$sc_refdir/common/write_data_physical.tcl"
+source "$sc_refdir/common/write_data_timing.tcl"

siliconcompiler/tools/openroad/scripts/common/write_data_physical.tcl

@@ -0,0 +1,3 @@
+write_db "outputs/${sc_design}.odb"
+write_def "outputs/${sc_design}.def"
+write_verilog -include_pwr_gnd "outputs/${sc_design}.vg"

siliconcompiler/tools/openroad/scripts/common/write_data_timing.tcl

@@ -0,0 +1 @@
+write_sdc "outputs/${sc_design}.sdc"

siliconcompiler/tools/openroad/scripts/common/write_images.tcl

@@ -93,6 +93,10 @@ proc sc_image_everything { } {
 }
 
 proc sc_image_irdrop { net corner } {
+    if { ![sc_cfg_tool_task_check_in_list power var reports] } {
+        return
+    }
+
     if { ![sc_has_placed_instances] || [sc_has_unplaced_instances] } {
         return
     }
@@ -107,7 +111,12 @@ proc sc_image_irdrop { net corner } {
     foreach msg $msgs {
         suppress_message PSM $msg
     }
-    set failed [catch { analyze_power_grid -net $net -corner $corner -source_type STRAPS } err]
+    set analyze_args []
+    lappend analyze_args -source_type STRAPS
+    if { [sc_check_version 18074] } {
+        lappend analyze_args -allow_reuse
+    }
+    set failed [catch { analyze_power_grid -net $net -corner $corner {*}$analyze_args } err]
     foreach msg $msgs {
         unsuppress_message PSM $msg
     }

siliconcompiler/tools/openroad/scripts/sc_rdlroute.tcl

@@ -180,5 +180,5 @@ utl::pop_metrics_stage
 ###############################
 
 utl::push_metrics_stage "sc__write__{}"
-source "$sc_refdir/common/write_data.tcl"
+source "$sc_refdir/common/write_data_physical.tcl"
 utl::pop_metrics_stage

siliconcompiler/tools/opensta/__init__.py

@@ -8,7 +8,7 @@ Sources: https://github.com/The-OpenROAD-Project/OpenSTA
 Installation: https://github.com/The-OpenROAD-Project/OpenSTA (also installed with OpenROAD)
 '''
 
-import os
+from siliconcompiler import utils
 from siliconcompiler.tools.openroad._apr import get_library_timing_keypaths
 from siliconcompiler.tools._common import get_tool_task
 from siliconcompiler.tools._common.asic import get_libraries
@@ -43,7 +43,7 @@ def setup(chip):
     chip.set('tool', tool, 'task', task, 'refdir', 'tools/opensta/scripts',
              step=step, index=index,
              package='siliconcompiler', clobber=False)
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=False)
 
     if delaymodel != 'nldm':

siliconcompiler/tools/opensta/report_libraries.py

@@ -1,4 +1,4 @@
-import os
+from siliconcompiler import utils
 from siliconcompiler.tools.opensta import setup as tool_setup
 from siliconcompiler.tools.opensta import runtime_options as tool_runtime_options
 from siliconcompiler.tools._common import get_tool_task
@@ -17,7 +17,7 @@ def setup(chip):
     chip.set('tool', tool, 'task', task, 'script', 'sc_report_libraries.tcl',
              step=step, index=index, clobber=False)
 
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index)
 
 

siliconcompiler/tools/opensta/timing.py

@@ -1,5 +1,6 @@
 import os
 import re
+from siliconcompiler import utils
 from siliconcompiler import sc_open, SiliconCompilerError
 from siliconcompiler.tools.opensta import setup as tool_setup
 from siliconcompiler.tools.opensta import runtime_options as tool_runtime_options
@@ -22,7 +23,7 @@ def setup(chip):
     chip.set('tool', tool, 'task', task, 'script', 'sc_timing.tcl',
              step=step, index=index, clobber=False)
 
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index)
 
     design = chip.top()