siliconcompiler 0.29.1__py3-none-any.whl → 0.29.3__py3-none-any.whl

siliconcompiler/_metadata.py

@@ -1,5 +1,5 @@
 # Version number following semver standard.
-version = '0.29.1'
+version = '0.29.3'
 
 # Default server address for remote runs, if unspecified.
 default_server = 'https://server.siliconcompiler.com'

siliconcompiler/apps/sc_install.py

@@ -126,7 +126,7 @@ def _recommended_tool_groups(tools):
     groups = {
         "asic": {"surelog", "sv2v", "yosys", "openroad", "klayout"},
         "fpga": {"surelog", "sv2v", "yosys", "vpr"},
-        "digital-simulation": {"verilator", "icarus"},
+        "digital-simulation": {"verilator", "icarus", "gtkwave"},
         "analog-simulation": {"xyce"}
     }
 
@@ -168,7 +168,7 @@ To system debugging information (this should only be used to debug):
     parser = argparse.ArgumentParser(
         prog=progname,
         description=description,
-        formatter_class=argparse.RawDescriptionHelpFormatter)
+        formatter_class=argparse.ArgumentDefaultsHelpFormatter)
 
     tools = _get_tools_list()
 

siliconcompiler/core.py

@@ -21,6 +21,7 @@ from siliconcompiler.remote import client
 from siliconcompiler.schema import Schema, SCHEMA_VERSION
 from siliconcompiler.schema import utils as schema_utils
 from siliconcompiler import utils
+from siliconcompiler.utils.logging import LoggerFormatter, ColorStreamFormatter
 from siliconcompiler import _metadata
 from siliconcompiler import NodeStatus, SiliconCompilerError
 from siliconcompiler.report import _show_summary_table
@@ -225,7 +226,8 @@ class Chip:
         else:
             in_run = False
 
-        log_format = ['%(levelname)-7s']
+        level_format = '%(levelname)-7s'
+        log_format = [level_format]
         if loglevel == 'debug':
             log_format.append('%(funcName)-10s')
             log_format.append('%(lineno)-4s')
@@ -261,14 +263,17 @@ class Chip:
             log_formatprefix = ""
 
         log_format.append('%(message)s')
-        logformat = log_formatprefix + ' | '.join(log_format)
+        stream_logformat = log_formatprefix + ' | '.join(log_format[1:])
 
         if not self.logger.hasHandlers():
             stream_handler = logging.StreamHandler(stream=sys.stdout)
             self.logger.addHandler(stream_handler)
 
         for handler in self.logger.handlers:
-            formatter = logging.Formatter(logformat)
+            if ColorStreamFormatter.supports_color(handler):
+                formatter = ColorStreamFormatter(log_formatprefix, level_format, stream_logformat)
+            else:
+                formatter = LoggerFormatter(log_formatprefix, level_format, stream_logformat)
             handler.setFormatter(formatter)
 
         self.logger.setLevel(schema_utils.translate_loglevel(loglevel))
@@ -500,6 +505,9 @@ class Chip:
                     'dependency-caching-rebase')
         """
 
+        if os.path.isfile(path):
+            path = os.path.dirname(os.path.abspath(path))
+
         preset_path = self.get('package', 'source', name, 'path')
         preset_ref = self.get('package', 'source', name, 'ref')
         if preset_path and preset_path != path or preset_ref and preset_ref != ref:
@@ -3200,6 +3208,7 @@ class Chip:
         sc_step = self.get('arg', 'step')
         sc_index = self.get('arg', 'index')
         sc_job = self.get('option', 'jobname')
+        flow = self.get('option', 'flow')
 
         has_filename = filename is not None
         # Finding last layout if no argument specified
@@ -3210,14 +3219,15 @@ class Chip:
             if sc_step and sc_index:
                 search_nodes.append((sc_step, sc_index))
             elif sc_step:
-                for check_step, check_index in nodes_to_execute(self, self.get('option', 'flow')):
+                for check_step, check_index in nodes_to_execute(self, flow):
                     if sc_step == check_step:
                         search_nodes.append((check_step, check_index))
             else:
-                for nodes in _get_flowgraph_execution_order(self,
-                                                            self.get('option', 'flow'),
-                                                            reverse=True):
-                    search_nodes.extend(nodes)
+                if flow is not None:
+                    for nodes in _get_flowgraph_execution_order(self,
+                                                                flow,
+                                                                reverse=True):
+                        search_nodes.extend(nodes)
 
             for ext in self._showtools.keys():
                 if extension and extension != ext:

siliconcompiler/flowgraph.py

@@ -205,18 +205,36 @@ def _get_flowgraph_execution_order(chip, flow, reverse=False):
             else:
                 ex_map.setdefault((istep, iindex), set()).add((step, index))
 
+    rev_ex_map = {}
+    for node, edges in ex_map.items():
+        for step, index in edges:
+            rev_ex_map.setdefault((step, index), set()).add(node)
+
     # Collect execution order of nodes
     if reverse:
         order = [set(_get_flowgraph_exit_nodes(chip, flow))]
     else:
         order = [set(_get_flowgraph_entry_nodes(chip, flow))]
 
+    visited = set()
     while True:
         next_level = set()
-        for step, index in order[-1]:
-            if (step, index) in ex_map and \
-               not any([(step, index) in v for v in ex_map.values()]):
-                next_level.update(ex_map.pop((step, index)))
+        next_visited = set()
+        for step, index in sorted(order[-1]):
+            if (step, index) not in rev_ex_map:
+                # No edges so assume inputs are okay
+                inputs_valid = True
+            else:
+                inputs_valid = all([node in visited for node in rev_ex_map[(step, index)]])
+
+            if inputs_valid:
+                next_visited.add((step, index))
+                if (step, index) in ex_map:
+                    next_level.update(ex_map.pop((step, index)))
+            else:
+                next_level.add((step, index))
+
+        visited.update(next_visited)
 
         if not next_level:
             break
@@ -233,7 +251,7 @@ def _get_flowgraph_execution_order(chip, flow, reverse=False):
 
     exec_order.reverse()
 
-    return exec_order
+    return [sorted(level) for level in exec_order]
 
 
 def get_executed_nodes(chip, flow):

siliconcompiler/scheduler/__init__.py

@@ -55,6 +55,10 @@ def _get_callback(hook):
     return None
 
 
+# Max lines to print from failed node log
+_failed_log_lines = 20
+
+
 ###############################################################################
 class SiliconCompilerTimeout(Exception):
     ''' Minimal Exception wrapper used to raise sc timeout errors.
@@ -833,6 +837,8 @@ def _run_executable_or_builtin(chip, step, index, version, toolpath, workdir, ru
     is_stderr_log = chip.get('tool', tool, 'task', task, 'stderr', 'destination',
                              step=step, index=index) == 'log' and stderr_file != stdout_file
 
+    chip.logger.info(f'Running in {workdir}')
+
     retcode = 0
     cmdlist = []
     cmd_args = []
@@ -877,7 +883,6 @@ def _run_executable_or_builtin(chip, step, index, version, toolpath, workdir, ru
         # Make record of tool options
         __record_tool(chip, step, index, version, toolpath, cmd_args)
 
-        chip.logger.info('Running in %s', workdir)
         chip.logger.info('%s', printable_cmd)
         timeout = chip.get('option', 'timeout', step=step, index=index)
         logfile = step + '.log'
@@ -988,10 +993,10 @@ def _run_executable_or_builtin(chip, step, index, version, toolpath, workdir, ru
         msg = f'Command failed with code {retcode}.'
         if logfile:
             if quiet:
-                # Print last 10 lines of log when in quiet mode
+                # Print last N lines of log when in quiet mode
                 with sc_open(logfile) as logfd:
                     loglines = logfd.read().splitlines()
-                    for logline in loglines[-10:]:
+                    for logline in loglines[-_failed_log_lines:]:
                         chip.logger.error(logline)
                 # No log file for pure-Python tools.
             msg += f' See log file {os.path.abspath(logfile)}'
@@ -1239,6 +1244,13 @@ def _finalizenode(chip, step, index, replay):
 
     if not is_skipped:
         _check_logfile(chip, step, index, quiet, run_func)
+
+    # Report metrics
+    for metric in ['errors', 'warnings']:
+        val = chip.get('metric', metric, step=step, index=index)
+        if val is not None:
+            chip.logger.info(f'Number of {metric}: {val}')
+
     _hash_files(chip, step, index)
 
     # Capture wall runtime and cpu cores
@@ -1535,12 +1547,13 @@ def _check_node_dependencies(chip, node, deps, deps_was_successful):
 def _launch_nodes(chip, nodes_to_run, processes, local_processes):
     running_nodes = {}
     max_parallel_run = chip.get('option', 'scheduler', 'maxnodes')
-    max_threads = os.cpu_count()
+    max_cores = utils.get_cores(chip)
+    max_threads = utils.get_cores(chip)
     if not max_parallel_run:
-        max_parallel_run = max_threads
+        max_parallel_run = utils.get_cores(chip)
 
-    # clip max parallel jobs to 1 <= jobs <= max_threads
-    max_parallel_run = max(1, min(max_parallel_run, max_threads))
+    # clip max parallel jobs to 1 <= jobs <= max_cores
+    max_parallel_run = max(1, min(max_parallel_run, max_cores))
 
     def allow_start(node):
         if node not in local_processes:
@@ -1561,7 +1574,7 @@ def _launch_nodes(chip, nodes_to_run, processes, local_processes):
         # clamp to max_parallel to avoid getting locked up
         requested_threads = max(1, min(requested_threads, max_threads))
 
-        if requested_threads + sum(running_nodes.values()) > max_threads:
+        if requested_threads + sum(running_nodes.values()) > max_cores:
             # delay until there are enough core available
             return False, 0
 
@@ -2062,7 +2075,6 @@ def check_logfile(chip, jobname=None, step=None, index='0',
                             chip.logger.info(f'{suffix}: {line_with_num}')
 
     for suffix in ordered_suffixes:
-        chip.logger.info(f'Number of {suffix}: {matches[suffix]}')
         checks[suffix]['report'].close()
 
     return matches

siliconcompiler/tools/__init__.py

@@ -5,6 +5,7 @@ from siliconcompiler.tools.chisel import chisel
 from siliconcompiler.tools.execute import execute
 from siliconcompiler.tools.genfasm import genfasm
 from siliconcompiler.tools.ghdl import ghdl
+from siliconcompiler.tools import gtkwave
 from siliconcompiler.tools.icarus import icarus
 from siliconcompiler.tools.icepack import icepack
 from siliconcompiler.tools.klayout import klayout
@@ -38,6 +39,7 @@ def get_tools():
             execute,
             genfasm,
             ghdl,
+            gtkwave,
             icarus,
             icepack,
             klayout,

siliconcompiler/tools/_common/asic.py

@@ -135,6 +135,76 @@ def set_tool_task_var(chip,
     return value
 
 
+def set_tool_task_lib_var(chip,
+                          param_key,
+                          default_value=None,
+                          schelp=None,
+                          option_key=None,
+                          lib_key=None):
+    '''
+    Set parameter from libraries -> option -> default_value
+    '''
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    if schelp:
+        chip.set('tool', tool, 'task', task, 'var', param_key,
+                 schelp, field='help')
+
+    if not option_key:
+        option_key = f'{tool}_{param_key}'
+    require_key, value = pick_key(chip, [('option', 'var', option_key)], step=step, index=index)
+
+    def check_value(val):
+        if isinstance(val, (list, tuple, set)):
+            return len(val) > 0
+        return val is not None
+
+    if check_value(value):
+        chip.set('tool', tool, 'task', task, 'var', param_key, value,
+                 step=step, index=index, clobber=False)
+
+        if require_key:
+            chip.add('tool', tool, 'task', task, 'require',
+                     ','.join(('option', option_key)),
+                     step=step, index=index)
+
+        return value
+
+    # Add library key
+    if not lib_key:
+        lib_key = f'{tool}_{param_key}'
+    lib_keys = []
+    for lib in get_libraries(chip, 'logic'):
+        if chip.valid('library', lib, 'option', 'var', lib_key) and \
+           chip.get('library', lib, 'option', 'var', lib_key):
+            lib_keys.append(('library', lib, 'option', 'var', lib_key))
+
+    values = set()
+    for lib_key in lib_keys:
+        chip.add('tool', tool, 'task', task, 'require', ','.join(lib_key), step=step, index=index)
+
+        get_step = step
+        get_index = index
+
+        if chip.get(*lib_key, field='pernode') == 'never':
+            get_step = None
+            get_index = None
+
+        values.update(chip.get(*lib_key, step=get_step, index=get_index))
+
+    if check_value(values):
+        chip.set('tool', tool, 'task', task, 'var', param_key, values,
+                 step=step, index=index, clobber=False)
+
+        chip.add('tool', tool, 'task', task, 'require',
+                 ','.join(['tool', tool, 'task', task, 'var', param_key]),
+                 step=step, index=index)
+
+    return values
+
+
 def get_tool_task_var(chip,
                       param_key,
                       option_key=None,

siliconcompiler/tools/_common/tcl/sc_pin_constraints.tcl

@@ -49,8 +49,8 @@ proc sc_collect_pin_constraints {
         }
 
         set side_pin_order []
-        dict for {index pin} $pins {
-            lappend side_pin_order {*}$pin
+        foreach index [lsort -integer [dict keys $pins]] {
+            lappend side_pin_order {*}[dict get $pins $index]
         }
 
         set pin_layer_ordering [dict create]

siliconcompiler/tools/bambu/convert.py

@@ -1,5 +1,6 @@
 import os
 import shutil
+from siliconcompiler import utils
 from siliconcompiler.tools._common import \
     add_frontend_requires, add_require_input, get_frontend_options, get_input_files, \
     get_tool_task, has_input_files
@@ -27,7 +28,7 @@ def setup(chip):
     chip.set('tool', tool, 'task', task, 'refdir', refdir,
              step=step, index=index,
              package='siliconcompiler', clobber=False)
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=False)
 
     # Input/Output requirements

siliconcompiler/tools/bluespec/convert.py

@@ -3,6 +3,7 @@ import shutil
 from siliconcompiler.tools._common import \
     add_require_input, add_frontend_requires, get_frontend_options, get_input_files, \
     get_tool_task, has_input_files
+from siliconcompiler import utils
 from siliconcompiler import sc_open
 
 # Directory inside step/index dir to store bsc intermediate results.
@@ -33,7 +34,7 @@ def setup(chip):
     chip.set('tool', tool, 'task', task, 'refdir', refdir,
              step=step, index=index,
              package='siliconcompiler', clobber=False)
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=False)
 
     # Input/Output requirements

siliconcompiler/tools/chisel/convert.py

@@ -3,6 +3,7 @@ import shutil
 import glob
 from siliconcompiler.tools._common import add_frontend_requires, get_tool_task, has_input_files
 from siliconcompiler import sc_open, SiliconCompilerError
+from siliconcompiler import utils
 
 
 def setup(chip):
@@ -28,7 +29,7 @@ def setup(chip):
     chip.set('tool', tool, 'task', task, 'refdir', refdir,
              step=step, index=index,
              package='siliconcompiler', clobber=False)
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=False)
 
     chip.set('tool', tool, 'task', task, 'option', ['-batch',

siliconcompiler/tools/genfasm/bitstream.py

@@ -1,5 +1,5 @@
-import os
 import shutil
+from siliconcompiler import utils
 from siliconcompiler.tools.genfasm import genfasm
 from siliconcompiler.tools.vpr import vpr
 from siliconcompiler.tools._common import get_tool_task
@@ -15,7 +15,7 @@ def setup(chip):
     index = chip.get('arg', 'index')
     tool, task = get_tool_task(chip, step, index)
 
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=False)
 
     chip.set('tool', tool, 'task', task, 'regex', 'warnings', "^Warning",

siliconcompiler/tools/ghdl/convert.py

@@ -1,6 +1,6 @@
-import os
 from siliconcompiler.tools._common import add_require_input, add_frontend_requires, \
     get_input_files, get_tool_task, has_input_files
+from siliconcompiler import utils
 
 
 def setup(chip):
@@ -23,7 +23,7 @@ def setup(chip):
     chip.set('tool', tool, 'vswitch', '--version')
     chip.set('tool', tool, 'version', '>=4.0.0-dev', clobber=clobber)
 
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=clobber)
     chip.set('tool', tool, 'task', task, 'option', '',
              step=step, index=index, clobber=clobber)

siliconcompiler/tools/gtkwave/__init__.py

@@ -0,0 +1,39 @@
+'''
+GTKWave is a fully featured GTK+ based wave viewer for Unix, Win32, and
+Mac OSX which reads LXT, LXT2, VZT, FST, and GHW files as well as standard
+Verilog VCD/EVCD files and allows their viewing.
+
+Documentation: https://gtkwave.github.io/gtkwave/
+
+Sources: https://github.com/gtkwave/gtkwave
+
+Installation: https://github.com/gtkwave/gtkwave
+'''
+
+from siliconcompiler.tools._common import \
+    get_tool_task
+
+
+def setup(chip):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    chip.set('tool', tool, 'exe', 'gtkwave')
+    chip.set('tool', tool, 'vswitch', '--version')
+    chip.set('tool', tool, 'version', '>=v3.3.116', clobber=False)
+    chip.set('tool', tool, 'format', 'tcl', clobber=False)
+
+
+################################
+# Version Check
+################################
+def parse_version(stdout):
+    # First line: GTKWave Analyzer v3.3.116 (w)1999-2023 BSI
+    return stdout.split()[2]
+
+
+def normalize_version(version):
+    if version[0] == 'v':
+        return version[1:]
+    return version

siliconcompiler/tools/gtkwave/scripts/sc_show.tcl

@@ -0,0 +1,34 @@
+###############################
+# Reading SC Schema
+###############################
+
+source ./sc_manifest.tcl
+
+##############################
+# Schema Adapter
+###############################
+
+set sc_step [sc_cfg_get arg step]
+set sc_index [sc_cfg_get arg index]
+set sc_flow [sc_cfg_get option flow]
+set sc_tool [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index tool]
+set sc_task [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
+
+###############################
+# Source pre-scripts
+###############################
+
+if { [sc_cfg_tool_task_exists prescript] } {
+    foreach sc_pre_script [sc_cfg_tool_task_get prescript] {
+        puts "Sourcing pre script: ${sc_pre_script}"
+        source $sc_pre_script
+    }
+}
+
+###############################
+# Handle exit
+###############################
+
+if { [lindex [sc_cfg_tool_task_get {var} show_exit] 0] == "true" } {
+    exit
+}

siliconcompiler/tools/gtkwave/show.py

@@ -0,0 +1,71 @@
+import os
+
+from siliconcompiler.tools.gtkwave import setup as tool_setup
+from siliconcompiler.tools._common import \
+    add_require_input, get_tool_task, input_provides
+from siliconcompiler import utils
+
+
+def setup(chip):
+    '''
+    Show a VCD file.
+    '''
+
+    tool_setup(chip)
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
+             step=step, index=index)
+
+    chip.set('tool', tool, 'task', task, 'refdir',
+             'tools/gtkwave/scripts',
+             step=step, index=index, package='siliconcompiler')
+
+    chip.set('tool', tool, 'task', task, 'refdir',
+             'tools/gtkwave/scripts',
+             step=step, index=index, package='siliconcompiler')
+    chip.set('tool', tool, 'task', task, 'script', 'sc_show.tcl',
+             step=step, index=index)
+
+    if f'{chip.top()}.vcd' in input_provides(chip, step, index):
+        chip.set('tool', tool, 'task', task, 'input', f'{chip.top()}.vcd', step=step, index=index)
+    elif chip.valid('tool', tool, 'task', task, 'var', 'show_filepath') and \
+            chip.get('tool', tool, 'task', task, 'var', 'show_filepath', step=step, index=index):
+        chip.add('tool', tool, 'task', task, 'require',
+                 ",".join(['tool', tool, 'task', task, 'var', 'show_filepath']),
+                 step=step, index=index)
+    else:
+        add_require_input(chip, 'input', 'waveform', 'vcd')
+
+    chip.set('tool', tool, 'task', task, 'var', 'show_exit', False,
+             step=step, index=index, clobber=False)
+
+
+def runtime_options(chip):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    options = []
+
+    threads = chip.get('tool', tool, 'task', task, 'threads', step=step, index=index)
+    if threads:
+        options.append(f'--cpu={threads}')
+
+    script = chip.find_files('tool', tool, 'task', task, 'script', step=step, index=index)[0]
+    options.append(f'--script={script}')
+
+    if os.path.exists(f'inputs/{chip.top()}.vcd'):
+        dump = f'inputs/{chip.top()}.vcd'
+    elif chip.valid('tool', tool, 'task', task, 'var', 'show_filepath') and \
+            chip.get('tool', tool, 'task', task, 'var', 'show_filepath', step=step, index=index):
+        dump = chip.get('tool', tool, 'task', task, 'var', 'show_filepath',
+                        step=step, index=index)[0]
+    else:
+        dump = chip.find_files('input', 'waveform', 'vcd', step=step, index=index)[0]
+    options.append(f'--dump={dump}')
+
+    return options

siliconcompiler/tools/icarus/compile.py

@@ -1,7 +1,7 @@
-import os
 from siliconcompiler.tools._common import \
     add_require_input, add_frontend_requires, get_input_files, get_frontend_options, \
     get_tool_task
+from siliconcompiler import utils
 
 
 def setup(chip):
@@ -20,7 +20,7 @@ def setup(chip):
     chip.set('tool', tool, 'vswitch', '-V')
     chip.set('tool', tool, 'version', '>=10.3', clobber=False)
 
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=False)
 
     chip.set('tool', tool, 'task', task, 'var', 'verilog_generation',
@@ -75,6 +75,10 @@ def runtime_options(chip):
         cmdlist.append('-I' + value)
     for value in opts['define']:
         cmdlist.append('-D' + value)
+
+    # add siliconcompiler specific defines
+    cmdlist.append(f"-DSILICONCOMPILER_TRACE_FILE=\\\"reports/{design}.vcd\\\"")
+
     for value in get_input_files(chip, 'input', 'cmdfile', 'f'):
         cmdlist.append('-f ' + value)
     for value in get_input_files(chip, 'input', 'rtl', 'netlist'):

siliconcompiler/tools/klayout/drc.py

@@ -7,6 +7,7 @@ from siliconcompiler.tools._common.asic import set_tool_task_var, get_tool_task_
 
 from siliconcompiler.tools.klayout.klayout import setup as setup_tool
 import xml.etree.ElementTree as ET
+from siliconcompiler import utils
 
 
 def make_docs(chip):
@@ -35,7 +36,7 @@ def setup(chip):
     chip.set('tool', tool, 'task', task, 'option', option,
              step=step, index=index, clobber=clobber)
 
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=clobber)
 
     chip.add('tool', tool, 'task', task, 'require', 'option,pdk')

siliconcompiler/tools/magic/magic.py

@@ -47,7 +47,7 @@ def setup(chip):
     chip.set('tool', tool, 'version', '>=8.3.196', clobber=False)
     chip.set('tool', tool, 'format', 'tcl')
 
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=False)
     chip.set('tool', tool, 'task', task, 'refdir', refdir,
              step=step, index=index,

siliconcompiler/tools/netgen/lvs.py

@@ -1,5 +1,6 @@
 import os
 
+from siliconcompiler import utils
 from siliconcompiler.tools.netgen import count_lvs
 from siliconcompiler import sc_open
 from siliconcompiler.tools._common import get_tool_task, record_metric
@@ -24,7 +25,7 @@ def setup(chip):
     chip.set('tool', tool, 'version', '>=1.5.192', clobber=False)
     chip.set('tool', tool, 'format', 'tcl')
 
-    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+    chip.set('tool', tool, 'task', task, 'threads', utils.get_cores(chip),
              step=step, index=index, clobber=False)
     chip.set('tool', tool, 'task', task, 'refdir', refdir,
              step=step, index=index,