siliconcompiler 0.29.0__py3-none-any.whl → 0.29.2__py3-none-any.whl

siliconcompiler/tools/openroad/scripts/common/procs.tcl

@@ -300,6 +300,23 @@ proc sc_bterm_has_placed_io { net } {
     return false
 }
 
+###########################
+# Get nets with unplaced bterms
+###########################
+
+proc sc_get_unplaced_io_nets { } {
+    set nets []
+    foreach bterm [[ord::get_db_block] getBTerms] {
+        if {
+            [$bterm getFirstPinPlacementStatus] == "UNPLACED" ||
+            [$bterm getFirstPinPlacementStatus] == "NONE"
+        } {
+            lappend nets [$bterm getNet]
+        }
+    }
+    return $nets
+}
+
 ###########################
 # Find nets regex
 ###########################
@@ -673,3 +690,74 @@ proc sc_check_version { min_required } {
 
     return [expr { [lindex $version 1] >= $min_required }]
 }
+
+proc sc_set_gui_title { } {
+    if { ![sc_check_version 17650] } {
+        return
+    }
+
+    global sc_tool
+    global sc_task
+
+    set step [sc_cfg_get arg step]
+    set index [sc_cfg_get arg index]
+    set job [sc_cfg_get option jobname]
+    if { [sc_cfg_exists "tool" $sc_tool "task" $sc_task "var" "show_step"] } {
+        set step [sc_cfg_get "tool" $sc_tool "task" $sc_task "var" "show_step"]
+    }
+    if { [sc_cfg_exists "tool" $sc_tool "task" $sc_task "var" "show_index"] } {
+        set index [sc_cfg_get "tool" $sc_tool "task" $sc_task "var" "show_index"]
+    }
+    if { [sc_cfg_exists "tool" $sc_tool "task" $sc_task "var" "show_job"] } {
+        set job [sc_cfg_get "tool" $sc_tool "task" $sc_task "var" "show_job"]
+    }
+
+    set title "OpenROAD - ${job} / ${step}${index}"
+    gui::set_title $title
+}
+
+proc sc_set_dont_use { args } {
+    sta::parse_key_args "sc_set_dont_use" args \
+        keys {-report} \
+        flags {-hold -clock -multibit -scanchain}
+
+    sta::check_argc_eq0 "sc_set_dont_use" $args
+
+    global sc_mainlib
+
+    if { [sc_check_version 18171] } {
+        reset_dont_use
+    }
+
+    set_dont_use [sc_cfg_get library $sc_mainlib asic cells dontuse]
+
+    set clk_groups "clkbuf clkgate clklogic"
+    foreach group $clk_groups {
+        set_dont_use [sc_cfg_get library $sc_mainlib asic cells $group]
+    }
+    set_dont_use [sc_cfg_get library $sc_mainlib asic cells hold]
+
+    if { [info exists flags(-hold)] } {
+        unset_dont_use [sc_cfg_get library $sc_mainlib asic cells hold]
+    }
+    if { [info exists flags(-clock)] } {
+        foreach group $clk_groups {
+            unset_dont_use [sc_cfg_get library $sc_mainlib asic cells $group]
+        }
+    }
+    if { [info exists flags(-clock)] } {
+        foreach group $clk_groups {
+            unset_dont_use [sc_cfg_get library $sc_mainlib asic cells $group]
+        }
+    }
+    if { [info exists flags(-multibit)] } {
+        unset_dont_use [sc_cfg_tool_task_get var multibit_ff_cells]
+    }
+    if { [info exists flags(-scanchain)] } {
+        unset_dont_use [sc_cfg_tool_task_get var scan_chain_cells]
+    }
+
+    if { [info exists keys(-report)] } {
+        tee -file reports/$keys(-report).rpt {report_dont_use}
+    }
+}

siliconcompiler/tools/openroad/scripts/common/reports.tcl

@@ -7,7 +7,7 @@ file mkdir reports/timing
 file mkdir reports/power
 file mkdir reports/markers
 
-set fields "{capacitance slew input_pins nets fanout}"
+set fields "{capacitance slew input_pins hierarcial_pins net fanout}"
 set sta_top_n_paths [lindex [sc_cfg_tool_task_get var sta_top_n_paths] 0]
 set PREFIX "SC_METRIC:"
 

siliconcompiler/tools/openroad/scripts/common/write_images.tcl

@@ -93,6 +93,10 @@ proc sc_image_everything { } {
 }
 
 proc sc_image_irdrop { net corner } {
+    if { ![sc_cfg_tool_task_check_in_list power var reports] } {
+        return
+    }
+
     if { ![sc_has_placed_instances] || [sc_has_unplaced_instances] } {
         return
     }
@@ -107,7 +111,12 @@ proc sc_image_irdrop { net corner } {
     foreach msg $msgs {
         suppress_message PSM $msg
     }
-    set failed [catch { analyze_power_grid -net $net -corner $corner -source_type STRAPS } err]
+    set analyze_args []
+    lappend analyze_args -source_type STRAPS
+    if { [sc_check_version 18074] } {
+        lappend analyze_args -allow_reuse
+    }
+    set failed [catch { analyze_power_grid -net $net -corner $corner {*}$analyze_args } err]
     foreach msg $msgs {
         unsuppress_message PSM $msg
     }

siliconcompiler/tools/openroad/scripts/sc_show.tcl

@@ -28,6 +28,11 @@ source -echo "$sc_refdir/common/debugging.tcl"
 
 source "$sc_refdir/common/procs.tcl"
 
+###############################
+# Setup GUI title early
+###############################
+sc_set_gui_title
+
 ###############################
 # Design information
 ###############################

siliconcompiler/tools/opensta/__init__.py

@@ -12,13 +12,13 @@ import os
 from siliconcompiler.tools.openroad._apr import get_library_timing_keypaths
 from siliconcompiler.tools._common import get_tool_task
 from siliconcompiler.tools._common.asic import get_libraries
-from siliconcompiler.targets import asap7_demo
 
 
 ####################################################################
 # Make Docs
 ####################################################################
 def make_docs(chip):
+    from siliconcompiler.targets import asap7_demo
     chip.use(asap7_demo)
 
 

siliconcompiler/tools/opensta/check_library.py

@@ -0,0 +1,27 @@
+from siliconcompiler.tools.opensta import setup as tool_setup
+from siliconcompiler.tools.opensta import runtime_options as tool_runtime_options
+from siliconcompiler.tools._common import get_tool_task
+
+
+def setup(chip):
+    '''
+    Check setup information about the timing libraries.
+    '''
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    tool_setup(chip)
+
+    chip.set('tool', tool, 'task', task, 'script', 'sc_check_library.tcl',
+             step=step, index=index, clobber=False)
+
+    chip.set('tool', tool, 'task', task, 'threads', 1,
+             step=step, index=index)
+
+
+################################
+# Runtime options
+################################
+def runtime_options(chip):
+    return tool_runtime_options(chip)

siliconcompiler/tools/opensta/scripts/sc_check_library.tcl

@@ -0,0 +1,255 @@
+###############################
+# Reading SC Schema
+###############################
+
+source ./sc_manifest.tcl > /dev/null
+
+##############################
+# Schema Adapter
+###############################
+
+set sc_tool opensta
+set sc_step [sc_cfg_get arg step]
+set sc_index [sc_cfg_get arg index]
+set sc_flow [sc_cfg_get option flow]
+set sc_task [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
+
+set sc_refdir [sc_cfg_tool_task_get refdir]
+
+# Design
+set sc_design [sc_top]
+
+# APR Parameters
+set sc_targetlibs [sc_get_asic_libraries logic]
+set sc_delaymodel [sc_cfg_get asic delaymodel]
+set sc_scenarios [dict keys [sc_cfg_get constraint timing]]
+
+###############################
+# Optional
+###############################
+
+# MACROS
+set sc_macrolibs [sc_get_asic_libraries macro]
+
+###############################
+# Read Files
+###############################
+
+# Read Liberty
+puts "Defining timing corners: $sc_scenarios"
+define_corners {*}$sc_scenarios
+foreach lib "$sc_targetlibs $sc_macrolibs" {
+    #Liberty
+    foreach corner $sc_scenarios {
+        foreach libcorner [sc_cfg_get constraint timing $corner libcorner] {
+            if { [sc_cfg_exists library $lib output $libcorner $sc_delaymodel] } {
+                foreach lib_file [sc_cfg_get library $lib output $libcorner $sc_delaymodel] {
+                    puts "Reading liberty file for ${corner} ($libcorner): ${lib_file}"
+                    read_liberty -corner $corner $lib_file
+                }
+                break
+            }
+        }
+    }
+}
+
+proc assert_glob { str } {
+    if { [string first "*" $str] != -1 } {
+        puts "\[ERROR] Regex detected: $str"
+    }
+}
+
+# Check cells
+# check for globbing and report list if globs are detected
+# check each cell
+foreach lib $sc_targetlibs {
+    dict for {cell_type cells} [sc_cfg_get library $lib asic cells] {
+        if { [llength $cells] == 0 } {
+            continue
+        }
+
+        puts "Checking: $lib / asic / cells / $cell_type"
+
+        foreach cell $cells {
+            puts "  $cell:"
+
+            if { $cell_type != "dontuse" } {
+                assert_glob $cell
+            }
+            set libcells [get_lib_cells $cell]
+            foreach libcell $libcells {
+                puts "    [get_full_name $libcell]"
+            }
+        }
+    }
+}
+
+# Check yosys setup
+# yosys_driver_cell
+foreach lib $sc_targetlibs {
+    puts "Checking $lib yosys_driver_cell"
+    assert_glob [sc_cfg_get library $lib option var yosys_driver_cell]
+    if { [get_lib_cells [sc_cfg_get library $lib option var yosys_driver_cell]] == 0 } {
+        puts "\[ERROR] missing"
+    }
+}
+# yosys_buffer_cell
+foreach lib $sc_targetlibs {
+    puts "Checking $lib yosys_buffer_cell"
+    assert_glob [sc_cfg_get library $lib option var yosys_buffer_cell]
+    if { [get_lib_cells [sc_cfg_get library $lib option var yosys_buffer_cell]] == 0 } {
+        puts "\[ERROR] missing"
+    }
+}
+# yosys_buffer_input
+foreach lib $sc_targetlibs {
+    puts "Checking $lib yosys_buffer_input"
+    assert_glob [sc_cfg_get library $lib option var yosys_buffer_input]
+    set cellname [sc_cfg_get library $lib option var yosys_buffer_cell]
+    set pins [get_lib_pins $cellname/[sc_cfg_get library $lib option var yosys_buffer_input]]
+    if { [llength $pins] != [llength [sta::corners]] } {
+        puts "\[ERROR] mismatch"
+    }
+    foreach pin $pins {
+        if { [get_property $pin direction] != "input" } {
+            puts "\[ERROR] [get_full_name $pin] incorrect direction"
+        }
+    }
+}
+# yosys_buffer_output
+foreach lib $sc_targetlibs {
+    puts "Checking $lib yosys_buffer_output"
+    assert_glob [sc_cfg_get library $lib option var yosys_buffer_output]
+    set cellname [sc_cfg_get library $lib option var yosys_buffer_cell]
+    set pins [get_lib_pins $cellname/[sc_cfg_get library $lib option var yosys_buffer_output]]
+    if { [llength $pins] != [llength [sta::corners]] } {
+        puts "\[ERROR] mismatch"
+    }
+    foreach pin $pins {
+        if { [get_property $pin direction] != "output" } {
+            puts "\[ERROR] [get_full_name $pin] incorrect direction"
+        }
+    }
+}
+# yosys_tiehigh_cell
+foreach lib $sc_targetlibs {
+    puts "Checking $lib yosys_tiehigh_cell"
+    assert_glob [sc_cfg_get library $lib option var yosys_tiehigh_cell]
+    if { [get_lib_cells [sc_cfg_get library $lib option var yosys_tiehigh_cell]] == 0 } {
+        puts "\[ERROR] missing"
+    }
+}
+# yosys_tiehigh_port
+foreach lib $sc_targetlibs {
+    puts "Checking $lib yosys_tiehigh_port"
+    assert_glob [sc_cfg_get library $lib option var yosys_tiehigh_port]
+    set cellname [sc_cfg_get library $lib option var yosys_tiehigh_cell]
+    set pins [get_lib_pins $cellname/[sc_cfg_get library $lib option var yosys_tiehigh_port]]
+    if { [llength $pins] != [llength [sta::corners]] } {
+        puts "\[ERROR] mismatch"
+    }
+    foreach pin $pins {
+        if { [get_property $pin direction] != "output" } {
+            puts "\[ERROR] [get_full_name $pin] incorrect direction"
+        }
+    }
+}
+# yosys_tielow_cell
+foreach lib $sc_targetlibs {
+    puts "Checking $lib yosys_tielow_cell"
+    assert_glob [sc_cfg_get library $lib option var yosys_tielow_cell]
+    if { [get_lib_cells [sc_cfg_get library $lib option var yosys_tielow_cell]] == 0 } {
+        puts "\[ERROR] missing"
+    }
+}
+# yosys_tielow_port
+foreach lib $sc_targetlibs {
+    puts "Checking $lib yosys_tielow_port"
+    assert_glob [sc_cfg_get library $lib option var yosys_tielow_port]
+    set cellname [sc_cfg_get library $lib option var yosys_tielow_cell]
+    set pins [get_lib_pins $cellname/[sc_cfg_get library $lib option var yosys_tielow_port]]
+    if { [llength $pins] != [llength [sta::corners]] } {
+        puts "\[ERROR] mismatch"
+    }
+    foreach pin $pins {
+        if { [get_property $pin direction] != "output" } {
+            puts "\[ERROR] [get_full_name $pin] incorrect direction"
+        }
+    }
+}
+# yosys_abc_constraint_load
+foreach lib $sc_targetlibs {
+    set cap 0.0
+    puts "Checking $lib yosys_abc_constraint_load"
+    set cellname [sc_cfg_get library $lib option var yosys_buffer_cell]
+    set pins [get_lib_pins $cellname/[sc_cfg_get library $lib option var yosys_buffer_input]]
+    foreach pin $pins {
+        set cap [expr { max($cap, [get_property $pin capacitance]) }]
+    }
+    set lib_cap [sc_cfg_get library $lib option var yosys_abc_constraint_load]
+    set cap [expr { 4 * $cap }]
+    set cap "[format "%.3f" $cap][sta::unit_scaled_suffix capacitance]"
+
+    if { $lib_cap != $cap } {
+        puts "\[ERROR] mismatch, should be $cap, not $lib_cap"
+    }
+}
+
+# yosys_abc_clock_multiplier
+foreach lib $sc_targetlibs {
+    puts "Checking $lib yosys_abc_clock_multiplier"
+    set ps_convert [expr { round(1.0 / [sta::time_sta_ui 1e-12]) }]
+    set convert [sc_cfg_get library $lib option var yosys_abc_clock_multiplier]
+    if { $convert != $ps_convert } {
+        puts "\[ERROR] incorrect multiplier: should be $ps_convert, not $convert"
+    }
+}
+
+# Check openroad setup
+# openroad_tiehigh_cell
+foreach lib $sc_targetlibs {
+    puts "Checking $lib openroad_tiehigh_cell"
+    assert_glob [sc_cfg_get library $lib option var openroad_tiehigh_cell]
+    if { [get_lib_cells [sc_cfg_get library $lib option var openroad_tiehigh_cell]] == 0 } {
+        puts "\[ERROR] missing"
+    }
+}
+# openroad_tiehigh_port
+foreach lib $sc_targetlibs {
+    puts "Checking $lib openroad_tiehigh_port"
+    assert_glob [sc_cfg_get library $lib option var openroad_tiehigh_port]
+    set cellname [sc_cfg_get library $lib option var openroad_tiehigh_cell]
+    set pins [get_lib_pins $cellname/[sc_cfg_get library $lib option var openroad_tiehigh_port]]
+    if { [llength $pins] != [llength [sta::corners]] } {
+        puts "\[ERROR] mismatch"
+    }
+    foreach pin $pins {
+        if { [get_property $pin direction] != "output" } {
+            puts "\[ERROR] [get_full_name $pin] incorrect direction"
+        }
+    }
+}
+
+# openroad_tielow_cell
+foreach lib $sc_targetlibs {
+    puts "Checking $lib openroad_tielow_cell"
+    assert_glob [sc_cfg_get library $lib option var openroad_tielow_cell]
+    if { [get_lib_cells [sc_cfg_get library $lib option var openroad_tielow_cell]] == 0 } {
+        puts "\[ERROR] missing"
+    }
+}
+# openroad_tielow_port
+foreach lib $sc_targetlibs {
+    puts "Checking $lib openroad_tielow_port"
+    assert_glob [sc_cfg_get library $lib option var openroad_tielow_port]
+    set cellname [sc_cfg_get library $lib option var openroad_tielow_cell]
+    set pins [get_lib_pins $cellname/[sc_cfg_get library $lib option var openroad_tielow_port]]
+    if { [llength $pins] != [llength [sta::corners]] } {
+        puts "\[ERROR] mismatch"
+    }
+    foreach pin $pins {
+        if { [get_property $pin direction] != "output" } {
+            puts "\[ERROR] [get_full_name $pin] incorrect direction"
+        }
+    }
+}

siliconcompiler/tools/opensta/scripts/sc_timing.tcl

@@ -128,7 +128,7 @@ source "$sc_refdir/sc_procs.tcl"
 
 set opensta_top_n_paths [lindex [sc_cfg_tool_task_get var top_n_paths] 0]
 
-set fields "{capacitance slew input_pins nets fanout}"
+set fields "{capacitance slew input_pins hierarcial_pins net fanout}"
 set PREFIX "SC_METRIC:"
 
 puts "$PREFIX timeunit"

siliconcompiler/tools/sv2v/sv2v.py

@@ -14,13 +14,12 @@ Sources: https://github.com/zachjs/sv2v
 Installation: https://github.com/zachjs/sv2v
 '''
 
-from siliconcompiler.tools.sv2v import convert
-
 
 ####################################################################
 # Make Docs
 ####################################################################
 def make_docs(chip):
+    from siliconcompiler.tools.sv2v import convert
     convert.setup(chip)
     return chip
 

siliconcompiler/tools/verilator/compile.py

@@ -97,6 +97,12 @@ def setup(chip):
              "'vcd' or 'fst'. Defaults to 'vcd'.",
              field='help')
 
+    chip.set('tool', tool, 'task', task, 'var', 'initialize_random',
+             'true/false, when true registers will reset with a random value.',
+             field='help')
+    chip.set('tool', tool, 'task', task, 'var', 'initialize_random', False,
+             step=step, index=index, clobber=False)
+
 
 def runtime_options(chip):
     tool = 'verilator'
@@ -107,6 +113,11 @@ def runtime_options(chip):
 
     cmdlist = runtime_options_tool(chip)
 
+    random_init = chip.get('tool', tool, 'task', task, 'var',
+                           'initialize_random', step=step, index=index)
+    if random_init == ['true']:
+        cmdlist.extend(['--x-assign', 'unique'])
+
     cmdlist.extend(['--exe', '--build'])
 
     threads = chip.get('tool', tool, 'task', task, 'threads', step=step, index=index)

siliconcompiler/tools/verilator/verilator.py

@@ -32,13 +32,13 @@ from siliconcompiler.tools._common import (
     get_tool_task,
     input_provides
 )
-from siliconcompiler.targets import freepdk45_demo
 
 
 ####################################################################
 # Make Docs
 ####################################################################
 def make_docs(chip):
+    from siliconcompiler.targets import freepdk45_demo
     chip.use(freepdk45_demo)
 
 
@@ -71,15 +71,13 @@ def setup(chip):
     chip.set('tool', tool, 'task', task, 'file', 'config',
              'Verilator configuration file',
              field='help')
-    if chip.get('tool', tool, 'task', task, 'file', 'config', step=step, index=index):
-        chip.add('tool', tool, 'task', task, 'require',
-                 ','.join(['tool', tool, 'task', task, 'file', 'config']),
-                 step=step, index=index)
+    add_require_input(chip, 'tool', tool, 'task', task, 'file', 'config')
+    add_require_input(chip, 'option', 'file', 'verilator_config')
 
     chip.set('tool', tool, 'task', task, 'var', 'enable_assert',
              'true/false, when true assertions are enabled in Verilator.',
              field='help')
-    chip.set('tool', tool, 'task', task, 'var', 'enable_assert', 'false',
+    chip.set('tool', tool, 'task', task, 'var', 'enable_assert', False,
              step=step, index=index, clobber=False)
 
     if chip.get('tool', tool, 'task', task, 'var', 'enable_assert', step=step, index=index):
@@ -132,8 +130,9 @@ def runtime_options(chip):
         cmdlist.append(libext_option)
 
     # Verilator docs recommend this file comes first in CLI arguments
-    for value in chip.find_files('tool', tool, 'task', task, 'file', 'config',
-                                 step=step, index=index):
+    for value in get_input_files(chip, 'tool', tool, 'task', task, 'file', 'config'):
+        cmdlist.append(value)
+    for value in get_input_files(chip, 'option', 'file', 'verilator_config'):
         cmdlist.append(value)
 
     for param, value in frontend_opts['param']:

siliconcompiler/tools/vivado/vivado.py

@@ -10,10 +10,10 @@ import os
 import re
 from siliconcompiler import sc_open
 from siliconcompiler.tools._common import record_metric
-from siliconcompiler.targets import fpgaflow_demo
 
 
 def make_docs(chip):
+    from siliconcompiler.targets import fpgaflow_demo
     chip.set('fpga', 'partname', 'ice40up5k-sg48')
     chip.use(fpgaflow_demo)