siliconcompiler 0.29.0__py3-none-any.whl → 0.29.2__py3-none-any.whl

siliconcompiler/tools/gtkwave/show.py

@@ -0,0 +1,70 @@
+import os
+
+from siliconcompiler.tools.gtkwave import setup as tool_setup
+from siliconcompiler.tools._common import \
+    add_require_input, get_tool_task, input_provides
+
+
+def setup(chip):
+    '''
+    Show a VCD file.
+    '''
+
+    tool_setup(chip)
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+             step=step, index=index)
+
+    chip.set('tool', tool, 'task', task, 'refdir',
+             'tools/gtkwave/scripts',
+             step=step, index=index, package='siliconcompiler')
+
+    chip.set('tool', tool, 'task', task, 'refdir',
+             'tools/gtkwave/scripts',
+             step=step, index=index, package='siliconcompiler')
+    chip.set('tool', tool, 'task', task, 'script', 'sc_show.tcl',
+             step=step, index=index)
+
+    if f'{chip.top()}.vcd' in input_provides(chip, step, index):
+        chip.set('tool', tool, 'task', task, 'input', f'{chip.top()}.vcd', step=step, index=index)
+    elif chip.valid('tool', tool, 'task', task, 'var', 'show_filepath') and \
+            chip.get('tool', tool, 'task', task, 'var', 'show_filepath', step=step, index=index):
+        chip.add('tool', tool, 'task', task, 'require',
+                 ",".join(['tool', tool, 'task', task, 'var', 'show_filepath']),
+                 step=step, index=index)
+    else:
+        add_require_input(chip, 'input', 'waveform', 'vcd')
+
+    chip.set('tool', tool, 'task', task, 'var', 'show_exit', False,
+             step=step, index=index, clobber=False)
+
+
+def runtime_options(chip):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    options = []
+
+    threads = chip.get('tool', tool, 'task', task, 'threads', step=step, index=index)
+    if threads:
+        options.append(f'--cpu={threads}')
+
+    script = chip.find_files('tool', tool, 'task', task, 'script', step=step, index=index)[0]
+    options.append(f'--script={script}')
+
+    if os.path.exists(f'inputs/{chip.top()}.vcd'):
+        dump = f'inputs/{chip.top()}.vcd'
+    elif chip.valid('tool', tool, 'task', task, 'var', 'show_filepath') and \
+            chip.get('tool', tool, 'task', task, 'var', 'show_filepath', step=step, index=index):
+        dump = chip.get('tool', tool, 'task', task, 'var', 'show_filepath',
+                        step=step, index=index)[0]
+    else:
+        dump = chip.find_files('input', 'waveform', 'vcd', step=step, index=index)[0]
+    options.append(f'--dump={dump}')
+
+    return options

siliconcompiler/tools/icarus/compile.py

@@ -75,6 +75,10 @@ def runtime_options(chip):
         cmdlist.append('-I' + value)
     for value in opts['define']:
         cmdlist.append('-D' + value)
+
+    # add siliconcompiler specific defines
+    cmdlist.append(f"-DSILICONCOMPILER_TRACE_FILE=\\\"reports/{design}.vcd\\\"")
+
     for value in get_input_files(chip, 'input', 'cmdfile', 'f'):
         cmdlist.append('-f ' + value)
     for value in get_input_files(chip, 'input', 'rtl', 'netlist'):

siliconcompiler/tools/klayout/convert_drc_db.py

@@ -1,10 +1,10 @@
 from siliconcompiler.tools._common import input_provides, input_file_node_name, get_tool_task
 
-from siliconcompiler.tools.klayout import klayout
 from siliconcompiler.tools.klayout.klayout import setup as setup_tool
 
 
 def make_docs(chip):
+    from siliconcompiler.tools.klayout import klayout
     klayout.make_docs(chip)
 
 

siliconcompiler/tools/klayout/drc.py

@@ -5,12 +5,12 @@ from siliconcompiler.tools._common import input_provides, has_input_files, \
     get_input_files, get_tool_task, record_metric
 from siliconcompiler.tools._common.asic import set_tool_task_var, get_tool_task_var
 
-from siliconcompiler.tools.klayout import klayout
 from siliconcompiler.tools.klayout.klayout import setup as setup_tool
 import xml.etree.ElementTree as ET
 
 
 def make_docs(chip):
+    from siliconcompiler.tools.klayout import klayout
     klayout.make_docs(chip)
     chip.set('tool', 'klayout', 'task', 'drc', 'var', 'drc_name', '<drc_name>',
              step='<step>', index='<index>')

siliconcompiler/tools/klayout/export.py

@@ -1,5 +1,6 @@
-
+import os
 from siliconcompiler.tools.klayout.klayout import setup as setup_tool
+from siliconcompiler.tools.klayout.klayout import runtime_options as runtime_options_tool
 from siliconcompiler.tools.klayout.screenshot import setup_gui_screenshot
 from siliconcompiler.tools._common import input_provides, get_tool_task
 from siliconcompiler.tools._common.asic import get_libraries
@@ -120,3 +121,9 @@ def setup(chip):
     if chip.get('tool', tool, 'task', task, 'var', 'screenshot',
                 step=step, index=index) == ['true']:
         setup_gui_screenshot(chip, require_input=False)
+
+
+def runtime_options(chip):
+    return runtime_options_tool(chip) + [
+        '-rd', f'SC_TOOLS_ROOT={os.path.dirname(os.path.dirname(__file__))}'
+    ]

siliconcompiler/tools/klayout/klayout.py

@@ -15,13 +15,13 @@ from pathlib import Path
 import platform
 import shutil
 from siliconcompiler.tools._common import get_tool_task
-from siliconcompiler.targets import freepdk45_demo
 
 
 ####################################################################
 # Make Docs
 ####################################################################
 def make_docs(chip):
+    from siliconcompiler.targets import freepdk45_demo
     chip.use(freepdk45_demo)
 
 
@@ -102,7 +102,7 @@ def runtime_options(chip):
     # that has no 3rd-party dependencies.
     # This must be done at runtime to work in a remote context.
 
-    return ['-rd', f'SC_ROOT={chip.scroot}']
+    return ['-rd', f'SC_KLAYOUT_ROOT={os.path.dirname(__file__)}']
 
 
 ################################

siliconcompiler/tools/klayout/klayout_convert_drc_db.py

@@ -150,9 +150,9 @@ def convert_drc(view, path):
 
 def main():
     # SC_ROOT provided by CLI
-    sys.path.append(SC_ROOT)  # noqa: F821
+    sys.path.append(SC_KLAYOUT_ROOT)  # noqa: F821
 
-    from tools.klayout.klayout_utils import get_schema
+    from klayout_utils import get_schema
 
     schema = get_schema(manifest='sc_manifest.json')
 

siliconcompiler/tools/klayout/klayout_export.py

@@ -42,7 +42,7 @@ import fnmatch
 def gds_export(design_name, in_def, in_files, out_file, tech, allow_missing, config_file='',
                seal_file='',
                timestamps=True):
-    from tools.klayout.klayout_utils import get_write_options  # noqa E402
+    from klayout_utils import get_write_options  # noqa E402
 
     # Load def file
     main_layout = pya.Layout()
@@ -119,16 +119,18 @@ def gds_export(design_name, in_def, in_files, out_file, tech, allow_missing, con
 
 def main():
     # SC_ROOT provided by CLI
-    sys.path.append(SC_ROOT)  # noqa: F821
+    sys.path.append(SC_KLAYOUT_ROOT)  # noqa: F821
+    sys.path.append(SC_TOOLS_ROOT)  # noqa: F821
+    print(sys.path)
 
-    from tools.klayout.klayout_utils import (
+    from klayout_utils import (
         technology,
         get_streams,
         save_technology,
         get_schema
     )
-    from tools.klayout.klayout_show import show
-    from tools._common.asic import get_libraries
+    from klayout_show import show
+    from _common.asic import get_libraries
 
     schema = get_schema(manifest='sc_manifest.json')
 

siliconcompiler/tools/klayout/klayout_operations.py

@@ -148,7 +148,7 @@ def rename_cell(base_layout, old_name, new_name):
 
 
 def write_stream(layout, outfile, timestamps):
-    from tools.klayout.klayout_utils import get_write_options
+    from klayout_utils import get_write_options
 
     print(f"[INFO] Writing layout: '{outfile}'")
 
@@ -324,9 +324,10 @@ def parse_operations(schema, base_layout, steps):
 
 if __name__ == "__main__":
     # SC_ROOT provided by CLI
-    sys.path.append(SC_ROOT)  # noqa: F821
+    sys.path.append(SC_KLAYOUT_ROOT)  # noqa: F821
+    sys.path.append(SC_TOOLS_ROOT)  # noqa: F821
 
-    from tools.klayout.klayout_utils import (
+    from klayout_utils import (
         technology,
         get_streams,
         get_schema

siliconcompiler/tools/klayout/klayout_show.py

@@ -205,9 +205,10 @@ def __screenshot_montage(schema, view, xbins, ybins):
 
 def main():
     # SC_ROOT provided by CLI, and is only accessible when this is main module
-    sys.path.append(SC_ROOT)  # noqa: F821
+    sys.path.append(SC_KLAYOUT_ROOT)  # noqa: F821
+    sys.path.append(SC_TOOLS_ROOT)  # noqa: F821
 
-    from tools.klayout.klayout_utils import (
+    from klayout_utils import (
         technology,
         get_schema
     )

siliconcompiler/tools/klayout/klayout_utils.py

@@ -21,7 +21,7 @@ def get_streams(schema):
 
 
 def technology(design, schema):
-    from tools._common.asic import get_libraries
+    from _common.asic import get_libraries
 
     sc_step = schema.get('arg', 'step')
     sc_index = schema.get('arg', 'index')

siliconcompiler/tools/klayout/operations.py

@@ -1,5 +1,7 @@
+import os
 from siliconcompiler import SiliconCompilerError
 from siliconcompiler.tools.klayout.klayout import setup as setup_tool
+from siliconcompiler.tools.klayout.klayout import runtime_options as runtime_options_tool
 from siliconcompiler.tools._common import input_provides, get_tool_task
 
 
@@ -194,3 +196,9 @@ def setup(chip):
                 raise SiliconCompilerError('write requires a filename to save to', chip=chip)
             chip.add('tool', tool, 'task', task, 'output', args,
                      step=step, index=index)
+
+
+def runtime_options(chip):
+    return runtime_options_tool(chip) + [
+        '-rd', f'SC_TOOLS_ROOT={os.path.dirname(os.path.dirname(__file__))}'
+    ]

siliconcompiler/tools/klayout/screenshot.py

@@ -1,11 +1,12 @@
-from siliconcompiler.tools.klayout import klayout
 from siliconcompiler.tools.klayout.klayout import setup as setup_tool
 from siliconcompiler.tools.klayout.show import general_gui_setup
 from siliconcompiler.tools.klayout.show import pre_process as show_pre_process
+from siliconcompiler.tools.klayout.show import runtime_options as show_runtime_options
 from siliconcompiler.tools._common import get_tool_task
 
 
 def make_docs(chip):
+    from siliconcompiler.tools.klayout import klayout
     klayout.make_docs(chip)
     chip.set('tool', 'klayout', 'task', 'screenshot', 'var', 'show_filepath', '<path>')
 
@@ -98,3 +99,7 @@ def setup_gui_screenshot(chip, require_input=True):
             for y in range(ybins):
                 chip.add('tool', tool, 'task', task, 'output', f'{design}_X{x}_Y{y}.png',
                          step=step, index=index)
+
+
+def runtime_options(chip):
+    return show_runtime_options(chip)

siliconcompiler/tools/klayout/show.py

@@ -1,12 +1,13 @@
 import os
 import shutil
 
-from siliconcompiler.tools.klayout import klayout
 from siliconcompiler.tools.klayout.klayout import setup as setup_tool
+from siliconcompiler.tools.klayout.klayout import runtime_options as runtime_options_tool
 from siliconcompiler.tools._common import find_incoming_ext, get_tool_task
 
 
 def make_docs(chip):
+    from siliconcompiler.tools.klayout import klayout
     klayout.make_docs(chip)
     chip.set('tool', 'klayout', 'task', 'show', 'var', 'show_filepath', '<path>')
 
@@ -99,3 +100,9 @@ def pre_process(chip):
             ext_file = os.path.join(rel_path, f'{chip.top()}.{ext}')
             if ext_file and os.path.exists(ext_file):
                 shutil.copy2(ext_file, f"inputs/{chip.top()}.{ext}")
+
+
+def runtime_options(chip):
+    return runtime_options_tool(chip) + [
+        '-rd', f'SC_TOOLS_ROOT={os.path.dirname(os.path.dirname(__file__))}'
+    ]

siliconcompiler/tools/magic/magic.py

@@ -13,7 +13,6 @@ import gzip
 import shutil
 import os
 from siliconcompiler.tools._common import input_provides, get_tool_task
-from siliconcompiler.targets import freepdk45_demo
 from siliconcompiler import utils
 
 
@@ -21,6 +20,7 @@ from siliconcompiler import utils
 # Make Docs
 ####################################################################
 def make_docs(chip):
+    from siliconcompiler.targets import freepdk45_demo
     chip.use(freepdk45_demo)
 
 

siliconcompiler/tools/openroad/__init__.py

@@ -11,13 +11,13 @@ Sources: https://github.com/The-OpenROAD-Project/OpenROAD
 Installation: https://github.com/The-OpenROAD-Project/OpenROAD
 '''
 from siliconcompiler.tools._common import get_tool_task
-from siliconcompiler.targets import asap7_demo
 
 
 ####################################################################
 # Make Docs
 ####################################################################
 def make_docs(chip):
+    from siliconcompiler.targets import asap7_demo
     chip.use(asap7_demo)
 
 

siliconcompiler/tools/openroad/_apr.py

@@ -5,7 +5,7 @@ from siliconcompiler import utils
 from siliconcompiler.tools._common import input_provides, add_common_file, \
     get_tool_task, record_metric
 from siliconcompiler.tools._common.asic import get_mainlib, set_tool_task_var, get_libraries, \
-    CellArea
+    CellArea, set_tool_task_lib_var
 from siliconcompiler.tools.openroad import setup as tool_setup
 
 
@@ -811,7 +811,7 @@ def define_mpl_params(chip):
                              'macro placement ([x, y] in microns)')
 
     set_tool_task_var(chip, param_key='rtlmp_enable',
-                      default_value='false',
+                      default_value=True,
                       schelp='true/false, enables the RTLMP macro placement')
     set_tool_task_var(chip, param_key='rtlmp_min_instances',
                       schelp='minimum number of instances to use while clustering for '
@@ -894,6 +894,14 @@ def define_ord_params(chip):
                       require=['key'],
                       schelp='number of Y bins to use for heatmap image generation')
 
+    set_tool_task_lib_var(chip, param_key='scan_chain_cells',
+                          default_value=None,
+                          schelp='cells to use for scan chain insertion')
+
+    set_tool_task_lib_var(chip, param_key='multibit_ff_cells',
+                          default_value=None,
+                          schelp='multibit flipflop cells')
+
 
 def define_ord_files(chip):
     step = chip.get('arg', 'step')
@@ -1101,6 +1109,7 @@ def build_pex_corners(chip):
                           'inputs',
                           'sc_parasitics.tcl'),
              step=step, index=index, clobber=True)
+    chip.set('tool', tool, 'task', task, 'file', 'parasitics', False, field='copy')
 
     with open(chip.get('tool', tool, 'task', task, 'file', 'parasitics',
                        step=step, index=index)[0], 'w') as f:

siliconcompiler/tools/openroad/global_placement.py

@@ -1,9 +1,11 @@
 from siliconcompiler.tools._common import get_tool_task
 from siliconcompiler.tools.openroad._apr import setup as apr_setup
-from siliconcompiler.tools.openroad._apr import set_reports, set_pnr_inputs, set_pnr_outputs
+from siliconcompiler.tools.openroad._apr import set_reports, set_pnr_inputs, set_pnr_outputs, \
+    set_tool_task_var
 from siliconcompiler.tools.openroad._apr import \
     define_ord_params, define_sta_params, define_sdc_params, \
-    define_gpl_params, define_grt_params, define_rsz_params
+    define_gpl_params, define_grt_params, define_rsz_params, \
+    define_ppl_params
 from siliconcompiler.tools.openroad._apr import build_pex_corners, define_ord_files
 from siliconcompiler.tools.openroad._apr import extract_metrics
 
@@ -35,6 +37,7 @@ def setup(chip):
     define_gpl_params(chip)
     define_grt_params(chip)
     define_rsz_params(chip)
+    define_ppl_params(chip)
 
     set_reports(chip, [
         'setup',
@@ -48,6 +51,24 @@ def setup(chip):
         'power_density'
     ])
 
+    set_tool_task_var(chip, param_key='enable_multibit_clustering',
+                      default_value=False,
+                      schelp='true/false, when true multibit clustering will be performed.')
+
+    set_tool_task_var(chip, param_key='enable_scan_chains',
+                      default_value=False,
+                      schelp='true/false, when true scan chains will be inserted.')
+
+    set_tool_task_var(chip, param_key='scan_enable_port_pattern',
+                      schelp='pattern of the scan chain enable port.',
+                      skip=['pdk', 'lib'])
+    set_tool_task_var(chip, param_key='scan_in_port_pattern',
+                      schelp='pattern of the scan chain in port.',
+                      skip=['pdk', 'lib'])
+    set_tool_task_var(chip, param_key='scan_out_port_pattern',
+                      schelp='pattern of the scan chain out port.',
+                      skip=['pdk', 'lib'])
+
 
 def pre_process(chip):
     define_ord_files(chip)

siliconcompiler/tools/openroad/init_floorplan.py

@@ -50,7 +50,7 @@ def setup(chip):
                       schelp='remove buffers inserted by synthesis')
 
     set_tool_task_var(chip, param_key='remove_dead_logic',
-                      default_value=False,
+                      default_value=True,
                       schelp='remove logic which does not drive a primary output')
 
     # Handle additional input files

siliconcompiler/tools/openroad/scripts/apr/preamble.tcl

@@ -61,7 +61,7 @@ sc_setup_sta
 
 sc_setup_parasitics
 
-set_dont_use [sc_cfg_get library $sc_mainlib asic cells dontuse]
+sc_set_dont_use
 
 sc_setup_global_routing
 

siliconcompiler/tools/openroad/scripts/apr/sc_clock_tree_synthesis.tcl

@@ -17,6 +17,8 @@ source -echo "$sc_refdir/apr/preamble.tcl"
 ###############################
 
 if { [llength [all_clocks]] > 0 } {
+    sc_set_dont_use -clock -report dont_use.clock_tree_synthesis
+
     # Clone clock tree inverters next to register loads
     # so cts does not try to buffer the inverted clocks.
     repair_clock_inverters
@@ -50,6 +52,8 @@ if { [llength [all_clocks]] > 0 } {
     sc_detailed_placement
 
     global_connect
+
+    sc_set_dont_use
 }
 
 # estimate for metrics

siliconcompiler/tools/openroad/scripts/apr/sc_global_placement.tcl

@@ -11,16 +11,79 @@ source ./sc_manifest.tcl > /dev/null
 set sc_refdir [sc_cfg_tool_task_get refdir]
 source -echo "$sc_refdir/apr/preamble.tcl"
 
+set dont_use_args []
+
+if { [lindex [sc_cfg_tool_task_get var enable_scan_chains] 0] == "true" } {
+    lappend dont_use_args -scanchain
+}
+if { [lindex [sc_cfg_tool_task_get var enable_multibit_clustering] 0] == "true" } {
+    lappend dont_use_args -multibit
+}
+
+sc_set_dont_use {*}$dont_use_args -report dont_use.global_placement
+
+###############################
+# Scan Chain Preparation
+###############################
+
+if { [lindex [sc_cfg_tool_task_get var enable_scan_chains] 0] == "true" } {
+    set dft_args []
+    if { [sc_cfg_tool_task_get var scan_in_port_pattern] != [] } {
+        lappend dft_args -scan_in_name_pattern \
+            [lindex [sc_cfg_tool_task_get var scan_in_port_pattern] 0]
+    }
+    if { [sc_cfg_tool_task_get var scan_out_port_pattern] != [] } {
+        lappend dft_args -scan_out_name_pattern \
+            [lindex [sc_cfg_tool_task_get var scan_out_port_pattern] 0]
+    }
+    if { [sc_cfg_tool_task_get var scan_enable_port_pattern] != [] } {
+        lappend dft_args -scan_enable_name_pattern \
+            [lindex [sc_cfg_tool_task_get var scan_enable_port_pattern] 0]
+    }
+
+    set_dft_config -clock_mixing clock_mix {*}$dft_args
+    tee -file reports/scan_chain_config.rpt {report_dft_config}
+    scan_replace
+}
+
+###############################
+# Perform multi-bit clustering
+###############################
+
+if { [lindex [sc_cfg_tool_task_get var enable_multibit_clustering] 0] == "true" } {
+    cluster_flops
+}
+
 ###############################
 # Global Placement
 ###############################
 
 sc_global_placement
 
-estimate_parasitics -placement
+###############################
+# Scan Chain Finalize
+###############################
+
+if { [lindex [sc_cfg_tool_task_get var enable_scan_chains] 0] == "true" } {
+    tee -file reports/scan_chain.rpt {preview_dft -verbose}
+    insert_dft
+
+    set new_ios [sc_get_unplaced_io_nets]
+    if { [llength $new_ios] > 0 } {
+        foreach net $new_ios {
+            utl::report "New IO net [$net getName]"
+        }
+        utl::warn FLW 1 "Scan chain generated new ports, rerunning pin placement"
+        sc_pin_placement
+    }
+}
 
 ###############################
 # Task Postamble
 ###############################
 
+sc_set_dont_use
+
+estimate_parasitics -placement
+
 source -echo "$sc_refdir/apr/postamble.tcl"

siliconcompiler/tools/openroad/scripts/apr/sc_repair_design.tcl

@@ -28,6 +28,8 @@ estimate_parasitics -placement
 # Repair DRVs
 ###############################
 
+sc_set_dont_use -scanchain -multibit -report dont_use.repair_drv
+
 set repair_design_args []
 
 set rsz_cap_margin [lindex [sc_cfg_tool_task_get {var} rsz_cap_margin] 0]
@@ -43,6 +45,8 @@ repair_design \
     -verbose \
     {*}$repair_design_args
 
+sc_set_dont_use
+
 ###############################
 # Tie-off cell insertion
 ###############################

siliconcompiler/tools/openroad/scripts/apr/sc_repair_timing.tcl

@@ -34,6 +34,9 @@ if { [lindex [sc_cfg_tool_task_get var rsz_skip_setup_repair] 0] != "true" } {
     # Setup Repair
     ###############################
 
+    # Enable ffs for resizing
+    sc_set_dont_use -scanchain -multibit -report dont_use.repair_timing.setup
+
     estimate_parasitics -placement
 
     repair_timing \
@@ -45,6 +48,9 @@ if { [lindex [sc_cfg_tool_task_get var rsz_skip_setup_repair] 0] != "true" } {
         {*}$repair_timing_args
 
     sc_detailed_placement
+
+    # Restore dont use
+    sc_set_dont_use
 }
 
 if { [lindex [sc_cfg_tool_task_get var rsz_skip_hold_repair] 0] != "true" } {
@@ -55,7 +61,7 @@ if { [lindex [sc_cfg_tool_task_get var rsz_skip_hold_repair] 0] != "true" } {
     estimate_parasitics -placement
 
     # Enable hold cells
-    unset_dont_use [sc_cfg_get library $sc_mainlib asic cells hold]
+    sc_set_dont_use -hold -scanchain -multibit -report dont_use.repair_timing.hold
 
     repair_timing \
         -hold \
@@ -68,7 +74,7 @@ if { [lindex [sc_cfg_tool_task_get var rsz_skip_hold_repair] 0] != "true" } {
     sc_detailed_placement
 
     # Restore dont use
-    set_dont_use [sc_cfg_get library $sc_mainlib asic cells dontuse]
+    sc_set_dont_use
 }
 
 global_connect