siliconcompiler 0.28.4__py3-none-any.whl → 0.28.5__py3-none-any.whl

siliconcompiler/tools/openroad/scripts/sc_rdlroute.tcl

@@ -0,0 +1,184 @@
+###############################
+# Reading SC Schema
+###############################
+
+source ./sc_manifest.tcl > /dev/null
+
+##############################
+# Schema Adapter
+###############################
+
+set sc_tool openroad
+set sc_step [sc_cfg_get arg step]
+set sc_index [sc_cfg_get arg index]
+set sc_flow [sc_cfg_get option flow]
+set sc_task [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
+
+set sc_refdir [sc_cfg_tool_task_get refdir]
+
+# Design
+set sc_design [sc_top]
+set sc_optmode [sc_cfg_get option optmode]
+set sc_pdk [sc_cfg_get option pdk]
+set sc_stackup [sc_cfg_get option stackup]
+
+# PDK Design Rules
+set sc_libtype [lindex [sc_cfg_get option var openroad_libtype] 0]
+set sc_techlef [sc_cfg_get pdk $sc_pdk aprtech openroad $sc_stackup $sc_libtype lef]
+
+set sc_threads [sc_cfg_tool_task_get threads]
+
+###############################
+# Optional
+###############################
+
+# MACROS
+set sc_macrolibs [sc_get_asic_libraries macro]
+
+###############################
+# Suppress messages if requested
+###############################
+
+foreach msg [sc_cfg_tool_task_get warningoff] {
+  set or_msg [split $msg "-"]
+  if { [llength $or_msg] != 2 } {
+    utl::warn FLW 1 "$msg is not a valid message id"
+  } else {
+    set or_tool [lindex $or_msg 0]
+    set or_msg_id [expr { int([lindex $or_msg 1]) }]
+    utl::info FLW 1 "Suppressing $msg messages"
+    suppress_message $or_tool $or_msg_id
+  }
+}
+
+###############################
+# Source helper functions
+###############################
+
+source "$sc_refdir/sc_procs.tcl"
+
+###############################
+# Common Setup
+###############################
+
+set_thread_count $sc_threads
+
+# Read techlef
+puts "Reading techlef: ${sc_techlef}"
+read_lef $sc_techlef
+
+# Read Lefs
+foreach lib "$sc_macrolibs" {
+  foreach lef_file [sc_cfg_get library $lib output $sc_stackup lef] {
+    puts "Reading lef: ${lef_file}"
+    read_lef $lef_file
+  }
+}
+
+# Read Verilog
+if { [file exists "inputs/${sc_design}.vg"] } {
+  puts "Reading netlist verilog: inputs/${sc_design}.vg"
+  read_verilog "inputs/${sc_design}.vg"
+} else {
+  foreach netlist [sc_cfg_get input netlist verilog] {
+    puts "Reading netlist verilog: ${netlist}"
+    read_verilog $netlist
+  }
+}
+link_design $sc_design
+
+###############################
+# Source Step Script
+###############################
+
+utl::push_metrics_stage "sc__prestep__{}"
+if { [sc_cfg_tool_task_exists prescript] } {
+  foreach sc_pre_script [sc_cfg_tool_task_get prescript] {
+    puts "Sourcing pre script: ${sc_pre_script}"
+    source -echo $sc_pre_script
+  }
+}
+utl::pop_metrics_stage
+
+utl::push_metrics_stage "sc__step__{}"
+
+###########################
+# Initialize floorplan
+###########################
+
+if { [sc_cfg_exists input asic floorplan] } {
+  set def [lindex [sc_cfg_get input asic floorplan] 0]
+  puts "Reading floorplan DEF: ${def}"
+  read_def -floorplan_initialize $def
+} else {
+  #NOTE: assuming a two tuple value as lower left, upper right
+  set sc_diearea [sc_cfg_get constraint outline]
+
+  # Use die and core sizes
+  set sc_diesize "[lindex $sc_diearea 0] [lindex $sc_diearea 1]"
+
+  set outline [odb::Rect]
+  $outline set_xlo [ord::microns_to_dbu [lindex $sc_diesize 0]]
+  $outline set_ylo [ord::microns_to_dbu [lindex $sc_diesize 1]]
+  $outline set_xhi [ord::microns_to_dbu [lindex $sc_diesize 2]]
+  $outline set_yhi [ord::microns_to_dbu [lindex $sc_diesize 3]]
+
+  [ord::get_db_block] setDieArea $outline
+}
+
+puts "Floorplan information:"
+puts "Die area: [ord::get_die_area]"
+
+###########################
+# Track Creation
+###########################
+
+# source tracks from file if found, else else use schema entries
+make_tracks
+
+###########################
+# RDL Routing
+###########################
+foreach rdl_file [sc_cfg_tool_task_get {file} rdlroute] {
+  puts "Sourcing rdlroute: ${rdl_file}"
+  source $rdl_file
+}
+
+######################
+# Do fill
+######################
+
+set removed_obs 0
+foreach obstruction [[ord::get_db_block] getObstructions] {
+  odb::dbObstruction_destroy $obstruction
+  incr removed_obs
+}
+utl::info FLW 1 "Deleted $removed_obs routing obstructions"
+
+if {
+  [lindex [sc_cfg_tool_task_get var fin_add_fill] 0] == "true" &&
+  [sc_cfg_exists pdk $sc_pdk aprtech openroad $sc_stackup $sc_libtype fill]
+} {
+  set sc_fillrules \
+    [lindex [sc_cfg_get pdk $sc_pdk aprtech openroad $sc_stackup $sc_libtype fill] 0]
+  density_fill -rules $sc_fillrules
+}
+
+utl::pop_metrics_stage
+
+utl::push_metrics_stage "sc__poststep__{}"
+if { [sc_cfg_tool_task_exists postscript] } {
+  foreach sc_post_script [sc_cfg_tool_task_get postscript] {
+    puts "Sourcing post script: ${sc_post_script}"
+    source -echo $sc_post_script
+  }
+}
+utl::pop_metrics_stage
+
+###############################
+# Write Design Data
+###############################
+
+utl::push_metrics_stage "sc__write__{}"
+source "$sc_refdir/sc_write.tcl"
+utl::pop_metrics_stage

siliconcompiler/tools/openroad/scripts/sc_report.tcl

@@ -0,0 +1,170 @@
+###############################
+# Report Metrics
+###############################
+
+proc sc_display_report { report } {
+  if { ![file exists $report] } {
+    return
+  }
+  set fid [open $report r]
+  set report_content [read $fid]
+  close $fid
+  puts $report_content
+}
+
+set fields "{capacitance slew input_pins nets fanout}"
+set PREFIX "SC_METRIC:"
+
+if { [sc_cfg_tool_task_check_in_list setup var reports] } {
+  puts "$PREFIX report_checks -path_delay max"
+  report_checks -fields $fields -path_delay max -format full_clock_expanded \
+    > reports/timing/setup.rpt
+  sc_display_report reports/timing/setup.rpt
+  report_checks -path_delay max -group_count $openroad_sta_top_n_paths \
+    > reports/timing/setup.topN.rpt
+
+  puts "$PREFIX setupslack"
+  report_worst_slack -max > reports/timing/worst_slack.setup.rpt
+  sc_display_report reports/timing/worst_slack.setup.rpt
+  report_worst_slack_metric -setup
+
+  puts "$PREFIX tns"
+  report_tns > reports/timing/total_negative_slack.rpt
+  sc_display_report reports/timing/total_negative_slack.rpt
+  report_tns_metric -setup
+}
+
+if { [sc_cfg_tool_task_check_in_list hold var reports] } {
+  puts "$PREFIX report_checks -path_delay min"
+  report_checks -fields $fields -path_delay min -format full_clock_expanded \
+    > reports/timing/hold.rpt
+  sc_display_report reports/timing/hold.rpt
+  report_checks -path_delay min -group_count $openroad_sta_top_n_paths \
+    > reports/timing/hold.topN.rpt
+
+  puts "$PREFIX holdslack"
+  report_worst_slack -min > reports/timing/worst_slack.hold.rpt
+  sc_display_report reports/timing/worst_slack.hold.rpt
+  report_worst_slack_metric -hold
+
+  report_tns_metric -hold
+}
+
+if { [sc_cfg_tool_task_check_in_list unconstrained var reports] } {
+  puts "$PREFIX unconstrained"
+  report_checks -fields $fields -unconstrained -format full_clock_expanded \
+    > reports/timing/unconstrained.rpt
+  sc_display_report reports/timing/unconstrained.rpt
+  report_checks -unconstrained -group_count $openroad_sta_top_n_paths \
+    > reports/timing/unconstrained.topN.rpt
+}
+
+if {
+  [sc_cfg_tool_task_check_in_list clock_skew var reports] &&
+  [llength [all_clocks]] > 0
+} {
+  puts "$PREFIX clock_skew"
+  report_clock_skew -setup -digits 4 > reports/timing/skew.setup.rpt
+  sc_display_report reports/timing/skew.setup.rpt
+  report_clock_skew_metric -setup
+  report_clock_skew -hold -digits 4 > reports/timing/skew.hold.rpt
+  sc_display_report reports/timing/skew.hold.rpt
+  report_clock_skew_metric -hold
+}
+
+if { [sc_cfg_tool_task_check_in_list drv_violations var reports] } {
+  puts "$PREFIX DRV violators"
+  report_check_types -max_slew -max_capacitance -max_fanout -violators \
+    > reports/timing/drv_violators.rpt
+  sc_display_report reports/timing/drv_violators.rpt
+  report_erc_metrics
+
+  puts "$PREFIX floating nets"
+  report_floating_nets -verbose > reports/floating_nets.rpt
+  sc_display_report reports/floating_nets.rpt
+}
+
+utl::metric_int "timing__clocks" [llength [all_clocks]]
+
+if { [sc_cfg_tool_task_check_in_list fmax var reports] } {
+  puts "$PREFIX fmax"
+  # Model on: https://github.com/The-OpenROAD-Project/OpenSTA/blob/f913c3ddbb3e7b4364ed4437c65ac78c4da9174b/tcl/Search.tcl#L1078
+  set fmax_metric 0
+  foreach clk [sta::sort_by_name [all_clocks]] {
+    set clk_name [get_name $clk]
+    set min_period [sta::find_clk_min_period $clk 1]
+    if { $min_period == 0.0 } {
+      continue
+    }
+    set fmax [expr { 1.0 / $min_period }]
+    utl::metric_float "timing__fmax__clock:${clk_name}" $fmax
+    puts "$clk_name fmax = [format %.2f [expr { $fmax / 1e6 }]] MHz"
+    set fmax_metric [expr { max($fmax_metric, $fmax) }]
+  }
+  if { $fmax_metric > 0 } {
+    utl::metric_float "timing__fmax" $fmax_metric
+  }
+}
+
+# get logic depth of design
+utl::metric_int "design__logic__depth" [count_logic_depth]
+
+if { [sc_cfg_tool_task_check_in_list power var reports] } {
+  puts "$PREFIX power"
+  foreach corner [sta::corners] {
+    set corner_name [$corner name]
+    puts "Power for corner: $corner_name"
+    report_power -corner $corner_name > reports/power/${corner_name}.rpt
+    sc_display_report reports/power/${corner_name}.rpt
+  }
+  report_power_metric -corner $sc_power_corner
+}
+
+puts "$PREFIX cellarea"
+report_design_area
+report_design_area_metrics
+
+# get number of nets in design
+utl::metric_int "design__nets" [llength [[ord::get_db_block] getNets]]
+
+# get number of registers
+utl::metric_int "design__registers" [llength [all_registers]]
+
+# get number of buffers
+set bufs 0
+set invs 0
+foreach inst [get_cells -hierarchical *] {
+  set cell [$inst cell]
+  if { $cell == "NULL" } {
+    continue
+  }
+  set liberty_cell [$cell liberty_cell]
+  if { $liberty_cell == "NULL" } {
+    continue
+  }
+  if { [$liberty_cell is_buffer] } {
+    incr bufs
+  } elseif { [$liberty_cell is_inverter] } {
+    incr invs
+  }
+}
+utl::metric_int "design__buffers" $bufs
+utl::metric_int "design__inverters" $invs
+
+# get number of unconstrained endpoints
+with_output_to_variable endpoints {check_setup -unconstrained_endpoints}
+set unconstrained_endpoints [regexp -all -inline {[0-9]+} $endpoints]
+if { $unconstrained_endpoints == "" } {
+  set unconstrained_endpoints 0
+}
+utl::metric_int "timing__unconstrained" $unconstrained_endpoints
+
+# Write markers
+foreach markerdb [[ord::get_db_block] getMarkerCategories] {
+  if { [$markerdb getMarkerCount] == 0 } {
+    continue
+  }
+
+  $markerdb writeTR "reports/markers/${sc_design}.[$markerdb getName].rpt"
+  $markerdb writeJSON "reports/markers/${sc_design}.[$markerdb getName].json"
+}

siliconcompiler/tools/opensta/scripts/sc_report_libraries.tcl

@@ -55,7 +55,17 @@ foreach lib "$sc_targetlibs $sc_macrolibs" {
 
 # Report cells
 foreach cell [get_lib_cells *] {
-    puts [get_full_name $cell]
+    set desc ""
+    if { [get_property $cell is_buffer] } {
+        set desc " (buffer)"
+    } elseif { [get_property $cell is_inverter] } {
+        set desc " (inverter)"
+    } elseif {
+        [llength [get_lib_pins -quiet [get_full_name $cell]/* -filter is_register_clock==1]] != 0
+    } {
+        set desc " (register)"
+    }
+    puts "[get_full_name $cell]$desc"
 
     set pins [get_lib_pins -quiet [get_full_name $cell]/*]
     if { [llength $pins] == 0 } {

siliconcompiler/tools/xyce/__init__.py

@@ -7,7 +7,7 @@ and small-scale parallel runs on Unix-like systems.
 
 Documentation: https://xyce.sandia.gov/documentation-tutorials/
 
-Sources: https://github.com/Xyce/Xyce
+Sources: https://xyce.sandia.gov/downloads/source-code/
 
 Installation: https://xyce.sandia.gov/documentation-tutorials/building-guide/
 

siliconcompiler/toolscripts/_tools.json

@@ -1,7 +1,7 @@
 {
   "openroad": {
     "git-url": "https://github.com/The-OpenROAD-Project/OpenROAD.git",
-    "git-commit": "ea63b9aa612f296523b0ec8a6b51dec94de8839c",
+    "git-commit": "1531ad983bfe91384e9253769fdc5f8dcf24fea8",
     "docker-cmds": [
       "# Remove OR-Tools files",
       "RUN rm -f $SC_PREFIX/Makefile $SC_PREFIX/README.md",
@@ -91,13 +91,12 @@
   },
   "yosys": {
     "git-url": "https://github.com/YosysHQ/yosys.git",
-    "git-commit": "0.46",
+    "git-commit": "0.47",
     "version-prefix": "",
     "auto-update": true
   },
   "xyce": {
-    "git-url": "https://github.com/Xyce/Xyce.git",
-    "version": "7.8.0",
+    "version": "7.8",
     "auto-update": false
   },
   "xdm": {

siliconcompiler/toolscripts/rhel8/install-xyce.sh

@@ -20,17 +20,16 @@ sudo yum install -y gcc gcc-c++ gcc-gfortran blas blas-devel \
     git
 sudo dnf config-manager --set-disabled devel || true
 
-# Download Trilinos
+# Download Trilinos.
 ## Version specified in: https://github.com/Xyce/Xyce/blob/master/INSTALL.md#building-trilinos
 trilinos_version=14-4-0
-wget https://github.com/trilinos/Trilinos/archive/refs/tags/trilinos-release-${trilinos_version}.tar.gz -O trilinos.tar.gz
+wget https://github.com/trilinos/Trilinos/archive/refs/tags/trilinos-release-${trilinos_version}.tar.gz --no-verbose -O trilinos.tar.gz
 mkdir -p trilinos
 tar --strip-components=1 -xf trilinos.tar.gz -C trilinos
-rm trilinos.tar.gz
 
-# Download Xyce (note that this is needed to build Trilinos)
+# Download Xyce.
 xyce_version=$(python3 ${src_path}/_tools.py --tool xyce --field version)
-wget https://github.com/Xyce/Xyce/archive/refs/tags/Release-${xyce_version}.tar.gz -O xyce.tar.gz
+wget https://xyce.sandia.gov/files/xyce/Xyce-${xyce_version}.tar.gz --no-verbose -O xyce.tar.gz
 mkdir -p xyce
 tar --strip-components=1 -xf xyce.tar.gz -C xyce
 rm xyce.tar.gz

siliconcompiler/toolscripts/rhel9/install-xyce.sh

@@ -20,17 +20,16 @@ sudo yum install -y gcc gcc-c++ gcc-gfortran blas blas-devel \
     git
 sudo dnf config-manager --set-disabled devel || true
 
-# Download Trilinos
+# Download Trilinos.
 ## Version specified in: https://github.com/Xyce/Xyce/blob/master/INSTALL.md#building-trilinos
 trilinos_version=14-4-0
-wget https://github.com/trilinos/Trilinos/archive/refs/tags/trilinos-release-${trilinos_version}.tar.gz -O trilinos.tar.gz
+wget https://github.com/trilinos/Trilinos/archive/refs/tags/trilinos-release-${trilinos_version}.tar.gz --no-verbose -O trilinos.tar.gz
 mkdir -p trilinos
 tar --strip-components=1 -xf trilinos.tar.gz -C trilinos
-rm trilinos.tar.gz
 
-# Download Xyce (note that this is needed to build Trilinos)
+# Download Xyce.
 xyce_version=$(python3 ${src_path}/_tools.py --tool xyce --field version)
-wget https://github.com/Xyce/Xyce/archive/refs/tags/Release-${xyce_version}.tar.gz -O xyce.tar.gz
+wget https://xyce.sandia.gov/files/xyce/Xyce-${xyce_version}.tar.gz --no-verbose -O xyce.tar.gz
 mkdir -p xyce
 tar --strip-components=1 -xf xyce.tar.gz -C xyce
 rm xyce.tar.gz

siliconcompiler/toolscripts/ubuntu20/install-xyce.sh

@@ -20,20 +20,20 @@ fi
 # Install CMAKE
 python3 -m venv .xyce --clear
 . .xyce/bin/activate
-python3 -m pip install cmake
+python3 -m pip install cmake>=3.23.0
 
 # Download Trilinos.
 ## Version specified in: https://github.com/Xyce/Xyce/blob/master/INSTALL.md#building-trilinos
 trilinos_version=14-4-0
-wget https://github.com/trilinos/Trilinos/archive/refs/tags/trilinos-release-${trilinos_version}.tar.gz -O trilinos.tar.gz
+wget https://github.com/trilinos/Trilinos/archive/refs/tags/trilinos-release-${trilinos_version}.tar.gz --no-verbose -O trilinos.tar.gz
 mkdir -p trilinos
-tar --strip-components=1 -xvf trilinos.tar.gz -C trilinos
+tar --strip-components=1 -xf trilinos.tar.gz -C trilinos
 
 # Download Xyce.
 xyce_version=$(python3 ${src_path}/_tools.py --tool xyce --field version)
-wget https://github.com/Xyce/Xyce/archive/refs/tags/Release-${xyce_version}.tar.gz -O xyce.tar.gz
+wget https://xyce.sandia.gov/files/xyce/Xyce-${xyce_version}.tar.gz --no-verbose -O xyce.tar.gz
 mkdir -p xyce
-tar --strip-components=1 -xvf xyce.tar.gz -C xyce
+tar --strip-components=1 -xf xyce.tar.gz -C xyce
 
 cd xyce
 

siliconcompiler/toolscripts/ubuntu22/install-xyce.sh

@@ -25,13 +25,13 @@ python3 -m pip install cmake>=3.23.0
 # Download Trilinos.
 ## Version specified in: https://github.com/Xyce/Xyce/blob/master/INSTALL.md#building-trilinos
 trilinos_version=14-4-0
-wget https://github.com/trilinos/Trilinos/archive/refs/tags/trilinos-release-${trilinos_version}.tar.gz -O trilinos.tar.gz
+wget https://github.com/trilinos/Trilinos/archive/refs/tags/trilinos-release-${trilinos_version}.tar.gz --no-verbose -O trilinos.tar.gz
 mkdir -p trilinos
 tar --strip-components=1 -xf trilinos.tar.gz -C trilinos
 
 # Download Xyce.
 xyce_version=$(python3 ${src_path}/_tools.py --tool xyce --field version)
-wget https://github.com/Xyce/Xyce/archive/refs/tags/Release-${xyce_version}.tar.gz -O xyce.tar.gz
+wget https://xyce.sandia.gov/files/xyce/Xyce-${xyce_version}.tar.gz --no-verbose -O xyce.tar.gz
 mkdir -p xyce
 tar --strip-components=1 -xf xyce.tar.gz -C xyce
 

siliconcompiler/toolscripts/ubuntu24/install-xyce.sh

@@ -25,13 +25,13 @@ python3 -m pip install cmake>=3.23.0
 # Download Trilinos.
 ## Version specified in: https://github.com/Xyce/Xyce/blob/master/INSTALL.md#building-trilinos
 trilinos_version=14-4-0
-wget https://github.com/trilinos/Trilinos/archive/refs/tags/trilinos-release-${trilinos_version}.tar.gz -O trilinos.tar.gz
+wget https://github.com/trilinos/Trilinos/archive/refs/tags/trilinos-release-${trilinos_version}.tar.gz --no-verbose -O trilinos.tar.gz
 mkdir -p trilinos
 tar --strip-components=1 -xf trilinos.tar.gz -C trilinos
 
 # Download Xyce.
 xyce_version=$(python3 ${src_path}/_tools.py --tool xyce --field version)
-wget https://github.com/Xyce/Xyce/archive/refs/tags/Release-${xyce_version}.tar.gz -O xyce.tar.gz
+wget https://xyce.sandia.gov/files/xyce/Xyce-${xyce_version}.tar.gz --no-verbose -O xyce.tar.gz
 mkdir -p xyce
 tar --strip-components=1 -xf xyce.tar.gz -C xyce
 

{siliconcompiler-0.28.4.dist-info → siliconcompiler-0.28.5.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: siliconcompiler
-Version: 0.28.4
+Version: 0.28.5
 Summary: A compiler framework that automates translation from source code to silicon.
 Author-email: Andreas Olofsson <andreas.d.olofsson@gmail.com>
 License: Apache License 2.0
@@ -36,14 +36,14 @@ Requires-Dist: packaging <24,>=21.3
 Requires-Dist: psutil >=5.8.0
 Requires-Dist: Pillow ==10.4.0
 Requires-Dist: GitPython ==3.1.43
-Requires-Dist: lambdapdk >=0.1.34
+Requires-Dist: lambdapdk >=0.1.38
 Requires-Dist: PyGithub ==2.4.0
 Requires-Dist: urllib3 >=1.26.0
 Requires-Dist: fasteners ==0.19
 Requires-Dist: fastjsonschema ==2.20.0
 Requires-Dist: docker ==7.1.0
 Requires-Dist: sc-surelog ==1.84.1
-Requires-Dist: orjson ==3.10.10
+Requires-Dist: orjson ==3.10.11
 Requires-Dist: streamlit ==1.39.0
 Requires-Dist: streamlit-agraph ==0.0.45
 Requires-Dist: streamlit-antd-components ==0.3.2
@@ -57,7 +57,7 @@ Requires-Dist: pydata-sphinx-theme ==0.16.0 ; extra == 'docs'
 Requires-Dist: sc-leflib >=0.2.0 ; extra == 'docs'
 Provides-Extra: examples
 Requires-Dist: migen ==0.9.2 ; extra == 'examples'
-Requires-Dist: lambdalib ==0.2.10 ; extra == 'examples'
+Requires-Dist: lambdalib ==0.3.0 ; extra == 'examples'
 Provides-Extra: profile
 Requires-Dist: gprof2dot ==2024.6.6 ; extra == 'profile'
 Provides-Extra: test