siliconcompiler 0.28.4__py3-none-any.whl → 0.28.5__py3-none-any.whl

siliconcompiler/schema/schema_obj.py

@@ -61,6 +61,8 @@ class Schema:
         logger (logging.Logger): instance of the parent logger if available
     """
 
+    _RECORD_ACCESS_IDENTIFIER = "SC_CFG_ACCESS_KEY"
+
     # Special key in node dict that represents a value corresponds to a
     # global default for all steps/indices.
     GLOBAL_KEY = 'global'
@@ -70,6 +72,9 @@ class Schema:
         if cfg is not None and manifest is not None:
             raise ValueError('You may not specify both cfg and manifest')
 
+        # Use during testing to record calls to Schema.get
+        self._init_record_access()
+
         self._init_logger(logger)
 
         self._stop_journal()
@@ -256,6 +261,10 @@ class Schema:
 
         See :meth:`~siliconcompiler.core.Chip.get` for detailed documentation.
         """
+
+        if self.__record_access["recording"]:
+            self.__record_access["record"].add(tuple(keypath))
+
         # Prevent accidental modifications of the schema content by not passing a reference
         return copy.copy(self.__get(*keypath, field=field, job=job, step=step, index=index))
 
@@ -1087,7 +1096,9 @@ class Schema:
 
         if template:
             fout.write(template.render(manifest_dict='\n'.join(tcl_set_cmds),
-                                       scroot=os.path.abspath(PACKAGE_ROOT)))
+                                       scroot=os.path.abspath(PACKAGE_ROOT),
+                                       record_access=self._do_record_access(),
+                                       record_access_id=Schema._RECORD_ACCESS_IDENTIFIER))
         else:
             for cmd in tcl_set_cmds:
                 fout.write(cmd + '\n')
@@ -1305,6 +1316,45 @@ class Schema:
             except Exception as e:
                 self.logger.error(f'Exception: {e}')
 
+    #######################################
+    def _do_record_access(self):
+        '''
+        Determine if Schema should record calls to .get
+        '''
+        return False
+
+    #######################################
+    def _init_record_access(self):
+        '''
+        Initialize record access data record
+        '''
+        self.__record_access = {
+            "do": self._do_record_access(),
+            "recording": False,
+            "record": set()
+        }
+
+    #######################################
+    def _start_record_access(self):
+        '''
+        Start recording calls to .get
+        '''
+        self.__record_access["recording"] = True
+
+    #######################################
+    def _stop_record_access(self):
+        '''
+        Stop recording calls to .get
+        '''
+        self.__record_access["recording"] = False
+
+    #######################################
+    def _get_record_access(self):
+        '''
+        Return calls to record_access
+        '''
+        return self.__record_access["record"].copy()
+
     #######################################
     def get_default(self, *keypath):
         '''Returns default value of a parameter.

siliconcompiler/targets/interposer_demo.py

@@ -0,0 +1,56 @@
+from siliconcompiler import Chip
+from siliconcompiler.flows import interposerflow, drcflow
+
+from lambdapdk import interposer
+from lambdapdk.interposer.libs import bumps
+
+
+####################################################
+# Target Setup
+####################################################
+def setup(chip):
+    '''
+    Interposer Demo Target
+    '''
+
+    # 1. Load PDK, flow, libs
+    chip.use(interposer)
+    chip.use(bumps)
+    chip.use(interposerflow)
+    chip.use(drcflow)
+
+    # 2. Set default targets
+    chip.set('option', 'flow', 'interposerflow', clobber=False)
+    chip.set('option', 'pdk', 'interposer', clobber=False)
+    chip.set('option', 'stackup', '3ML_0400', clobber=False)
+    chip.set('option', 'var', 'openroad_libtype', 'none', clobber=False)
+    chip.set('option', 'var', 'klayout_libtype', 'none', clobber=False)
+
+    # 3. Set project specific design choices
+    chip.set('asic', 'macrolib', 'interposer_bumps', clobber=False)
+
+    # 4. get project specific design choices
+    chip.set('asic', 'delaymodel', 'nldm', clobber=False)
+
+    # 5. Timing corners
+    chip.set('constraint', 'timing', 'slow', 'libcorner', 'slow', clobber=False)
+    chip.set('constraint', 'timing', 'slow', 'pexcorner', 'maximum', clobber=False)
+    chip.set('constraint', 'timing', 'slow', 'mode', 'func', clobber=False)
+    chip.set('constraint', 'timing', 'slow', 'check', ['setup', 'hold'], clobber=False)
+
+    chip.set('constraint', 'timing', 'fast', 'libcorner', 'fast', clobber=False)
+    chip.set('constraint', 'timing', 'fast', 'pexcorner', 'minimum', clobber=False)
+    chip.set('constraint', 'timing', 'fast', 'mode', 'func', clobber=False)
+    chip.set('constraint', 'timing', 'fast', 'check', ['setup', 'hold'], clobber=False)
+
+    chip.set('constraint', 'timing', 'typical', 'libcorner', 'typ', clobber=False)
+    chip.set('constraint', 'timing', 'typical', 'pexcorner', 'typical', clobber=False)
+    chip.set('constraint', 'timing', 'typical', 'mode', 'func', clobber=False)
+    chip.set('constraint', 'timing', 'typical', 'check', ['setup', 'hold'], clobber=False)
+
+
+#########################
+if __name__ == "__main__":
+    target = Chip('<target>')
+    setup(target)
+    target.write_manifest('interposer_demo.json')

siliconcompiler/templates/tcl/manifest.tcl.j2

@@ -16,6 +16,8 @@ proc sc_cfg_get { args } {
     # Refer to global sc_cfg dictionary
     global sc_cfg
 
+    {% if record_access %}puts "{{ record_access_id }} [join $args ,]"{% endif %}
+
     if { ![sc_cfg_exists {*}$args] } {
         throw {FLOW KEYERROR} "key \"$args\" is not in the siliconcompiler configuration"
     }

siliconcompiler/tools/klayout/export.py

@@ -41,11 +41,9 @@ def setup(chip):
                               step=step, index=index)[0]
     sc_stream_order = [default_stream, *[s for s in streams if s != default_stream]]
 
-    if stackup and targetlibs:
+    if stackup:
         macrolibs = get_libraries(chip, 'macro')
 
-        chip.add('tool', tool, 'task', task, 'require', ",".join(['asic', 'logiclib']),
-                 step=step, index=index)
         chip.add('tool', tool, 'task', task, 'require', ",".join(['option', 'stackup']),
                  step=step, index=index)
         req_set = False
@@ -83,7 +81,12 @@ def setup(chip):
                      ",".join(['library', lib, 'output', stackup, 'lef']),
                      step=step, index=index)
     else:
-        chip.error('Stackup and targetlib parameters required for Klayout.')
+        chip.error('Stackup parameter required for Klayout.')
+
+    if not targetlibs:
+        chip.add('tool', tool, 'task', task, 'require',
+                 'option,var,klayout_libtype',
+                 step=step, index=index)
 
     # Input/Output requirements for default flow
     design = chip.top()

siliconcompiler/tools/klayout/klayout_export.py

@@ -61,6 +61,9 @@ def gds_export(design_name, in_def, in_files, out_file, tech, allow_missing, con
     for cell in def_cells:
         print(f"  [INFO] DEF cell: {cell}")
 
+    if f"{design_name}_DEF_FILL" in def_cells:
+        def_cells.remove(f"{design_name}_DEF_FILL")
+
     # Load in the gds to merge
     print("[INFO] Merging GDS/OAS files...")
     for fil in in_files:

siliconcompiler/tools/klayout/klayout_utils.py

@@ -31,8 +31,14 @@ def technology(design, schema):
         sc_stackup = schema.get('option', 'stackup')
     else:
         sc_stackup = schema.get('pdk', sc_pdk, 'stackup')[0]
-    sc_mainlib = schema.get('asic', 'logiclib', step=sc_step, index=sc_index)[0]
-    sc_libtype = schema.get('library', sc_mainlib, 'asic', 'libarch', step=sc_step, index=sc_index)
+
+    logiclibs = schema.get('asic', 'logiclib', step=sc_step, index=sc_index)
+    if not logiclibs:
+        sc_libtype = schema.get('option', 'var', 'klayout_libtype')[0]
+    else:
+        sc_mainlib = logiclibs[0]
+        sc_libtype = schema.get('library', sc_mainlib, 'asic', 'libarch',
+                                step=sc_step, index=sc_index)
 
     sc_libs = []
     sc_libs += get_libraries(schema, 'logic')

siliconcompiler/tools/openroad/metrics.py

@@ -0,0 +1,45 @@
+
+from siliconcompiler.tools.openroad.openroad import setup as setup_tool
+from siliconcompiler.tools.openroad.openroad import build_pex_corners
+from siliconcompiler.tools.openroad.openroad import post_process as or_post_process
+from siliconcompiler.tools.openroad.openroad import pre_process as or_pre_process
+from siliconcompiler.tools.openroad.openroad import _set_reports, set_pnr_inputs, set_pnr_outputs
+
+
+def setup(chip):
+    '''
+    Extract metrics
+    '''
+
+    # Generic tool setup.
+    setup_tool(chip)
+
+    set_pnr_inputs(chip)
+    set_pnr_outputs(chip)
+
+    _set_reports(chip, [
+        'setup',
+        'hold',
+        'unconstrained',
+        'clock_skew',
+        'power',
+        'drv_violations',
+        'fmax',
+
+        # Images
+        'placement_density',
+        'routing_congestion',
+        'power_density',
+        'clock_placement',
+        'clock_trees',
+        'optimization_placement'
+    ])
+
+
+def pre_process(chip):
+    or_pre_process(chip)
+    build_pex_corners(chip)
+
+
+def post_process(chip):
+    or_post_process(chip)

siliconcompiler/tools/openroad/openroad.py

@@ -326,6 +326,9 @@ def post_process(chip):
             ('vias', 'sc__step__route__vias', True, None),
             ('wirelength', 'sc__step__route__wirelength', True, 'distance'),
             ('cellarea', 'sc__metric__design__instance__area', True, 'area'),
+            ('stdcellarea', 'sc__metric__design__instance__area__stdcell', True, 'area'),
+            ('macroarea', 'sc__metric__design__instance__area__macros', True, 'area'),
+            ('padcellarea', 'sc__metric__design__instance__area__padcells', True, 'area'),
             ('totalarea', 'sc__metric__design__core__area', True, 'area'),
             ('utilization', 'sc__metric__design__instance__utilization', True, 100.0),
             ('setuptns', 'sc__metric__timing__setup__tns', has_timing, 'time'),

siliconcompiler/tools/openroad/rdlroute.py

@@ -0,0 +1,97 @@
+import os
+
+from siliconcompiler.tools._common import input_provides, get_tool_task
+from siliconcompiler.tools._common.asic import set_tool_task_var
+from siliconcompiler.tools.openroad.openroad import build_pex_corners
+from siliconcompiler.tools.openroad.openroad import post_process as or_post_process
+
+
+def setup(chip):
+    '''
+    Perform floorplanning, pin placements, macro placements and power grid generation
+    '''
+
+    # Generic tool setup.
+    # default tool settings, note, not additive!
+
+    tool = 'openroad'
+    script = 'sc_rdlroute.tcl'
+    refdir = os.path.join('tools', tool, 'scripts')
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    design = chip.top()
+
+    chip.set('tool', tool, 'exe', tool)
+    chip.set('tool', tool, 'vswitch', '-version')
+    chip.set('tool', tool, 'version', '>=v2.0-16839')
+    chip.set('tool', tool, 'format', 'tcl')
+
+    # exit automatically in batch mode and not breakpoint
+    option = ''
+    if exit and not chip.get('option', 'breakpoint', step=step, index=index):
+        option += " -exit"
+
+    option += " -metrics reports/metrics.json"
+    chip.set('tool', tool, 'task', task, 'option', option, step=step, index=index)
+
+    # Input/Output requirements for default asicflow steps
+
+    chip.set('tool', tool, 'task', task, 'refdir', refdir,
+             step=step, index=index,
+             package='siliconcompiler')
+    chip.set('tool', tool, 'task', task, 'script', script,
+             step=step, index=index)
+    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+             step=step, index=index, clobber=False)
+
+    if chip.get('option', 'nodisplay'):
+        # Tells QT to use the offscreen platform if nodisplay is used
+        chip.set('tool', tool, 'task', task, 'env', 'QT_QPA_PLATFORM', 'offscreen',
+                 step=step, index=index)
+
+    # basic warning and error grep check on logfile
+    chip.set('tool', tool, 'task', task, 'regex', 'warnings', r'^\[WARNING|^Warning',
+             step=step, index=index, clobber=False)
+    chip.set('tool', tool, 'task', task, 'regex', 'errors', r'^\[ERROR',
+             step=step, index=index, clobber=False)
+
+    chip.add('tool', tool, 'task', task, 'require',
+             'option,var,openroad_libtype',
+             step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'require',
+             ','.join(['tool', tool, 'task', task, 'file', 'rdlroute']),
+             step=step, index=index)
+    chip.set('tool', tool, 'task', task, 'file', 'rdlroute',
+             'script to perform rdl route',
+             field='help')
+
+    set_tool_task_var(chip, param_key='fin_add_fill',
+                      default_value='false',
+                      schelp='true/false, when true enables adding fill, '
+                             'if enabled by the PDK, to the design',
+                      skip='lib')
+
+    if f'{design}.v' in input_provides(chip, step, index):
+        chip.add('tool', tool, 'task', task, 'input', design + '.v', step=step, index=index)
+    elif f'{design}.vg' in input_provides(chip, step, index):
+        chip.add('tool', tool, 'task', task, 'input', design + '.vg', step=step, index=index)
+    else:
+        chip.add('tool', tool, 'task', task, 'require',
+                 ','.join(['input', 'netlist', 'verilog']),
+                 step=step, index=index)
+
+    chip.add('tool', tool, 'task', task, 'output', design + '.sdc', step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', design + '.vg', step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', design + '.def', step=step, index=index)
+    chip.add('tool', tool, 'task', task, 'output', design + '.odb', step=step, index=index)
+
+
+def pre_process(chip):
+    build_pex_corners(chip)
+
+
+def post_process(chip):
+    or_post_process(chip)

siliconcompiler/tools/openroad/scripts/sc_apr.tcl

@@ -504,7 +504,7 @@ if { $sc_task == "show" || $sc_task == "screenshot" } {
   ###############################
 
   utl::push_metrics_stage "sc__metric__{}"
-  source "$sc_refdir/sc_metrics.tcl"
+  source "$sc_refdir/sc_report.tcl"
   utl::pop_metrics_stage
 
   # Images

siliconcompiler/tools/openroad/scripts/sc_metrics.tcl

@@ -1,170 +1 @@
-###############################
-# Report Metrics
-###############################
 
-proc sc_display_report { report } {
-  if { ![file exists $report] } {
-    return
-  }
-  set fid [open $report r]
-  set report_content [read $fid]
-  close $fid
-  puts $report_content
-}
-
-set fields "{capacitance slew input_pins nets fanout}"
-set PREFIX "SC_METRIC:"
-
-if { [sc_cfg_tool_task_check_in_list setup var reports] } {
-  puts "$PREFIX report_checks -path_delay max"
-  report_checks -fields $fields -path_delay max -format full_clock_expanded \
-    > reports/timing/setup.rpt
-  sc_display_report reports/timing/setup.rpt
-  report_checks -path_delay max -group_count $openroad_sta_top_n_paths \
-    > reports/timing/setup.topN.rpt
-
-  puts "$PREFIX setupslack"
-  report_worst_slack -max > reports/timing/worst_slack.setup.rpt
-  sc_display_report reports/timing/worst_slack.setup.rpt
-  report_worst_slack_metric -setup
-
-  puts "$PREFIX tns"
-  report_tns > reports/timing/total_negative_slack.rpt
-  sc_display_report reports/timing/total_negative_slack.rpt
-  report_tns_metric -setup
-}
-
-if { [sc_cfg_tool_task_check_in_list hold var reports] } {
-  puts "$PREFIX report_checks -path_delay min"
-  report_checks -fields $fields -path_delay min -format full_clock_expanded \
-    > reports/timing/hold.rpt
-  sc_display_report reports/timing/hold.rpt
-  report_checks -path_delay min -group_count $openroad_sta_top_n_paths \
-    > reports/timing/hold.topN.rpt
-
-  puts "$PREFIX holdslack"
-  report_worst_slack -min > reports/timing/worst_slack.hold.rpt
-  sc_display_report reports/timing/worst_slack.hold.rpt
-  report_worst_slack_metric -hold
-
-  report_tns_metric -hold
-}
-
-if { [sc_cfg_tool_task_check_in_list unconstrained var reports] } {
-  puts "$PREFIX unconstrained"
-  report_checks -fields $fields -unconstrained -format full_clock_expanded \
-    > reports/timing/unconstrained.rpt
-  sc_display_report reports/timing/unconstrained.rpt
-  report_checks -unconstrained -group_count $openroad_sta_top_n_paths \
-    > reports/timing/unconstrained.topN.rpt
-}
-
-if {
-  [sc_cfg_tool_task_check_in_list clock_skew var reports] &&
-  [llength [all_clocks]] > 0
-} {
-  puts "$PREFIX clock_skew"
-  report_clock_skew -setup -digits 4 > reports/timing/skew.setup.rpt
-  sc_display_report reports/timing/skew.setup.rpt
-  report_clock_skew_metric -setup
-  report_clock_skew -hold -digits 4 > reports/timing/skew.hold.rpt
-  sc_display_report reports/timing/skew.hold.rpt
-  report_clock_skew_metric -hold
-}
-
-if { [sc_cfg_tool_task_check_in_list drv_violations var reports] } {
-  puts "$PREFIX DRV violators"
-  report_check_types -max_slew -max_capacitance -max_fanout -violators \
-    > reports/timing/drv_violators.rpt
-  sc_display_report reports/timing/drv_violators.rpt
-  report_erc_metrics
-
-  puts "$PREFIX floating nets"
-  report_floating_nets -verbose > reports/floating_nets.rpt
-  sc_display_report reports/floating_nets.rpt
-}
-
-utl::metric_int "timing__clocks" [llength [all_clocks]]
-
-if { [sc_cfg_tool_task_check_in_list fmax var reports] } {
-  puts "$PREFIX fmax"
-  # Model on: https://github.com/The-OpenROAD-Project/OpenSTA/blob/f913c3ddbb3e7b4364ed4437c65ac78c4da9174b/tcl/Search.tcl#L1078
-  set fmax_metric 0
-  foreach clk [sta::sort_by_name [all_clocks]] {
-    set clk_name [get_name $clk]
-    set min_period [sta::find_clk_min_period $clk 1]
-    if { $min_period == 0.0 } {
-      continue
-    }
-    set fmax [expr { 1.0 / $min_period }]
-    utl::metric_float "timing__fmax__clock:${clk_name}" $fmax
-    puts "$clk_name fmax = [format %.2f [expr { $fmax / 1e6 }]] MHz"
-    set fmax_metric [expr { max($fmax_metric, $fmax) }]
-  }
-  if { $fmax_metric > 0 } {
-    utl::metric_float "timing__fmax" $fmax_metric
-  }
-}
-
-# get logic depth of design
-utl::metric_int "design__logic__depth" [count_logic_depth]
-
-if { [sc_cfg_tool_task_check_in_list power var reports] } {
-  puts "$PREFIX power"
-  foreach corner [sta::corners] {
-    set corner_name [$corner name]
-    puts "Power for corner: $corner_name"
-    report_power -corner $corner_name > reports/power/${corner_name}.rpt
-    sc_display_report reports/power/${corner_name}.rpt
-  }
-  report_power_metric -corner $sc_power_corner
-}
-
-puts "$PREFIX cellarea"
-report_design_area
-report_design_area_metrics
-
-# get number of nets in design
-utl::metric_int "design__nets" [llength [[ord::get_db_block] getNets]]
-
-# get number of registers
-utl::metric_int "design__registers" [llength [all_registers]]
-
-# get number of buffers
-set bufs 0
-set invs 0
-foreach inst [get_cells -hierarchical *] {
-  set cell [$inst cell]
-  if { $cell == "NULL" } {
-    continue
-  }
-  set liberty_cell [$cell liberty_cell]
-  if { $liberty_cell == "NULL" } {
-    continue
-  }
-  if { [$liberty_cell is_buffer] } {
-    incr bufs
-  } elseif { [$liberty_cell is_inverter] } {
-    incr invs
-  }
-}
-utl::metric_int "design__buffers" $bufs
-utl::metric_int "design__inverters" $invs
-
-# get number of unconstrained endpoints
-with_output_to_variable endpoints {check_setup -unconstrained_endpoints}
-set unconstrained_endpoints [regexp -all -inline {[0-9]+} $endpoints]
-if { $unconstrained_endpoints == "" } {
-  set unconstrained_endpoints 0
-}
-utl::metric_int "timing__unconstrained" $unconstrained_endpoints
-
-# Write markers
-foreach markerdb [[ord::get_db_block] getMarkerCategories] {
-  if { [$markerdb getMarkerCount] == 0 } {
-    continue
-  }
-
-  $markerdb writeTR "reports/markers/${sc_design}.[$markerdb getName].rpt"
-  $markerdb writeJSON "reports/markers/${sc_design}.[$markerdb getName].json"
-}