siliconcompiler 0.28.3__py3-none-any.whl → 0.28.4__py3-none-any.whl

siliconcompiler/tools/yosys/sc_screenshot.tcl

@@ -0,0 +1,104 @@
+###############################
+# Reading SC Schema
+###############################
+
+source ./sc_manifest.tcl
+
+yosys echo on
+
+###############################
+# Schema Adapter
+###############################
+
+set sc_tool yosys
+set sc_step [sc_cfg_get arg step]
+set sc_index [sc_cfg_get arg index]
+set sc_flow [sc_cfg_get option flow]
+set sc_task [sc_cfg_get flowgraph $sc_flow $sc_step $sc_index task]
+set sc_refdir [sc_cfg_tool_task_get refdir]
+
+####################
+# DESIGNER's CHOICE
+####################
+
+set sc_design [sc_top]
+
+########################################################
+# Helper function
+########################################################
+
+source "$sc_refdir/procs.tcl"
+
+########################################################
+# Design Inputs
+########################################################
+
+if { [file exists "inputs/$sc_design.v"] } {
+    set input_verilog "inputs/$sc_design.v"
+    yosys read_verilog -noblackbox -sv $input_verilog
+    set file_type "v"
+} elseif { [file exists "inputs/$sc_design.vg"] } {
+    set input_verilog "inputs/$sc_design.vg"
+    yosys read_verilog -noblackbox -sv $input_verilog
+    set file_type "vg"
+} elseif { [sc_cfg_tool_task_exists var show_filepath] } {
+    yosys read_verilog -noblackbox -sv [sc_cfg_tool_task_get var show_filepath]
+    set file_type [lindex [sc_cfg_tool_task_get var show_filetype] 0]
+}
+
+########################################################
+# Override top level parameters
+########################################################
+
+sc_apply_params
+
+########################################################
+# Read Libraries
+########################################################
+
+set sc_logiclibs [sc_get_asic_libraries logic]
+set sc_macrolibs [sc_get_asic_libraries macro]
+
+set sc_libraries [sc_cfg_tool_task_get {file} synthesis_libraries]
+if { [sc_cfg_tool_task_exists {file} synthesis_libraries_macros] } {
+    set sc_macro_libraries \
+        [sc_cfg_tool_task_get {file} synthesis_libraries_macros]
+} else {
+    set sc_macro_libraries []
+}
+
+set sc_blackboxes []
+foreach lib $sc_macrolibs {
+    if { [sc_cfg_exists library $lib output blackbox verilog] } {
+        foreach lib_f [sc_cfg_get library $lib output blackbox verilog] {
+            lappend sc_blackboxes $lib_f
+        }
+    }
+}
+
+foreach lib_file "$sc_libraries $sc_macro_libraries" {
+    yosys read_liberty -lib $lib_file
+}
+foreach bb_file $sc_blackboxes {
+    yosys log "Reading blackbox model file: $bb_file"
+    yosys read_verilog -sv $bb_file
+}
+
+########################################################
+# Screenshot
+########################################################
+
+yosys hierarchy -top $sc_design
+
+if { $file_type == "v" } {
+    yosys proc
+}
+
+yosys show \
+    -nobg \
+    -format png \
+    -width \
+    -signed \
+    -stretch \
+    -prefix outputs/${sc_design} \
+    $sc_design

siliconcompiler/tools/yosys/sc_syn.tcl

@@ -26,6 +26,12 @@ set sc_flow [sc_cfg_get option flow]
 set sc_optmode [sc_cfg_get option optmode]
 set sc_pdk [sc_cfg_get option pdk]
 
+########################################################
+# Helper function
+########################################################
+
+source "$sc_refdir/procs.tcl"
+
 ########################################################
 # Design Inputs
 ########################################################
@@ -57,15 +63,7 @@ if { [file exists "inputs/$sc_design.v"] } {
 # Override top level parameters
 ########################################################
 
-yosys chparam -list
-if { [sc_cfg_exists option param] } {
-    dict for {key value} [sc_cfg_get option param] {
-        if { ![string is integer $value] } {
-            set value [concat \"$value\"]
-        }
-        yosys chparam -set $key $value $sc_design
-    }
-}
+sc_apply_params
 
 ########################################################
 # Synthesis based on mode

siliconcompiler/tools/yosys/screenshot.py

@@ -0,0 +1,153 @@
+from siliconcompiler.tools.yosys.yosys import setup as tool_setup
+import os
+import siliconcompiler.tools.yosys.prepareLib as prepareLib
+from siliconcompiler.tools._common.asic import get_libraries
+from siliconcompiler.tools._common import get_tool_task
+from siliconcompiler.targets import asap7_demo
+
+
+def make_docs(chip):
+    chip.use(asap7_demo)
+
+
+def setup(chip):
+    '''
+    Generate a screenshot of the design
+    '''
+
+    # Generic tool setup.
+    tool_setup(chip)
+
+    # ASIC-specific setup.
+    # setup_asic(chip)
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+    chip.set('tool', tool, 'task', task, 'input', [], step=step, index=index)
+    chip.set('tool', tool, 'task', task, 'script', 'sc_screenshot.tcl',
+             step=step, index=index)
+
+    design = chip.top()
+    chip.set('tool', tool, 'task', task, 'output', [design + '.dot', design + '.png'],
+             step=step, index=index)
+
+
+################################
+# format liberty files for yosys
+################################
+def prepare_asic_libraries(chip):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    # Clear in case of rerun
+    for libtype in ('synthesis_libraries', 'synthesis_libraries_macros'):
+        chip.set('tool', tool, 'task', task, 'file', libtype, [],
+                 step=step, index=index)
+
+    # Generate synthesis_libraries and synthesis_macro_libraries for Yosys use
+
+    # mark libs with dont_use since ABC cannot get this information via its commands
+    # this also ensures the liberty files have been decompressed and corrected formatting
+    # issues that generally cannot be handled by yosys or yosys-abc
+    def get_synthesis_libraries(lib):
+        keypath = _get_synthesis_library_key(chip, lib)
+        if keypath and chip.valid(*keypath):
+            return chip.find_files(*keypath, step=step, index=index)
+        return []
+
+    for libtype in ('logic', 'macro'):
+        for lib in get_libraries(chip, libtype):
+            lib_content = {}
+            # Mark dont use
+            for lib_file in get_synthesis_libraries(lib):
+                # Ensure a unique name is used for library
+                lib_file_name_base = os.path.basename(lib_file)
+                if lib_file_name_base.lower().endswith('.gz'):
+                    lib_file_name_base = lib_file_name_base[0:-3]
+                if lib_file_name_base.lower().endswith('.lib'):
+                    lib_file_name_base = lib_file_name_base[0:-4]
+
+                lib_file_name = lib_file_name_base
+                unique_ident = 0
+                while lib_file_name in lib_content:
+                    lib_file_name = f'{lib_file_name_base}_{unique_ident}'
+                    unique_ident += 1
+
+                lib_content[lib_file_name] = prepareLib.processLibertyFile(
+                        lib_file,
+                        logger=None if chip.get('option', 'quiet',
+                                                step=step, index=index) else chip.logger)
+
+            if not lib_content:
+                continue
+
+            var_name = 'synthesis_libraries'
+            if libtype == "macro":
+                var_name = 'synthesis_libraries_macros'
+
+            for file, content in lib_content.items():
+                output_file = os.path.join(
+                    chip.getworkdir(step=step, index=index),
+                    'inputs',
+                    f'sc_{libtype}_{lib}_{file}.lib'
+                )
+
+                with open(output_file, 'w') as f:
+                    f.write(content)
+
+                chip.add('tool', tool, 'task', task, 'file', var_name, output_file,
+                         step=step, index=index)
+
+
+def get_synthesis_corner(chip):
+    tool = 'yosys'
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    _, task = get_tool_task(chip, step, index)
+
+    syn_corners = chip.get('tool', tool, 'task', task, 'var', 'synthesis_corner',
+                           step=step, index=index)
+    if syn_corners:
+        return syn_corners
+
+    # determine corner based on setup corner from constraints
+    corner = None
+    for constraint in chip.getkeys('constraint', 'timing'):
+        checks = chip.get('constraint', 'timing', constraint, 'check', step=step, index=index)
+        if "setup" in checks and not corner:
+            corner = chip.get('constraint', 'timing', constraint, 'libcorner',
+                              step=step, index=index)
+
+    if not corner:
+        # try getting it from first constraint with a valid libcorner
+        for constraint in chip.getkeys('constraint', 'timing'):
+            if not corner:
+                corner = chip.get('constraint', 'timing', constraint, 'libcorner',
+                                  step=step, index=index)
+
+    return corner
+
+
+def _get_synthesis_library_key(chip, lib):
+    if chip.valid('library', lib, 'option', 'file', 'yosys_synthesis_libraries'):
+        return ('library', lib, 'option', 'file', 'yosys_synthesis_libraries')
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    delaymodel = chip.get('asic', 'delaymodel', step=step, index=index)
+
+    for corner in chip.getkeys('library', lib, 'output'):
+        if chip.valid('library', lib, 'output', corner, delaymodel):
+            return ('library', lib, 'output', corner, delaymodel)
+
+    return None
+
+
+##################################################
+def pre_process(chip):
+    ''' Tool specific function to run before step execution
+    '''
+
+    prepare_asic_libraries(chip)

siliconcompiler/tools/yosys/syn_asic.py

@@ -74,6 +74,7 @@ def setup_asic(chip):
     mainlib = get_mainlib(chip)
     for option, value in [
             ('flatten', "true"),
+            ('auto_flatten', "true"),
             ('hier_iterations', "10"),
             ('hier_threshold', "1000"),
             ('autoname', "true"),
@@ -171,6 +172,8 @@ def setup_asic(chip):
     chip.set('tool', tool, 'task', task, 'var', 'add_buffers',
              'true/false, flag to indicate whether to add buffers or not.', field='help')
 
+    chip.set('tool', tool, 'task', task, 'var', 'auto_flatten',
+             'true/false, attempt to determine how to flatten the design', field='help')
     chip.set('tool', tool, 'task', task, 'var', 'hier_iterations',
              'Number of iterations to attempt to determine the hierarchy to flatten',
              field='help')

siliconcompiler/tools/yosys/syn_asic.tcl

@@ -1,8 +1,6 @@
 ####################
 # Helper functions
 ####################
-source "$sc_refdir/syn_asic_fpga_shared.tcl"
-
 proc preserve_modules { } {
     global sc_cfg
     global sc_tool
@@ -232,7 +230,7 @@ yosys synth {*}$synth_args -top $sc_design -run begin:fine
 sc_map_memory $sc_memory_libmap_files $sc_memory_techmap_files 0
 
 # Perform hierarchy flattening
-if { !$flatten_design } {
+if { !$flatten_design && [lindex [sc_cfg_tool_task_get var auto_flatten] 0] == "true" } {
     set sc_hier_iterations \
         [lindex [sc_cfg_tool_task_get var hier_iterations] 0]
     set sc_hier_threshold \

siliconcompiler/tools/yosys/syn_fpga.tcl

@@ -1,5 +1,6 @@
-source "$sc_refdir/syn_asic_fpga_shared.tcl"
-
+####################
+# Helper functions
+####################
 proc legalize_flops { feature_set } {
     set legalize_flop_types []
 

siliconcompiler/toolscripts/_tools.json

@@ -1,7 +1,7 @@
 {
   "openroad": {
     "git-url": "https://github.com/The-OpenROAD-Project/OpenROAD.git",
-    "git-commit": "3a75eb5d52a207622c3dfd52937d3a02488f76b5",
+    "git-commit": "ea63b9aa612f296523b0ec8a6b51dec94de8839c",
     "docker-cmds": [
       "# Remove OR-Tools files",
       "RUN rm -f $SC_PREFIX/Makefile $SC_PREFIX/README.md",
@@ -36,7 +36,7 @@
     "auto-update": false
   },
   "klayout": {
-    "version": "0.29.7",
+    "version": "0.29.8",
     "git-url": "https://github.com/KLayout/klayout.git",
     "docker-skip": true,
     "auto-update": true,
@@ -45,7 +45,7 @@
   },
   "sv2v": {
     "git-url": "https://github.com/zachjs/sv2v.git",
-    "git-commit": "5374679e4bb26e115b9a9b4a2d8ef4253d7a8bf3",
+    "git-commit": "7808819c48c167978aeb5ef34c6e5ed416e90875",
     "auto-update": true
   },
   "verilator": {

siliconcompiler/utils/__init__.py

@@ -1,9 +1,10 @@
 import contextlib
+import hashlib
 import os
 import re
 import psutil
 import shutil
-from pathlib import Path
+from pathlib import Path, PurePosixPath
 from siliconcompiler._metadata import version as sc_version
 from jinja2 import Environment, FileSystemLoader
 
@@ -421,3 +422,31 @@ def truncate_text(text, width):
         text = text[:break_at-1] + '...' + text[break_at+3:]
 
     return text
+
+
+def get_hashed_filename(path, package=None, hash=hashlib.sha1):
+    '''
+    Utility to map collected file to an unambiguous name based on its path.
+
+    The mapping looks like:
+    path/to/file.ext => file_<hash('path/to/file')>.ext
+    '''
+    path = PurePosixPath(path)
+    ext = ''.join(path.suffixes)
+
+    # strip off all file suffixes to get just the bare name
+    barepath = path
+    while barepath.suffix:
+        barepath = PurePosixPath(barepath.stem)
+    filename = str(barepath.parts[-1])
+
+    if not package:
+        package = ''
+    else:
+        package = f'{package}:'
+
+    path_to_hash = f'{package}{str(path)}'
+
+    pathhash = hash(path_to_hash.encode('utf-8')).hexdigest()
+
+    return f'{filename}_{pathhash}{ext}'

siliconcompiler/utils/showtools.py

@@ -4,6 +4,7 @@ from siliconcompiler.tools.openroad import show as openroad_show
 from siliconcompiler.tools.openroad import screenshot as openroad_screenshot
 from siliconcompiler.tools.vpr import show as vpr_show
 from siliconcompiler.tools.vpr import screenshot as vpr_screenshot
+from siliconcompiler.tools.yosys import screenshot as yosys_screenshot
 
 
 def setup(chip):
@@ -23,3 +24,6 @@ def setup(chip):
     chip.register_showtool('route', vpr_screenshot)
     chip.register_showtool('place', vpr_show)
     chip.register_showtool('place', vpr_screenshot)
+
+    chip.register_showtool('v', yosys_screenshot)
+    chip.register_showtool('vg', yosys_screenshot)

{siliconcompiler-0.28.3.dist-info → siliconcompiler-0.28.4.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: siliconcompiler
-Version: 0.28.3
+Version: 0.28.4
 Summary: A compiler framework that automates translation from source code to silicon.
 Author-email: Andreas Olofsson <andreas.d.olofsson@gmail.com>
 License: Apache License 2.0
@@ -9,6 +9,19 @@ Project-URL: Documentation, https://docs.siliconcompiler.com
 Project-URL: Repository, https://github.com/siliconcompiler/siliconcompiler
 Project-URL: Issues, https://github.com/siliconcompiler/siliconcompiler/issues
 Project-URL: Discussion, https://github.com/siliconcompiler/siliconcompiler/discussions
+Classifier: Environment :: Console
+Classifier: License :: OSI Approved :: Apache Software License
+Classifier: Programming Language :: Python :: 3.8
+Classifier: Programming Language :: Python :: 3.9
+Classifier: Programming Language :: Python :: 3.10
+Classifier: Programming Language :: Python :: 3.11
+Classifier: Programming Language :: Python :: 3.12
+Classifier: Programming Language :: Python :: 3.13
+Classifier: Operating System :: POSIX :: Linux
+Classifier: Operating System :: MacOS
+Classifier: Operating System :: Microsoft :: Windows
+Classifier: Topic :: Scientific/Engineering :: Electronic Design Automation (EDA)
+Classifier: Topic :: Software Development :: Build Tools
 Requires-Python: >=3.8
 Description-Content-Type: text/markdown
 License-File: LICENSE
@@ -30,7 +43,7 @@ Requires-Dist: fasteners ==0.19
 Requires-Dist: fastjsonschema ==2.20.0
 Requires-Dist: docker ==7.1.0
 Requires-Dist: sc-surelog ==1.84.1
-Requires-Dist: orjson ==3.10.7
+Requires-Dist: orjson ==3.10.10
 Requires-Dist: streamlit ==1.39.0
 Requires-Dist: streamlit-agraph ==0.0.45
 Requires-Dist: streamlit-antd-components ==0.3.2
@@ -40,7 +53,7 @@ Requires-Dist: importlib-metadata ; python_version < "3.10"
 Provides-Extra: docs
 Requires-Dist: Sphinx ==8.1.3 ; extra == 'docs'
 Requires-Dist: pip-licenses ==5.0.0 ; extra == 'docs'
-Requires-Dist: pydata-sphinx-theme ==0.15.4 ; extra == 'docs'
+Requires-Dist: pydata-sphinx-theme ==0.16.0 ; extra == 'docs'
 Requires-Dist: sc-leflib >=0.2.0 ; extra == 'docs'
 Provides-Extra: examples
 Requires-Dist: migen ==0.9.2 ; extra == 'examples'