siliconcompiler 0.28.3__py3-none-any.whl → 0.28.4__py3-none-any.whl

siliconcompiler/tools/_common/asic.py

@@ -47,7 +47,8 @@ def set_tool_task_var(chip,
                       option_key=None,
                       pdk_key=None,
                       lib_key=None,
-                      require=None):
+                      require=None,
+                      skip=None):
     '''
     Set parameter from PDK -> main library -> option -> default_value
     '''
@@ -56,7 +57,11 @@ def set_tool_task_var(chip,
     tool, task = _common.get_tool_task(chip, step, index)
     pdkname = chip.get('option', 'pdk')
     stackup = chip.get('option', 'stackup')
-    mainlib = get_mainlib(chip)
+
+    if not skip:
+        skip = []
+    if not isinstance(skip, (list, tuple)):
+        skip = [skip]
 
     if not require:
         require = []
@@ -66,31 +71,35 @@ def set_tool_task_var(chip,
     check_keys = []
 
     # Add PDK key
-    if not pdk_key:
-        pdk_key = param_key
-    check_keys.append(['pdk', pdkname, 'var', tool, stackup, pdk_key])
-    if 'pdk' in require:
-        chip.add('tool', tool, 'task', task, 'require',
-                 ','.join(check_keys[-1]),
-                 step=step, index=index)
+    if 'pdk' not in skip:
+        if not pdk_key:
+            pdk_key = param_key
+        check_keys.append(['pdk', pdkname, 'var', tool, stackup, pdk_key])
+        if 'pdk' in require:
+            chip.add('tool', tool, 'task', task, 'require',
+                     ','.join(check_keys[-1]),
+                     step=step, index=index)
 
     # Add library key
-    if not lib_key:
-        lib_key = f'{tool}_{param_key}'
-    check_keys.append(['library', mainlib, 'option', 'var', lib_key])
-    if 'lib' in require:
-        chip.add('tool', tool, 'task', task, 'require',
-                 ','.join(check_keys[-1]),
-                 step=step, index=index)
+    if 'lib' not in skip:
+        mainlib = get_mainlib(chip)
+        if not lib_key:
+            lib_key = f'{tool}_{param_key}'
+        check_keys.append(['library', mainlib, 'option', 'var', lib_key])
+        if 'lib' in require:
+            chip.add('tool', tool, 'task', task, 'require',
+                     ','.join(check_keys[-1]),
+                     step=step, index=index)
 
     # Add option key
-    if not option_key:
-        option_key = f'{tool}_{param_key}'
-    check_keys.append(['option', 'var', option_key])
-    if 'option' in require:
-        chip.add('tool', tool, 'task', task, 'require',
-                 ','.join(check_keys[-1]),
-                 step=step, index=index)
+    if 'option' not in skip:
+        if not option_key:
+            option_key = f'{tool}_{param_key}'
+        check_keys.append(['option', 'var', option_key])
+        if 'option' in require:
+            chip.add('tool', tool, 'task', task, 'require',
+                     ','.join(check_keys[-1]),
+                     step=step, index=index)
 
     require_key, value = _common.pick_key(chip, reversed(check_keys), step=step, index=index)
     if not value:
@@ -113,3 +122,50 @@ def set_tool_task_var(chip,
     if schelp:
         chip.set('tool', tool, 'task', task, 'var', param_key,
                  schelp, field='help')
+
+    return value
+
+
+def get_tool_task_var(chip,
+                      param_key,
+                      option_key=None,
+                      pdk_key=None,
+                      lib_key=None,
+                      skip=None):
+    '''
+    Get parameter from PDK -> main library -> option -> default_value
+    '''
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, _ = _common.get_tool_task(chip, step, index)
+    pdkname = chip.get('option', 'pdk')
+    stackup = chip.get('option', 'stackup')
+
+    if not skip:
+        skip = []
+    if not isinstance(skip, (list, tuple)):
+        skip = [skip]
+
+    check_keys = []
+    # Add PDK key
+    if 'pdk' not in skip:
+        if not pdk_key:
+            pdk_key = param_key
+        check_keys.append(['pdk', pdkname, 'var', tool, stackup, pdk_key])
+
+    # Add library key
+    if 'lib' not in skip:
+        mainlib = get_mainlib(chip)
+        if not lib_key:
+            lib_key = f'{tool}_{param_key}'
+        check_keys.append(['library', mainlib, 'option', 'var', lib_key])
+
+    # Add option key
+    if 'option' not in skip:
+        if not option_key:
+            option_key = f'{tool}_{param_key}'
+        check_keys.append(['option', 'var', option_key])
+
+    _, value = _common.pick_key(chip, reversed(check_keys), step=step, index=index)
+
+    return value

siliconcompiler/tools/genfasm/genfasm.py

@@ -1,5 +1,6 @@
 from siliconcompiler.tools.vpr.vpr import parse_version as vpr_parse_version
 from siliconcompiler.tools.vpr.vpr import normalize_version as vpr_normalize_version
+from siliconcompiler.tools.vpr.vpr import add_tool_requirements as add_vpr_requirements
 
 '''
 Generate a `FSAM <https://github.com/chipsalliance/fasm>`_ file from the output of
@@ -25,6 +26,12 @@ def setup(chip):
     chip.set('tool', 'genfasm', 'vswitch', '--version')
     chip.set('tool', 'genfasm', 'version', '>=8.1.0', clobber=False)
 
+    add_tool_requirements(chip)
+
+
+def add_tool_requirements(chip):
+    add_vpr_requirements(chip)
+
 
 def parse_version(chip):
     return vpr_parse_version(chip)

siliconcompiler/tools/ghdl/convert.py

@@ -40,6 +40,13 @@ def setup(chip):
 
     chip.set('tool', tool, 'task', task, 'output', f'{design}.v', step=step, index=index)
 
+    chip.set('tool', tool, 'task', task, 'var', 'extraopts', 'extra options to pass to ghdl',
+             field='help')
+    if chip.get('tool', tool, 'task', task, 'var', 'extraopts', step=step, index=index):
+        chip.add('tool', tool, 'task', task, 'require',
+                 ','.join(['tool', tool, 'task', task, 'var', 'extraopts']),
+                 step=step, index=index)
+
 
 ################################
 #  Custom runtime options

siliconcompiler/tools/klayout/convert_drc_db.py

@@ -0,0 +1,60 @@
+from siliconcompiler.tools._common import input_provides, input_file_node_name, get_tool_task
+
+from siliconcompiler.tools.klayout import klayout
+from siliconcompiler.tools.klayout.klayout import setup as setup_tool
+
+
+def make_docs(chip):
+    klayout.make_docs(chip)
+
+
+def setup(chip):
+    '''
+    Convert a DRC db from .lyrdb or .ascii to an openroad json marker file
+    '''
+
+    # Generic tool setup.
+    setup_tool(chip)
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+    design = chip.top()
+
+    clobber = False
+
+    chip.set('tool', tool, 'task', task, 'threads', 1,
+             step=step, index=index, clobber=clobber)
+
+    script = 'klayout_convert_drc_db.py'
+    option = ['-z', '-nc', '-rx', '-r']
+    chip.set('tool', tool, 'task', task, 'script', script,
+             step=step, index=index, clobber=clobber)
+    chip.set('tool', tool, 'task', task, 'option', option,
+             step=step, index=index, clobber=clobber)
+
+    input_nodes = set()
+    for nodes in input_provides(chip, step, index).values():
+        input_nodes.update(nodes)
+
+    chip.set('tool', tool, 'task', task, 'input', [], step=step, index=index)
+    chip.set('tool', tool, 'task', task, 'output', [], step=step, index=index)
+    for file, nodes in input_provides(chip, step, index).items():
+        if file not in (f'{design}.lyrdb', f'{design}.ascii'):
+            continue
+
+        if len(input_nodes) == 1:
+            chip.add('tool', tool, 'task', task, 'input',
+                     file,
+                     step=step, index=index)
+        else:
+            for in_step, in_index in nodes:
+                chip.add('tool', tool, 'task', task, 'input',
+                         input_file_node_name(file, in_step, in_index),
+                         step=step, index=index)
+    if not chip.get('tool', tool, 'task', task, 'input', step=step, index=index):
+        chip.add('tool', tool, 'task', task, 'input', f'{design}.lyrdb',
+                 step=step, index=index)
+
+    chip.set('tool', tool, 'task', task, 'output', f'{design}.json',
+             step=step, index=index)

siliconcompiler/tools/klayout/drc.py

@@ -0,0 +1,156 @@
+import os
+import shlex
+
+from siliconcompiler.tools._common import input_provides, has_input_files, \
+    get_input_files, get_tool_task, record_metric
+from siliconcompiler.tools._common.asic import set_tool_task_var, get_tool_task_var
+
+from siliconcompiler.tools.klayout import klayout
+from siliconcompiler.tools.klayout.klayout import setup as setup_tool
+import xml.etree.ElementTree as ET
+
+
+def make_docs(chip):
+    klayout.make_docs(chip)
+    chip.set('tool', 'klayout', 'task', 'drc', 'var', 'drc_name', '<drc_name>',
+             step='<step>', index='<index>')
+
+
+def setup(chip):
+    '''
+    Performs a design rule check on the provided layout
+    '''
+
+    # Generic tool setup.
+    setup_tool(chip)
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+    design = chip.top()
+
+    clobber = False
+
+    option = ['-z', '-nc', '-rx']
+    chip.set('tool', tool, 'task', task, 'option', option,
+             step=step, index=index, clobber=clobber)
+
+    chip.set('tool', tool, 'task', task, 'threads', os.cpu_count(),
+             step=step, index=index, clobber=clobber)
+
+    chip.add('tool', tool, 'task', task, 'require', 'option,pdk')
+    chip.add('tool', tool, 'task', task, 'require', 'option,stackup')
+
+    chip.set('tool', tool, 'task', task, 'var', 'drc_name', 'drc',
+             step=step, index=index, clobber=False)
+    chip.add('tool', tool, 'task', task, 'require', f'tool,{tool},task,{task},var,drc_name',
+             step=step, index=index)
+
+    drc_name = chip.get('tool', tool, 'task', task, 'var', 'drc_name', step=step, index=index)
+    if not drc_name:
+        raise ValueError('drc_name is required')
+    drc_name = drc_name[0]
+
+    pdk = chip.get('option', 'pdk')
+    stackup = chip.get('option', 'stackup')
+    chip.add('tool', tool, 'task', task, 'require',
+             f'pdk,{pdk},drc,runset,klayout,{stackup},{drc_name}')
+
+    if f'{design}.gds' in input_provides(chip, step, index):
+        chip.add('tool', tool, 'task', task, 'input', design + '.gds',
+                 step=step, index=index)
+    elif f'{design}.oas' in input_provides(chip, step, index):
+        chip.add('tool', tool, 'task', task, 'input', design + '.oas',
+                 step=step, index=index)
+    elif has_input_files(chip, 'input', 'layout', 'oas', check_library_files=False):
+        chip.add('tool', tool, 'task', task, 'require', 'input,layout,oas',
+                 step=step, index=index)
+    else:
+        chip.add('tool', tool, 'task', task, 'require', 'input,layout,gds',
+                 step=step, index=index)
+
+    chip.add('tool', tool, 'task', task, 'output', design + '.lyrdb',
+             step=step, index=index)
+
+    set_tool_task_var(
+        chip,
+        f'drc_params:{drc_name}',
+        schelp="Input parameter to DRC script, in the form of key=value, if the value "
+               "is <topcell>, <input>, <report>, <threads> these will be automatically "
+               "determined.",
+        skip='lib')
+
+
+def runtime_options(chip):
+    design = chip.top()
+
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    pdk = chip.get('option', 'pdk')
+    stackup = chip.get('option', 'stackup')
+
+    layout = None
+    for file in [f'inputs/{design}.gds', f'inputs/{design}.oas']:
+        if os.path.isfile(file):
+            layout = file
+            break
+
+    if not layout:
+        for file in [
+                get_input_files(chip, 'input', 'layout', 'oas', add_library_files=False),
+                get_input_files(chip, 'input', 'layout', 'gds', add_library_files=False)]:
+            if file:
+                layout = file[0]
+
+    threads = chip.get('tool', tool, 'task', task, 'threads', step=step, index=index)
+    if not threads:
+        threads = 1
+
+    drc_name = chip.get('tool', tool, 'task', task, 'var', 'drc_name',
+                        step=step, index=index)[0]
+    report = os.path.abspath(f"outputs/{chip.top()}.lyrdb")
+
+    runset = chip.find_files('pdk', pdk, 'drc', 'runset', 'klayout', stackup, drc_name)[0]
+
+    params_lookup = {
+        "<topcell>": chip.top(),
+        "<report>": shlex.quote(report),
+        "<threads>": threads,
+        "<input>": shlex.quote(layout)
+    }
+
+    args = [
+        '-r', shlex.quote(runset)
+    ]
+
+    for param in get_tool_task_var(chip, f'drc_params:{drc_name}', skip='lib'):
+        for lookup, value in params_lookup.items():
+            param = param.replace(lookup, str(value))
+        args.extend(
+            ['-rd', param]
+        )
+    return args
+
+
+def post_process(chip):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+
+    drc_db = f"outputs/{chip.top()}.lyrdb"
+
+    drc_report = None
+    if os.path.isfile(drc_db):
+        with open(drc_db, "r") as f:
+            drc_report = ET.fromstring(f.read())
+    if drc_report is None:
+        drc_db = []
+
+    violation_count = 0
+    if drc_report:
+        violations = drc_report.find('items')
+        if violations:
+            violation_count = len(violations.findall('item'))
+
+    record_metric(chip, step, index, 'drcs', violation_count, drc_db)

siliconcompiler/tools/klayout/export.py

@@ -19,6 +19,8 @@ def setup(chip):
     _, task = get_tool_task(chip, step, index)
     clobber = False
 
+    chip.set('tool', tool, 'task', task, 'threads', 1, step=step, index=index, clobber=clobber)
+
     script = 'klayout_export.py'
     option = ['-z', '-nc', '-rx', '-r']
     chip.set('tool', tool, 'task', task, 'script', script, step=step, index=index, clobber=clobber)

siliconcompiler/tools/klayout/klayout.py

@@ -82,7 +82,6 @@ def setup(chip, mode="batch"):
 
     chip.set('tool', tool, 'task', task, 'refdir', refdir, step=step, index=index,
              package='siliconcompiler', clobber=clobber)
-    chip.set('tool', tool, 'task', task, 'threads', 1, step=step, index=index, clobber=clobber)
 
     if chip.get('option', 'nodisplay'):
         # Tells QT to use the offscreen platform if nodisplay is used

siliconcompiler/tools/klayout/klayout_convert_drc_db.py

@@ -0,0 +1,182 @@
+# KLayout script to export an OpenROAD marker DB from a DRC db
+#
+# Based on:
+# https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts/blob/master/flow/util/convertDrc.py
+
+import pya
+import glob
+import json
+import os
+import sys
+
+
+def convert_drc(view, path):
+    rdb_id = view.create_rdb(os.path.basename(path))
+    rdb = view.rdb(rdb_id)
+    print(f"[INFO] reading {path}")
+    rdb.load(path)
+
+    source = os.path.abspath(path)
+
+    ordb = {
+        "source": source,
+        "description": "KLayout DRC conversion",
+        "category": {}
+    }
+
+    for category in rdb.each_category():
+        if category.num_items() == 0:
+            # ignore categories with no data
+            continue
+
+        ordb_category = {
+            "description": category.description,
+            "source": source,
+            "violations": []
+        }
+        ordb["category"][category.name()] = ordb_category
+
+        for item in rdb.each_item_per_category(category.rdb_id()):
+            violation = {
+                "visited": item.is_visited(),
+                "visible": True,
+                "waived": "waived" in item.tags_str
+            }
+
+            ordb_category["violations"].append(violation)
+
+            shapes = []
+            violation["shape"] = shapes
+
+            text = []
+
+            for value in item.each_value():
+                if value.is_box():
+                    shapes.append({
+                        "type": "box",
+                        "points": [{
+                            "x": value.box().left,
+                            "y": value.box().bottom
+                        }, {
+                            "x": value.box().right,
+                            "y": value.box().top
+                        }]
+                    })
+                elif value.is_edge():
+                    shapes.append({
+                        "type": "line",
+                        "points": [{
+                            "x": value.edge().p1.x,
+                            "y": value.edge().p1.y
+                        }, {
+                            "x": value.edge().p2.x,
+                            "y": value.edge().p2.y
+                        }]
+                    })
+                elif value.is_edge_pair():
+                    edge1 = value.edge_pair().first
+                    edge2 = value.edge_pair().second
+
+                    shapes.append({
+                        "type": "line",
+                        "points": [{
+                            "x": edge1.p1.x,
+                            "y": edge1.p1.y
+                        }, {
+                            "x": edge1.p2.x,
+                            "y": edge1.p2.y
+                        }]
+                    })
+                    shapes.append({
+                        "type": "line",
+                        "points": [{
+                            "x": edge2.p1.x,
+                            "y": edge2.p1.y
+                        }, {
+                            "x": edge2.p2.x,
+                            "y": edge2.p2.y
+                        }]
+                    })
+                elif value.is_polygon():
+                    points = []
+                    for edge in value.polygon().each_edge():
+                        points.append({
+                            "x": edge.p1.x,
+                            "y": edge.p1.y
+                        })
+                    points.append({
+                        "x": edge.p2.x,
+                        "y": edge.p2.y
+                    })
+                    shapes.append({
+                        "type": "polygon",
+                        "points": points
+                    })
+                elif value.is_path():
+                    points = []
+                    for edge in value.path().polygon().each_edge():
+                        points.append({
+                            "x": edge.p1.x,
+                            "y": edge.p1.y
+                        })
+                    points.append({
+                        "x": edge.p2.x,
+                        "y": edge.p2.y
+                    })
+                    shapes.append({
+                        "type": "polygon",
+                        "points": points
+                    })
+                elif value.is_text():
+                    text.append(value.text())
+                elif value.is_string():
+                    text.append(value.string())
+                else:
+                    print("[WARN] Unknown violation shape:", value)
+
+            comment = ""
+            if hasattr(item, 'comment'):
+                comment = item.comment
+            if text:
+                if comment:
+                    comment += ": "
+                comment += ", ".join(text)
+
+            if comment:
+                violation["comment"] = comment
+
+    return ordb
+
+
+def main():
+    # SC_ROOT provided by CLI
+    sys.path.append(SC_ROOT)  # noqa: F821
+
+    from tools.klayout.klayout_utils import get_schema
+
+    schema = get_schema(manifest='sc_manifest.json')
+
+    design = schema.get('design')
+
+    app = pya.Application.instance()
+    win = app.main_window()
+
+    # Create a dummy view to use for loading
+    cell_view = win.create_layout(0)
+    layout_view = cell_view.view()
+
+    ordb = {}
+    for file in glob.glob(f'inputs/{design}*.lyrdb') + glob.glob('inputs/{design}*.ascii'):
+        name = os.path.basename(file)
+
+        ordb[name] = convert_drc(layout_view, file)
+
+    with open(f"outputs/{design}.json", "w") as outfile:
+        json.dump(
+            ordb,
+            outfile,
+            indent=2)
+
+
+if __name__ == '__main__':
+    main()

siliconcompiler/tools/klayout/operations.py

@@ -109,6 +109,8 @@ def setup(chip):
     _, task = get_tool_task(chip, step, index)
     clobber = False
 
+    chip.set('tool', tool, 'task', task, 'threads', 1, step=step, index=index, clobber=clobber)
+
     script = 'klayout_operations.py'
     option = ['-z', '-nc', '-rx', '-r']
     chip.set('tool', tool, 'task', task, 'script', script, step=step, index=index, clobber=clobber)

siliconcompiler/tools/klayout/screenshot.py

@@ -24,6 +24,8 @@ def setup(chip):
     _, task = get_tool_task(chip, step, index)
     clobber = False
 
+    chip.set('tool', tool, 'task', task, 'threads', 1, step=step, index=index, clobber=clobber)
+
     setup_gui_screenshot(chip)
 
     option = ['-nc', '-z', '-rm']

siliconcompiler/tools/klayout/show.py

@@ -73,12 +73,12 @@ def setup(chip):
 
     step = chip.get('arg', 'step')
     index = chip.get('arg', 'index')
-    _, task = get_tool_task(chip, step, index)
+    tool, task = get_tool_task(chip, step, index)
+    clobber = False
 
-    general_gui_setup(chip, task, False)
+    chip.set('tool', tool, 'task', task, 'threads', 1, step=step, index=index, clobber=clobber)
 
-    tool = 'klayout'
-    clobber = False
+    general_gui_setup(chip, task, False)
 
     option = ['-nc', '-rm']
     chip.set('tool', tool, 'task', task, 'option', option, step=step, index=index, clobber=clobber)

siliconcompiler/tools/magic/drc.py

@@ -1,8 +1,10 @@
 import re
 
 from siliconcompiler.tools.magic.magic import setup as setup_tool
+from siliconcompiler.tools.magic.magic import process_file
 from siliconcompiler import sc_open
 from siliconcompiler.tools._common import get_tool_task, record_metric
+from siliconcompiler.tools._common.asic import get_mainlib, get_libraries
 
 
 def setup(chip):
@@ -22,6 +24,25 @@ def setup(chip):
     chip.set('tool', tool, 'task', task, 'output', f'{design}.drc.mag', step=step, index=index)
 
 
+def pre_process(chip):
+    step = chip.get('arg', 'step')
+    index = chip.get('arg', 'index')
+    tool, task = get_tool_task(chip, step, index)
+
+    pdk = chip.get('option', 'pdk')
+    stackup = chip.get('option', 'stackup')
+    mainlib = get_mainlib(chip)
+    libtype = chip.get('library', mainlib, 'asic', 'libarch', step=step, index=index)
+    process_file('lef', chip, 'pdk', pdk, 'aprtech', 'magic', stackup, libtype, 'lef')
+
+    for lib in get_libraries(chip, 'logic'):
+        process_file('lef', chip, 'library', lib, 'output', stackup, 'lef')
+
+    for lib in get_libraries(chip, 'macro'):
+        if lib in chip.get('tool', tool, 'task', task, 'var', 'exclude', step=step, index=index):
+            process_file('lef', chip, 'library', lib, 'output', stackup, 'lef')
+
+
 ################################
 # Post_process (post executable)
 ################################