siliconcompiler 0.26.5__py3-none-any.whl → 0.27.1__py3-none-any.whl

siliconcompiler/flows/synflow.py

@@ -15,14 +15,13 @@ from siliconcompiler.tools.builtin import minimum
 def make_docs(chip):
     n = 3
     _make_docs(chip)
-    return setup(chip, syn_np=n, timing_np=n)
+    return setup(syn_np=n, timing_np=n)
 
 
 ###########################################################################
 # Flowgraph Setup
 ############################################################################
-def setup(chip,
-          flowname='synflow',
+def setup(flowname='synflow',
           syn_np=1,
           timing_np=1):
     '''
@@ -44,7 +43,7 @@ def setup(chip,
     * timing_np : Number of parallel timing jobs to launch
     '''
 
-    flow = siliconcompiler.Flow(chip, flowname)
+    flow = siliconcompiler.Flow(flowname)
 
     # Linear flow, up until branch to run parallel verification steps.
     longpipe = ['syn',
@@ -80,7 +79,7 @@ def setup(chip,
         flowtasks.append((step, tasks[step]))
 
     # Programmatically build linear portion of flowgraph and fanin/fanout args
-    prevstep = setup_multiple_frontends(chip, flow)
+    prevstep = setup_multiple_frontends(flow)
     for step, task in flowtasks:
         fanout = 1
         if step in np:

siliconcompiler/fpgas/lattice_ice40.py

@@ -5,7 +5,7 @@ from siliconcompiler.utils import register_sc_data_source
 ####################################################
 # Setup for ICE40 Family FPGAs
 ####################################################
-def setup(chip):
+def setup():
     '''
     Lattice ICE40 FPGAs are a family of small parts
     made by Lattice Semiconductor.  A fully open source
@@ -23,10 +23,9 @@ def setup(chip):
         "ice40up5k-sg48",
     ]
 
-    register_sc_data_source(chip)
-
     for part_name in all_part_names:
-        fpga = siliconcompiler.FPGA(chip, part_name, package='siliconcompiler_data')
+        fpga = siliconcompiler.FPGA(part_name, package='siliconcompiler_data')
+        register_sc_data_source(fpga)
 
         fpga.set('fpga', part_name, 'vendor', vendor)
         fpga.set('fpga', part_name, 'lutsize', lut_size)

siliconcompiler/fpgas/vpr_example.py

@@ -6,7 +6,7 @@ from siliconcompiler.utils import register_sc_data_source
 ####################################################
 # Setup for vpr_example Family FPGAs
 ####################################################
-def setup(chip):
+def setup():
     '''
     The vpr_example FPGA family is a set of
     open source architectures used as illustrative
@@ -36,11 +36,10 @@ def setup(chip):
         'example_arch_X030Y030',
     ]
 
-    register_sc_data_source(chip)
-
     # Settings common to all parts in family
     for part_name in all_part_names:
-        fpga = siliconcompiler.FPGA(chip, part_name, package='siliconcompiler_data')
+        fpga = siliconcompiler.FPGA(part_name, package='siliconcompiler_data')
+        register_sc_data_source(fpga)
 
         fpga.set('fpga', part_name, 'vendor', vendor)
 

siliconcompiler/scheduler/send_messages.py

@@ -12,6 +12,7 @@ import fastjsonschema
 from pathlib import Path
 from siliconcompiler.flowgraph import get_executed_nodes
 import uuid
+from siliconcompiler.targets import freepdk45_demo
 
 
 # Compile validation code for API request bodies.
@@ -172,7 +173,7 @@ def send(chip, msg_type, step, index):
 if __name__ == "__main__":
     from siliconcompiler import Chip
     chip = Chip('test')
-    chip.load_target("freepdk45_demo")
+    chip.use(freepdk45_demo)
     chip.set('option', 'scheduler', 'msgevent', 'ALL')
     # chip.set('option', 'scheduler', 'msgcontact', 'fillin')
     send(chip, "BEGIN", "import", "0")

siliconcompiler/schema/schema_cfg.py

@@ -10,7 +10,7 @@ try:
 except ImportError:
     from siliconcompiler.schema.utils import trim
 
-SCHEMA_VERSION = '0.44.3'
+SCHEMA_VERSION = '0.44.4'
 
 #############################################################################
 # PARAM DEFINITION
@@ -2540,19 +2540,6 @@ def schema_option(cfg):
             `Unix 'nice' <https://en.wikipedia.org/wiki/Nice_(Unix)>`_.""")
 
     # Compilation
-    scparam(cfg, ['option', 'target'],
-            sctype='str',
-            scope='job',
-            shorthelp="Compilation target",
-            switch="-target <str>",
-            example=["cli: -target freepdk45_demo",
-                     "api: chip.set('option', 'target', 'freepdk45_demo')"],
-            schelp="""
-            Sets a target module to be used for compilation. The target
-            module must set up all parameters needed. The target module
-            may load multiple flows and libraries.
-            """)
-
     scparam(cfg, ['option', 'pdk'],
             sctype='str',
             scope='job',

siliconcompiler/schema/schema_obj.py

@@ -5,7 +5,6 @@
 # that have isolated Python environments.
 
 import copy
-import json
 import logging
 import os
 import re
@@ -14,6 +13,13 @@ import argparse
 import sys
 import shlex
 
+try:
+    import orjson as json
+    _has_orjson = True
+except ModuleNotFoundError:
+    import json
+    _has_orjson = False
+
 try:
     import gzip
     _has_gzip = True
@@ -223,7 +229,7 @@ class Schema:
 
         try:
             if re.search(r'(\.json|\.sup)(\.gz)*$', filepath, flags=re.IGNORECASE):
-                localcfg = json.load(fin)
+                localcfg = json.loads(fin.read())
             elif re.search(r'(\.yaml|\.yml)(\.gz)*$', filepath, flags=re.IGNORECASE):
                 if not _has_yaml:
                     raise ImportError('yaml package required to read YAML manifest')
@@ -1023,7 +1029,11 @@ class Schema:
         localcfg = {**self.cfg}
         if self.__journal is not None:
             localcfg['__journal__'] = self.__journal
-        fout.write(json.dumps(localcfg, indent=4))
+        if _has_orjson:
+            manifest_str = json.dumps(localcfg, option=json.OPT_INDENT_2).decode()
+        else:
+            manifest_str = json.dumps(localcfg, indent=2)
+        fout.write(manifest_str)
 
     ###########################################################################
     def write_yaml(self, fout):
@@ -1467,6 +1477,26 @@ class Schema:
                                         help=helpstr,
                                         default=argparse.SUPPRESS)
 
+        print_additional_arg_value = {}
+        if additional_args:
+            # Add additional user specified arguments
+            arg_dests = []
+            for arg, arg_detail in additional_args.items():
+                do_print = True
+                if "sc_print" in arg_detail:
+                    do_print = arg_detail["sc_print"]
+                    del arg_detail["sc_print"]
+                argument = parser.add_argument(arg, **arg_detail)
+                print_additional_arg_value[argument.dest] = do_print
+
+                arg_dests.append(argument.dest)
+                used_switches.add(arg)
+            # rewrite additional_args with new dest information
+            additional_args = arg_dests
+
+        if version:
+            parser.add_argument('-version', action='version', version=version)
+
         # Check if there are invalid switches
         if switchlist:
             for switch in switchlist:
@@ -1503,25 +1533,6 @@ class Schema:
             else:
                 scargs.append(argument)
 
-        if version:
-            parser.add_argument('-version', action='version', version=version)
-
-        print_additional_arg_value = {}
-        if additional_args:
-            # Add additional user specified arguments
-            arg_dests = []
-            for arg, arg_detail in additional_args.items():
-                do_print = True
-                if "sc_print" in arg_detail:
-                    do_print = arg_detail["sc_print"]
-                    del arg_detail["sc_print"]
-                argument = parser.add_argument(arg, **arg_detail)
-                print_additional_arg_value[argument.dest] = do_print
-
-                arg_dests.append(argument.dest)
-            # rewrite additional_args with new dest information
-            additional_args = arg_dests
-
         # Grab argument from pre-process sysargs
         cmdargs = vars(parser.parse_args(scargs))
 
@@ -1535,7 +1546,7 @@ class Schema:
             for arg in additional_args:
                 if arg in cmdargs:
                     val = cmdargs[arg]
-                    if print_additional_arg_value[arg]:
+                    if print_additional_arg_value[arg] and val:
                         msg = f'Command line argument entered: "{arg}" Value: {val}'
                         self.logger.info(msg)
                     extra_params[arg] = val
@@ -1656,7 +1667,7 @@ class Schema:
                     self.set(*args, val, step=step, index=index, clobber=True)
 
         if post_process:
-            post_process(cmdargs)
+            extra_params = post_process(cmdargs, extra_params)
 
         return extra_params
 

siliconcompiler/sphinx_ext/dynamicgen.py

@@ -386,7 +386,7 @@ class DynamicGen(SphinxDirective):
         setup = self.get_setup_method(module)
         if not setup:
             return None
-        new_chip = setup(chip)
+        new_chip = setup()
         if new_chip:
             return new_chip
         else:
@@ -399,7 +399,7 @@ class DynamicGen(SphinxDirective):
         if docs_chip and docs_configured:
             return docs_chip
 
-        return self._handle_setup(chip, module)
+        return self._handle_setup(module)
 
     def get_ref_prefix(self):
         return self.REF_PREFIX
@@ -635,7 +635,7 @@ class ToolGen(DynamicGen):
         if toolmodule:
             return chip
         else:
-            return self._handle_setup(chip, module)
+            return self._handle_setup(module)
 
     def display_config(self, chip, modname):
         '''Display config under `eda, <modname>` in a single table.'''
@@ -726,7 +726,7 @@ class ToolGen(DynamicGen):
             s += p
 
         try:
-            task_setup(chip)
+            task_setup()
 
             config = build_section("Configuration", self.get_configuration_ref_key(toolname,
                                                                                    taskname))

siliconcompiler/targets/asic_demo.py

@@ -17,7 +17,7 @@ def setup(chip):
     chip.set('design', design)
 
     # Load the Sky130 PDK/standard cell library target.
-    chip.load_target(skywater130_demo)
+    chip.use(skywater130_demo)
 
     # Set quiet flag
     chip.set('option', 'quiet', True, clobber=False)

siliconcompiler/targets/fpgaflow_demo.py

@@ -34,7 +34,7 @@ def setup(chip):
         raise SiliconCompilerError(f'{part_name} has not been loaded', chip=chip)
 
     # 3. Load flow
-    chip.use(fpgaflow)
+    chip.use(fpgaflow, partname=part_name)
 
     # 4. Select default flow
     chip.set('option', 'flow', 'fpgaflow', clobber=False)

siliconcompiler/tools/klayout/klayout.py

@@ -15,13 +15,14 @@ from pathlib import Path
 import platform
 import shutil
 from siliconcompiler.tools._common import get_tool_task
+from siliconcompiler.targets import freepdk45_demo
 
 
 ####################################################################
 # Make Docs
 ####################################################################
 def make_docs(chip):
-    chip.load_target("freepdk45_demo")
+    chip.use(freepdk45_demo)
 
 
 ####################################################################

siliconcompiler/tools/magic/magic.py

@@ -11,13 +11,14 @@ Sources: https://github.com/RTimothyEdwards/magic
 
 import os
 from siliconcompiler.tools._common import input_provides, get_tool_task
+from siliconcompiler.targets import freepdk45_demo
 
 
 ####################################################################
 # Make Docs
 ####################################################################
 def make_docs(chip):
-    chip.load_target("freepdk45_demo")
+    chip.use(freepdk45_demo)
 
 
 ################################

siliconcompiler/tools/openroad/openroad.py

@@ -18,13 +18,14 @@ from siliconcompiler import utils
 from siliconcompiler.tools._common import input_provides, add_common_file, \
     get_tool_task, record_metric
 from siliconcompiler.tools._common.asic import get_mainlib, set_tool_task_var, get_libraries
+from siliconcompiler.targets import asap7_demo
 
 
 ####################################################################
 # Make Docs
 ####################################################################
 def make_docs(chip):
-    chip.load_target("asap7_demo")
+    chip.use(asap7_demo)
 
 
 ################################

siliconcompiler/tools/opensta/__init__.py

@@ -12,13 +12,14 @@ import os
 from siliconcompiler.tools.openroad.openroad import get_library_timing_keypaths
 from siliconcompiler.tools._common import get_tool_task
 from siliconcompiler.tools._common.asic import get_libraries
+from siliconcompiler.targets import asap7_demo
 
 
 ####################################################################
 # Make Docs
 ####################################################################
 def make_docs(chip):
-    chip.load_target("asap7_demo")
+    chip.use(asap7_demo)
 
 
 ################################

siliconcompiler/tools/verilator/verilator.py

@@ -33,13 +33,14 @@ from siliconcompiler.tools._common import (
     get_tool_task,
     input_provides
 )
+from siliconcompiler.targets import freepdk45_demo
 
 
 ####################################################################
 # Make Docs
 ####################################################################
 def make_docs(chip):
-    chip.load_target("freepdk45_demo")
+    chip.use(freepdk45_demo)
 
 
 def setup(chip):

siliconcompiler/tools/vivado/vivado.py

@@ -10,11 +10,12 @@ import os
 import re
 from siliconcompiler import sc_open
 from siliconcompiler.tools._common import record_metric
+from siliconcompiler.targets import fpgaflow_demo
 
 
 def make_docs(chip):
     chip.set('fpga', 'partname', 'ice40up5k-sg48')
-    chip.load_target("fpgaflow_demo")
+    chip.use(fpgaflow_demo)
 
 
 tool = 'vivado'

siliconcompiler/tools/vpr/vpr.py

@@ -31,8 +31,9 @@ __block_file = "reports/block_usage.json"
 # Make Docs
 ######################################################################
 def make_docs(chip):
+    from siliconcompiler.targets import fpgaflow_demo
     chip.set('fpga', 'partname', 'example_arch_X005Y005')
-    chip.load_target("fpgaflow_demo")
+    chip.use(fpgaflow_demo)
     setup_tool(chip)
     return chip
 

siliconcompiler/tools/yosys/syn_asic.py

@@ -7,10 +7,11 @@ from siliconcompiler import sc_open
 from siliconcompiler import utils
 from siliconcompiler.tools._common.asic import set_tool_task_var, get_libraries, get_mainlib
 from siliconcompiler.tools._common import get_tool_task
+from siliconcompiler.targets import asap7_demo
 
 
 def make_docs(chip):
-    chip.load_target("asap7_demo")
+    chip.use(asap7_demo)
 
 
 def setup(chip):

siliconcompiler/tools/yosys/syn_fpga.py

@@ -2,6 +2,7 @@ from siliconcompiler.tools.yosys.yosys import syn_setup, syn_post_process
 import json
 from siliconcompiler import sc_open
 from siliconcompiler.tools._common import get_tool_task, record_metric
+from siliconcompiler.targets import fpgaflow_demo
 
 
 ######################################################################
@@ -9,7 +10,7 @@ from siliconcompiler.tools._common import get_tool_task, record_metric
 ######################################################################
 def make_docs(chip):
     chip.set('fpga', 'partname', 'ice40up5k-sg48')
-    chip.load_target("fpgaflow_demo")
+    chip.use(fpgaflow_demo)
 
 
 def setup(chip):

siliconcompiler/tools/yosys/yosys.py

@@ -17,13 +17,14 @@ import re
 import json
 from siliconcompiler import sc_open
 from siliconcompiler.tools._common import get_tool_task, record_metric
+from siliconcompiler.targets import asap7_demo
 
 
 ######################################################################
 # Make Docs
 ######################################################################
 def make_docs(chip):
-    chip.load_target("asap7_demo")
+    chip.use(asap7_demo)
 
 
 ################################

siliconcompiler/use.py

@@ -4,12 +4,15 @@ from siliconcompiler import Chip
 
 
 class PackageChip(Chip):
-    def __init__(self, chip, name, package=None):
+    def __init__(self, *args, package=None):
         # Start with None as init setting will not depend on package
         self.__package = None
 
+        name = args[-1]
         super().__init__(name)
-        self.logger = chip.logger
+
+        if len(args) == 2:
+            self.logger.warning(f'passing Chip object to {type(self)} is deprecated')
 
         path = None
         ref = None
@@ -83,11 +86,10 @@ class PDK(PackageChip):
     This inherits all methods from :class:`~siliconcompiler.Chip`.
 
     Args:
-        chip (Chip): A real only copy of the parent chip.
         name (string): Name of the PDK.
         package (string): Name of the data source
     Examples:
-        >>> siliconcompiler.PDK(chip, "asap7")
+        >>> siliconcompiler.PDK("asap7")
         Creates a flow object with name "asap7".
     """
 
@@ -101,11 +103,10 @@ class FPGA(PackageChip):
     This inherits all methods from :class:`~siliconcompiler.Chip`.
 
     Args:
-        chip (Chip): A real only copy of the parent chip.
         name (string): Name of the FPGA.
         package (string): Name of the data source
     Examples:
-        >>> siliconcompiler.FPGA(chip, "lattice_ice40")
+        >>> siliconcompiler.FPGA("lattice_ice40")
         Creates a flow object with name "lattice_ice40".
     """
 
@@ -119,17 +120,16 @@ class Library(PackageChip):
     This inherits all methods from :class:`~siliconcompiler.Chip`.
 
     Args:
-        chip (Chip): A real only copy of the parent chip.
         name (string): Name of the library.
         package (string): Name of the data source
         auto_enable (boolean): If True, will automatically be added to ['option','library'].
             This is only valid for non-logiclibs and macrolibs
     Examples:
-        >>> siliconcompiler.Library(chip, "asap7sc7p5t")
+        >>> siliconcompiler.Library("asap7sc7p5t")
         Creates a library object with name "asap7sc7p5t".
     """
-    def __init__(self, chip, name, package=None, auto_enable=False):
-        super().__init__(chip, name, package=package)
+    def __init__(self, *args, package=None, auto_enable=False):
+        super().__init__(*args, package=package)
 
         self.__auto_enable = auto_enable
 
@@ -146,15 +146,15 @@ class Flow(Chip):
     This inherits all methods from :class:`~siliconcompiler.Chip`.
 
     Args:
-        chip (Chip): A real only copy of the parent chip.
         name (string): Name of the flow.
     Examples:
-        >>> siliconcompiler.Flow(chip, "asicflow")
+        >>> siliconcompiler.Flow("asicflow")
         Creates a flow object with name "asicflow".
     """
-    def __init__(self, chip, name):
-        super().__init__(name)
-        self.logger = chip.logger
+    def __init__(self, *args):
+        super().__init__(args[-1])
+        if len(args) == 2:
+            self.logger.warning(f'passing Chip object to {type(self)} is deprecated')
 
 
 class Checklist(Chip):
@@ -166,12 +166,12 @@ class Checklist(Chip):
     This inherits all methods from :class:`~siliconcompiler.Chip`.
 
     Args:
-        chip (Chip): A real only copy of the parent chip.
         name (string): Name of the checklist.
     Examples:
-        >>> siliconcompiler.Checklist(chip, "tapeout")
+        >>> siliconcompiler.Checklist("tapeout")
         Creates a checklist object with name "tapeout".
     """
-    def __init__(self, chip, name):
-        super().__init__(name)
-        self.logger = chip.logger
+    def __init__(self, *args):
+        super().__init__(args[-1])
+        if len(args) == 2:
+            self.logger.warning(f'passing Chip object to {type(self)} is deprecated')

{siliconcompiler-0.26.5.dist-info → siliconcompiler-0.27.1.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: siliconcompiler
-Version: 0.26.5
+Version: 0.27.1
 Summary: A compiler framework that automates translation from source code to silicon.
 Author-email: Andreas Olofsson <andreas.d.olofsson@gmail.com>
 License: Apache License 2.0
@@ -30,6 +30,7 @@ Requires-Dist: fasteners ==0.19
 Requires-Dist: fastjsonschema ==2.20.0
 Requires-Dist: docker ==7.1.0
 Requires-Dist: sc-surelog ==1.84.1
+Requires-Dist: orjson ==3.10.7
 Requires-Dist: streamlit ==1.37.1
 Requires-Dist: streamlit-agraph ==0.0.45
 Requires-Dist: streamlit-tree-select ==0.0.5
@@ -90,15 +91,16 @@ SiliconCompiler is available as wheel packages on PyPI for macOS, Windows and
 Linux platforms. For working Python 3.8-3.12 environment, just use pip.
 
 ```sh
-python -m pip install --upgrade siliconcompiler
+python3 -m pip install --upgrade siliconcompiler
 ```
 
-Converting RTL into DRC clean GDS takes less than 10 lines of simple Python code.
+Converting RTL into DRC clean GDS takes 10 lines of simple Python code.
 
 ```python
-import siliconcompiler                             # import python package
-chip = siliconcompiler.Chip('heartbeat')           # create chip object
-chip.load_target('skywater130_demo')               # load a pre-defined target
+from siliconcompiler import Chip                   # import python package
+from siliconcompiler.targets import skywater130_demo
+chip = Chip('heartbeat')                           # create chip object
+chip.use(skywater130_demo)                         # load a pre-defined target
 chip.input('heartbeat.v')                          # set input sources
 chip.clock('clk', period=10)                       # set constraints
 chip.set('option','remote', True)                  # enable remote execution
@@ -161,8 +163,8 @@ To install the project from source (recommended for developers only).
 ```bash
 git clone https://github.com/siliconcompiler/siliconcompiler
 cd siliconcompiler
-python -m pip install -e .             # Required install step
-python -m pip install -e .[docs,test]  # Optional install step for generating docs and running tests
+python3 -m pip install -e .             # Required install step
+python3 -m pip install -e .[docs,test]  # Optional install step for generating docs and running tests
 ```
 
 # EDA Tool Installation