siliconcompiler 0.26.5__py3-none-any.whl → 0.27.1__py3-none-any.whl

siliconcompiler/_metadata.py

@@ -1,5 +1,5 @@
 # Version number following semver standard.
-version = '0.26.5'
+version = '0.27.1'
 
 # Default server address for remote runs, if unspecified.
 default_server = 'https://server.siliconcompiler.com'

siliconcompiler/apps/sc.py

@@ -39,9 +39,11 @@ def main():
 
     # Read command-line inputs and generate Chip objects to run the flow on.
     try:
-        chip.create_cmdline(progname,
-                            description=description,
-                            input_map=get_default_iomap())
+        args = chip.create_cmdline(progname,
+                                   description=description,
+                                   input_map=get_default_iomap())
+    except SiliconCompilerError:
+        return 1
     except Exception as e:
         chip.logger.error(e)
         return 1
@@ -69,8 +71,8 @@ def main():
         chip.set('design', topmodule)
 
     # Set demo target if none specified
-    if not chip.get('option', 'target'):
-        chip.load_target(skywater130_demo)
+    if 'target' not in args or not args['target']:
+        chip.use(skywater130_demo)
 
     try:
         # Run flow

siliconcompiler/apps/sc_issue.py

@@ -4,7 +4,6 @@ import os
 import siliconcompiler
 import tarfile
 import json
-import importlib
 from siliconcompiler.scheduler import _runtask, _executenode
 from siliconcompiler.issue import generate_testcase
 from siliconcompiler.tools._common import get_tool_task
@@ -18,7 +17,8 @@ def main():
                   '-arg_index',
                   '-tool_task_var',
                   '-tool_task_option',
-                  '-loglevel']
+                  '-loglevel',
+                  '-use']
     description = """
 -----------------------------------------------------------
 Restricted SC app that generates a sharable testcase from a
@@ -54,11 +54,6 @@ To run a testcase, use:
                  'help': 'run a provided testcase',
                  'sc_print': False},
 
-        '-use': {'action': 'append',
-                 'help': 'modules to load into test run',
-                 'metavar': '<module>',
-                 'sc_print': False},
-
         '-add_library': {'action': 'append',
                          'help': 'library to include in the testcase, if not provided all '
                                  'libraries will be added according to the -exclude_libraries flag',
@@ -155,15 +150,6 @@ To run a testcase, use:
         chip.logger.info(f"Changing {builddir_key} to '{new_builddir}'")
         chip.set(*builddir_key, new_builddir)
 
-        if switches['use']:
-            for use in switches['use']:
-                try:
-                    module = importlib.import_module(use)
-                    chip.logger.info(f"Loading '{use}' module")
-                    chip.use(module)
-                except ModuleNotFoundError:
-                    chip.logger.error(f"Unable to use '{use}' module")
-
         # Run task
         # Rerun setup task, assumed to be running in its own thread so
         # multiprocess is not needed

siliconcompiler/checklists/oh_tapeout.py

@@ -1,14 +1,14 @@
 import siliconcompiler
 
 
-def setup(chip):
+def setup():
     '''Subset of OH! library tapeout checklist.
 
     https://github.com/aolofsson/oh/blob/master/docs/tapeout_checklist.md
     '''
     standard = 'oh_tapeout'
 
-    checklist = siliconcompiler.Checklist(chip, standard)
+    checklist = siliconcompiler.Checklist(standard)
 
     # Automated
     checklist.set('checklist', standard, 'drc_clean', 'description',

siliconcompiler/core.py

@@ -16,6 +16,7 @@ import textwrap
 import graphviz
 import codecs
 import copy
+from inspect import getfullargspec
 from siliconcompiler.remote import client
 from siliconcompiler.schema import Schema, SCHEMA_VERSION
 from siliconcompiler.schema import utils as schema_utils
@@ -34,6 +35,7 @@ from siliconcompiler.flowgraph import _get_flowgraph_nodes, nodes_to_execute, \
     _get_flowgraph_execution_order, _check_flowgraph_io, \
     _get_flowgraph_information
 from siliconcompiler.tools._common import get_tool_task
+from types import FunctionType, ModuleType
 
 
 class Chip:
@@ -226,6 +228,7 @@ class Chip:
             log_format.append('%(lineno)-4s')
 
         if in_run:
+            max_column_width = 20
             # Figure out how wide to make step and index fields
             max_step_len = 1
             max_index_len = 1
@@ -235,7 +238,8 @@ class Chip:
             for future_step, future_index in nodes_to_run:
                 max_step_len = max(len(future_step), max_step_len)
                 max_index_len = max(len(future_index), max_index_len)
-            max_step_len = min(max_step_len, 20)
+            max_step_len = min(max_step_len, max_column_width)
+            max_index_len = min(max_index_len, max_column_width)
 
             jobname = self.get('option', 'jobname')
 
@@ -244,9 +248,9 @@ class Chip:
             if index is None:
                 index = '-' * max(max_index_len // 4, 1)
 
-            log_format.append(jobname)
+            log_format.append(utils.truncate_text(jobname, max_column_width))
             log_format.append(f'{utils.truncate_text(step, max_step_len): <{max_step_len}}')
-            log_format.append(f'{index: >{max_index_len}}')
+            log_format.append(f'{utils.truncate_text(index, max_step_len): >{max_index_len}}')
 
         log_format.append('%(message)s')
         logformat = '| ' + ' | '.join(log_format)
@@ -298,7 +302,7 @@ class Chip:
          2. read_manifest([cfg])
          3. read compiler inputs
          4. all other switches
-         5. load_target('target')
+         5. use(target)
 
         The cmdline interface is implemented using the Python argparse package
         and the following use restrictions apply.
@@ -360,9 +364,12 @@ class Chip:
                 return 'O' + item
             return item
 
-        def post_process(cmdargs):
+        def post_process(cmdargs, extra_params):
             # Ensure files and dir packages are set
             for key in self.allkeys():
+                if 'default' in key:
+                    continue
+
                 paramtype = self.get(*key, field='type')
                 if 'file' not in paramtype and 'dir' not in paramtype:
                     continue
@@ -370,6 +377,8 @@ class Chip:
                 is_list = '[' in paramtype
 
                 for vals, step, index in self.schema._getvals(*key):
+                    if not vals:
+                        continue
                     if self.get(*key, field='pernode') != 'never':
                         if step is None:
                             step = Schema.GLOBAL_KEY
@@ -387,13 +396,58 @@ class Chip:
                     self.set(*key, packages, field='package', step=step, index=index)
 
             # Read in target if set
-            if 'option_target' in cmdargs:
-                # running target command
-                self.load_target(cmdargs['option_target'])
+            if "target" in extra_params:
+                if extra_params["target"]:
+                    # running target command
+                    # Search order "{name}", and "siliconcompiler.targets.{name}"
+                    modules = []
+                    module = extra_params["target"]
+                    for mod_name in [module, f'siliconcompiler.targets.{module}']:
+                        mod = self._load_module(mod_name)
+                        if mod:
+                            modules.append(mod)
+
+                    if len(modules) == 0:
+                        raise SiliconCompilerError(f'Could not find target {module}', chip=self)
+
+                    self.use(modules[0])
+                    extra_params["target"] = modules[0].__name__
+
+            if "use" in extra_params:
+                if extra_params["use"]:
+                    for use in extra_params["use"]:
+                        mod = self._load_module(use)
+                        if mod is not None:
+                            self.use(mod)
+                        else:
+                            raise ValueError(f'{use} is not a valid module.')
+                del extra_params["use"]
+
+            return extra_params
 
         if not progname:
             progname = self.design
 
+        if not additional_args:
+            additional_args = {}
+
+        if "-target" in additional_args:
+            raise ValueError('-target cannot be used as an additional argument')
+
+        additional_args["-target"] = {
+            "help": "target to load",
+            "metavar": "<target>"
+        }
+
+        if "-use" in additional_args:
+            raise ValueError('-use cannot be used as an additional argument')
+
+        additional_args["-use"] = {
+            "action": "append",
+            "help": "modules to load",
+            "metavar": "<module>"
+        }
+
         try:
             return self.schema.create_cmdline(
                 progname=progname,
@@ -464,53 +518,18 @@ class Chip:
         """
         Loads a target module and runs the setup() function.
 
-        The function searches the installed Python packages for <name> and
-        siliconcompiler.targets.<name> and runs the setup function in that module
-        if found.
-
         Args:
-            module (str or module): Module name
+            module (module): Module name
             **kwargs (str): Options to pass along to the target
 
         Examples:
-            >>> chip.load_target('freepdk45_demo', syn_np=5)
+            >>> chip.use(freepdk45_demo, syn_np=5)
             Loads the 'freepdk45_demo' target with 5 parallel synthesis tasks
         """
 
-        if not inspect.ismodule(module):
-            # Search order "{name}", and "siliconcompiler.targets.{name}"
-            modules = []
-            for mod_name in [module, f'siliconcompiler.targets.{module}']:
-                mod = self._load_module(mod_name)
-                if mod:
-                    modules.append(mod)
-
-            if len(modules) == 0:
-                raise SiliconCompilerError(f'Could not find target {module}', chip=self)
-        else:
-            modules = [module]
-
-        # Check for setup in modules
-        load_function = None
-        for mod in modules:
-            load_function = getattr(mod, 'setup', None)
-            if load_function:
-                module_name = mod.__name__
-                break
-
-        if not load_function:
-            raise SiliconCompilerError(
-                f'Could not find setup function for {module} target',
-                chip=self)
-
-        try:
-            load_function(self, **kwargs)
-        except Exception as e:
-            self.logger.error(f'Failed to load target {module}')
-            raise e
+        self.logger.warning(".load_target is deprecated, use .use() instead.")
 
-        # Record target
-        self.set('option', 'target', module_name)
+        self.use(module, **kwargs)
 
     ##########################################################################
     def use(self, module, **kwargs):
@@ -526,6 +545,8 @@ class Chip:
              - Action
            * - Module with setup function
              - Call `setup()` and import returned objects
+           * - A setup function
+             - Call `function()` and import returned objects
            * - Chip
              - Import as a library
            * - Library
@@ -547,18 +568,45 @@ class Chip:
         from siliconcompiler import Library
         from siliconcompiler import Checklist
 
-        setup_func = getattr(module, 'setup', None)
-        if (setup_func):
-            # Call the module setup function.
-            try:
-                use_modules = setup_func(self, **kwargs)
-            except Exception as e:
-                self.logger.error(f'Unable to run setup() for {module.__name__}')
-                raise e
+        func = None
+
+        if module is None:
+            raise ValueError('module parameter cannot be None')
+
+        if isinstance(module, ModuleType):
+            func = getattr(module, 'setup', None)
+            if func is None:
+                raise NotImplementedError(f'{module} does not have a setup()')
+        elif isinstance(module, FunctionType):
+            func = module
         else:
             # Import directly
             use_modules = module
 
+        if func:
+            # Call the setup function.
+            try:
+                func_spec = getfullargspec(func)
+
+                args_len = len(func_spec.args or []) - len(func_spec.defaults or [])
+
+                args = []
+                if args_len == 1:
+                    args.append(self)
+                elif args_len > 1:
+                    raise RuntimeError('function signature cannot have more than 1 argument')
+                use_modules = func(*args, **kwargs)
+
+                if args_len == 1 and use_modules:
+                    self.logger.warning('Target returned items, which it should not have')
+            except Exception as e:
+                self.logger.error(f'Unable to run {func.__name__}() for {module.__name__}')
+                raise e
+
+        if use_modules is None:
+            # loaded a target so done
+            return
+
         # Make it a list for consistency
         if not isinstance(use_modules, list):
             use_modules = [use_modules]
@@ -3040,7 +3088,7 @@ class Chip:
 
         try:
             from siliconcompiler.flows import showflow
-            self.use(showflow, filetype=filetype, screenshot=screenshot)
+            self.use(showflow, filetype=filetype, screenshot=screenshot, showtools=self._showtools)
         except Exception as e:
             self.logger.error(f"Flow setup failed: {e}")
             # restore environment

siliconcompiler/flows/_common.py

@@ -17,7 +17,7 @@ def _make_docs(chip):
     chip.set('input', 'hll', 'bsv', 'test')
     chip.set('input', 'hll', 'scala', 'test')
 
-    chip.load_target(freepdk45_demo)
+    chip.use(freepdk45_demo)
 
 
 def __get_frontends(allow_system_verilog):
@@ -36,7 +36,7 @@ def __get_frontends(allow_system_verilog):
     }
 
 
-def setup_multiple_frontends(chip, flow, allow_system_verilog=False):
+def setup_multiple_frontends(flow, allow_system_verilog=False):
     '''
     Sets of multiple frontends if different frontends are required.
 

siliconcompiler/flows/asicflow.py

@@ -22,14 +22,13 @@ from siliconcompiler.tools.builtin import minimum
 def make_docs(chip):
     n = 3
     _make_docs(chip)
-    return setup(chip, syn_np=n, floorplan_np=n, physyn_np=n, place_np=n, cts_np=n, route_np=n)
+    return setup(syn_np=n, floorplan_np=n, physyn_np=n, place_np=n, cts_np=n, route_np=n)
 
 
 ###########################################################################
 # Flowgraph Setup
 ############################################################################
-def setup(chip,
-          flowname='asicflow',
+def setup(flowname='asicflow',
           syn_np=1,
           floorplan_np=1,
           physyn_np=1,
@@ -68,7 +67,7 @@ def setup(chip,
     * route_np : Number of parallel routing jobs to launch
     '''
 
-    flow = siliconcompiler.Flow(chip, flowname)
+    flow = siliconcompiler.Flow(flowname)
 
     # Linear flow, up until branch to run parallel verification steps.
     longpipe = ['syn',
@@ -126,7 +125,7 @@ def setup(chip,
         flowtasks.append((step, tasks[step]))
 
     # Programmatically build linear portion of flowgraph and fanin/fanout args
-    prevstep = setup_multiple_frontends(chip, flow)
+    prevstep = setup_multiple_frontends(flow)
     for step, task in flowtasks:
         fanout = 1
         if step in np:

siliconcompiler/flows/asictopflow.py

@@ -6,14 +6,14 @@ from siliconcompiler.tools.klayout import export
 from siliconcompiler.flows._common import _make_docs
 
 
-def setup(chip):
+def setup():
     '''A flow for stitching together hardened blocks without doing any automated
     place-and-route.
 
     This flow generates a GDS and a netlist for passing to a
     verification/signoff flow.
     '''
-    flow = siliconcompiler.Flow(chip, 'asictopflow')
+    flow = siliconcompiler.Flow('asictopflow')
 
     flow.node(flow.design, 'import', surelog_parse)
     flow.node(flow.design, 'syn', syn_asic)
@@ -33,6 +33,6 @@ def setup(chip):
 if __name__ == "__main__":
     chip = siliconcompiler.Chip('design')
     _make_docs(chip)
-    flow = setup(chip)
+    flow = setup()
     chip.use(flow)
     chip.write_flowgraph(f"{flow.top()}.png", flow=flow.top())

siliconcompiler/flows/dvflow.py

@@ -10,14 +10,13 @@ from siliconcompiler.tools.execute import exec_input
 ############################################################################
 def make_docs(chip):
     chip.set('input', 'rtl', 'netlist', 'test')
-    return setup(chip, np=5)
+    return setup(np=5)
 
 
 #############################################################################
 # Flowgraph Setup
 #############################################################################
-def setup(chip,
-          flowname='dvflow',
+def setup(flowname='dvflow',
           tool='icarus',
           np=1):
     '''
@@ -35,7 +34,7 @@ def setup(chip,
     This flow is a WIP
     '''
 
-    flow = siliconcompiler.Flow(chip, flowname)
+    flow = siliconcompiler.Flow(flowname)
 
     tasks = {
         'compile': None,

siliconcompiler/flows/fpgaflow.py

@@ -23,14 +23,13 @@ from siliconcompiler.tools.nextpnr import apr as nextpnr_apr
 ############################################################################
 def make_docs(chip):
     _make_docs(chip)
-    chip.set('fpga', 'partname', 'example_arch')
-    return setup(chip)
+    return setup(partname='example_arch')
 
 
 ############################################################################
 # Flowgraph Setup
 ############################################################################
-def setup(chip, flowname='fpgaflow', fpgaflow_type=None, partname=None):
+def setup(flowname='fpgaflow', fpgaflow_type=None, partname=None):
     '''
     A configurable FPGA compilation flow.
 
@@ -60,10 +59,7 @@ def setup(chip, flowname='fpgaflow', fpgaflow_type=None, partname=None):
           flow instead of one selected from the partname set in the schema.
     '''
 
-    flow = siliconcompiler.Flow(chip, flowname)
-
-    if not partname:
-        partname = chip.get('fpga', 'partname')
+    flow = siliconcompiler.Flow(flowname)
 
     if fpgaflow_type:
         flow_pipe = flow_lookup_by_type(fpgaflow_type)
@@ -71,7 +67,7 @@ def setup(chip, flowname='fpgaflow', fpgaflow_type=None, partname=None):
         flow_pipe = flow_lookup(partname)
 
     # Minimal setup
-    prevstep = setup_multiple_frontends(chip, flow)
+    prevstep = setup_multiple_frontends(flow)
     for step, tool_module in flow_pipe:
         # Flow
         flow.node(flowname, step, tool_module)

siliconcompiler/flows/generate_openroad_rcx.py

@@ -11,20 +11,20 @@ from siliconcompiler.flows._common import _make_docs
 ############################################################################
 def make_docs(chip):
     _make_docs(chip)
-    return setup(chip, corners=5)
+    return setup(corners=5)
 
 
 ###########################################################################
 # Flowgraph Setup
 ############################################################################
-def setup(chip, extraction_task=None, corners=1, serial_extraction=False):
+def setup(extraction_task=None, corners=1, serial_extraction=False):
     '''
     Flow to generate the OpenRCX decks needed by OpenROAD to do parasitic
     extraction.
     '''
 
     flowname = 'generate_rcx'
-    flow = siliconcompiler.Flow(chip, flowname)
+    flow = siliconcompiler.Flow(flowname)
 
     if not extraction_task:
         chip.logger.warning('Valid extraction not specified, defaulting to builtin/nop')

siliconcompiler/flows/lintflow.py

@@ -8,13 +8,13 @@ from siliconcompiler.tools.slang import lint as slang_lint
 ###########################################################################
 # Flowgraph Setup
 ############################################################################
-def setup(chip, tool='verilator'):
+def setup(tool='verilator'):
     '''
     An RTL linting flow.
     '''
 
     flowname = 'lintflow'
-    flow = siliconcompiler.Flow(chip, flowname)
+    flow = siliconcompiler.Flow(flowname)
 
     if tool == 'verilator':
         flow.node(flowname, 'lint', verilator_lint)
@@ -30,6 +30,6 @@ def setup(chip, tool='verilator'):
 if __name__ == "__main__":
     chip = siliconcompiler.Chip('design')
     _make_docs(chip)
-    flow = setup(chip)
+    flow = setup()
     chip.use(flow)
     chip.write_flowgraph(f"{flow.top()}.png", flow=flow.top())

siliconcompiler/flows/screenshotflow.py

@@ -11,10 +11,10 @@ def make_docs(chip):
     chip.set('tool', 'klayout', 'task', 'screenshot', 'var', 'ybins', 2)
     chip.set('tool', 'montage', 'task', 'tile', 'var', 'xbins', 2)
     chip.set('tool', 'montage', 'task', 'tile', 'var', 'ybins', 2)
-    return setup(chip)
+    return setup()
 
 
-def setup(chip, flowname='screenshotflow'):
+def setup(flowname='screenshotflow'):
     '''
     Flow to generate a high resolution design image from a GDS or OAS file.
 
@@ -31,7 +31,7 @@ def setup(chip, flowname='screenshotflow'):
         ('merge', tile)
     ]
 
-    flow = Flow(chip, flowname)
+    flow = Flow(flowname)
 
     prevstep = None
     for step, task in pipe:

siliconcompiler/flows/showflow.py

@@ -1,19 +1,20 @@
 import siliconcompiler
 from siliconcompiler import SiliconCompilerError
+from siliconcompiler.targets import freepdk45_demo
 
 
 ############################################################################
 # DOCS
 ############################################################################
 def make_docs(chip):
-    chip.load_target('freepdk45_demo')
-    return setup(chip, filetype='gds', np=3)
+    chip.use(freepdk45_demo)
+    return setup(filetype='gds', showtools=chip._showtools, np=3)
 
 
 ###########################################################################
 # Flowgraph Setup
 ############################################################################
-def setup(chip, flowname='showflow', filetype=None, screenshot=False, np=1):
+def setup(flowname='showflow', filetype=None, screenshot=False, showtools=None, np=1):
     '''
     A flow to show the output files generated from other flows.
 
@@ -25,18 +26,22 @@ def setup(chip, flowname='showflow', filetype=None, screenshot=False, np=1):
 
     * np : Number of parallel show jobs to launch
     * screenshot : true/false, indicate if this should be configured as a screenshot
+    * showtools: dictionary of file extensions with the associated show and screenshot tasks
     '''
 
-    flow = siliconcompiler.Flow(chip, flowname)
+    flow = siliconcompiler.Flow(flowname)
 
     # Get required parameters first
     if not filetype:
         raise ValueError('filetype is a required argument')
 
-    if filetype not in chip._showtools:
+    if not showtools:
+        raise ValueError('showtools is a required argument')
+
+    if filetype not in showtools:
         raise SiliconCompilerError(f'Show tool for {filetype} is not defined.')
 
-    show_tool = chip._showtools[filetype]
+    show_tool = showtools[filetype]
 
     stepname = 'show'
     if screenshot:

siliconcompiler/flows/signoffflow.py

@@ -9,10 +9,10 @@ from siliconcompiler.tools.builtin import join
 
 def make_docs(chip):
     chip.set('input', 'netlist', 'verilog', 'test')
-    return setup(chip)
+    return setup()
 
 
-def setup(chip):
+def setup():
     '''A flow for running LVS/DRC signoff on a GDS layout.
 
     Inputs must be passed to this flow as follows::
@@ -22,7 +22,7 @@ def setup(chip):
     '''
     flowname = 'signoffflow'
 
-    flow = siliconcompiler.Flow(chip, flowname)
+    flow = siliconcompiler.Flow(flowname)
 
     # nop import since we don't need to pull in any sources
     flow.node(flowname, 'import', nop)