qiskit 1.3.0__cp39-abi3-win32.whl → 1.3.0b1__cp39-abi3-win32.whl

qiskit/transpiler/__init__.py

@@ -106,9 +106,8 @@ also add initial logical optimization prior to routing, you would do something l
 .. code-block:: python
 
     import numpy as np
-    from qiskit.providers.fake_provider import GenericBackendV2
     from qiskit.circuit.library import HGate, PhaseGate, RXGate, TdgGate, TGate, XGate
-    from qiskit.transpiler import PassManager, generate_preset_pass_manager
+    from qiskit.transpiler import PassManager
     from qiskit.transpiler.passes import (
         ALAPScheduleAnalysis,
         CXCancellation,
@@ -116,7 +115,6 @@ also add initial logical optimization prior to routing, you would do something l
         PadDynamicalDecoupling,
     )
 
-    backend = GenericBackendV2(num_qubits=5)
     dd_sequence = [XGate(), XGate()]
     scheduling_pm = PassManager(
         [
@@ -137,9 +135,6 @@ also add initial logical optimization prior to routing, you would do something l
         ]
     )
 
-    pass_manager = generate_preset_pass_manager(
-        optimization_level=0
-    )
 
     # Add pre-layout stage to run extra logical optimization
     pass_manager.pre_layout = logical_opt
@@ -258,7 +253,7 @@ descriptions of the instructions it supports:
     )
     print(target)
 
-.. code-block:: text
+.. parsed-literal::
 
     Target
     Number of qubits: 3
@@ -583,7 +578,7 @@ original.  This can be verified by checking the depth of both circuits:
 
    print('Original depth:', qc.depth(), 'Decomposed Depth:', qc_basis.depth())
 
-.. code-block:: text
+.. parsed-literal::
 
     Original depth: 4 Decomposed Depth: 10
 
@@ -603,7 +598,7 @@ It is important to highlight two special cases:
 
       print(backend.operation_names)
 
-   .. code-block:: text
+   .. parsed-literal::
 
       ['id', 'rz', 'sx', 'x', 'cx', 'measure', 'delay']
 
@@ -1022,7 +1017,7 @@ classical register wires, though theoretically two conditional instructions
 conditioned on the same register could commute, i.e. read-access to the
 classical register doesn't change its state.
 
-.. code-block:: text
+.. parsed-literal::
 
     qc = QuantumCircuit(2, 1)
     qc.delay(100, 0)
@@ -1033,7 +1028,7 @@ The scheduler SHOULD comply with the above topological ordering policy of the
 DAG circuit.
 Accordingly, the `asap`-scheduled circuit will become
 
-.. code-block:: text
+.. parsed-literal::
 
          ┌────────────────┐   ┌───┐
     q_0: ┤ Delay(100[dt]) ├───┤ X ├──────────────
@@ -1060,7 +1055,7 @@ then a discriminated (D) binary value is moved to the classical register (C).
 A sequence from t0 to t1 of the measure instruction interval could be
 modeled as follows:
 
-.. code-block:: text
+.. parsed-literal::
 
     Q ░▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒░
     B ░░▒▒▒▒▒▒▒▒░░░░░░░░░
@@ -1075,7 +1070,7 @@ and the :class:`.Clbit` is only occupied at the very end of the interval.
 The lack of precision representing the physical model may induce
 edge cases in the scheduling:
 
-.. code-block:: text
+.. parsed-literal::
 
             ┌───┐
     q_0: ───┤ X ├──────
@@ -1094,7 +1089,7 @@ is unchanged during the application of the stimulus, so two nodes are
 simultaneously operated.
 If one tries to `alap`-schedule this circuit, it may return following circuit:
 
-.. code-block:: text
+.. parsed-literal::
 
          ┌────────────────┐   ┌───┐
     q_0: ┤ Delay(500[dt]) ├───┤ X ├──────
@@ -1110,7 +1105,7 @@ It looks like the topological ordering between the nodes is flipped in the
 scheduled view.
 This behavior can be understood by considering the control flow model described above,
 
-.. code-block:: text
+.. parsed-literal::
 
     : Quantum Circuit, first-measure
     0 ░░░░░░░░░░░░▒▒▒▒▒▒░
@@ -1142,7 +1137,7 @@ be copied to the pass manager property set before the pass is called.
 
 Due to default latencies, the `alap`-scheduled circuit of above example may become
 
-.. code-block:: text
+.. parsed-literal::
 
             ┌───┐
     q_0: ───┤ X ├──────
@@ -1156,8 +1151,7 @@ If the backend microarchitecture supports smart scheduling of the control flow
 instructions, such as separately scheduling qubits and classical registers,
 the insertion of the delay yields an unnecessarily longer total execution time.
 
-.. code-block:: text
-
+.. parsed-literal::
     : Quantum Circuit, first-XGate
     0 ░▒▒▒░░░░░░░░░░░░░░░
     1 ░▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒░
@@ -1174,7 +1168,7 @@ However, this result is much more intuitive in the topological ordering view.
 If a finite conditional latency value is provided, for example, 30 dt, the circuit
 is scheduled as follows:
 
-.. code-block:: text
+.. parsed-literal::
 
          ┌───────────────┐   ┌───┐
     q_0: ┤ Delay(30[dt]) ├───┤ X ├──────
@@ -1186,8 +1180,7 @@ is scheduled as follows:
 
 with the timing model:
 
-.. code-block:: text
-
+.. parsed-literal::
     : Quantum Circuit, first-xgate
     0 ░░▒▒▒░░░░░░░░░░░░░░░
     1 ░░▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒▒░

qiskit/transpiler/basepasses.py

@@ -201,7 +201,7 @@ class TransformationPass(BasePass):  # pylint: disable=abstract-method
         if state.workflow_status.previous_run == RunState.SUCCESS:
             if isinstance(new_dag, DAGCircuit):
                 # Copy calibration data from the original program
-                new_dag._calibrations_prop = passmanager_ir._calibrations_prop
+                new_dag.calibrations = passmanager_ir.calibrations
             else:
                 raise TranspilerError(
                     "Transformation passes should return a transformed dag."

qiskit/transpiler/passes/__init__.py

@@ -93,7 +93,6 @@ Optimizations
    NormalizeRXAngle
    OptimizeAnnotated
    Split2QUnitaries
-   RemoveIdentityEquivalent
 
 Calibration
 =============
@@ -248,7 +247,6 @@ from .optimization import OptimizeCliffords
 from .optimization import ElidePermutations
 from .optimization import NormalizeRXAngle
 from .optimization import OptimizeAnnotated
-from .optimization import RemoveIdentityEquivalent
 from .optimization import Split2QUnitaries
 
 # circuit analysis