pyvex 9.2.189__cp311-cp311-macosx_11_0_arm64.whl

pyvex/include/libvex_guest_offsets.h

@@ -0,0 +1,941 @@
+#define OFFSET_x86_EAX 0x8
+#define OFFSET_x86_ECX 0xc
+#define OFFSET_x86_EDX 0x10
+#define OFFSET_x86_EBX 0x14
+#define OFFSET_x86_ESP 0x18
+#define OFFSET_x86_EBP 0x1c
+#define OFFSET_x86_ESI 0x20
+#define OFFSET_x86_EDI 0x24
+#define OFFSET_x86_CC_OP 0x28
+#define OFFSET_x86_CC_DEP1 0x2c
+#define OFFSET_x86_CC_DEP2 0x30
+#define OFFSET_x86_CC_NDEP 0x34
+#define OFFSET_x86_DFLAG 0x38
+#define OFFSET_x86_IDFLAG 0x3c
+#define OFFSET_x86_ACFLAG 0x40
+#define OFFSET_x86_EIP 0x44
+#define OFFSET_x86_FPREG 0x48
+#define OFFSET_x86_FPTAG 0x88
+#define OFFSET_x86_FPROUND 0x90
+#define OFFSET_x86_FC3210 0x94
+#define OFFSET_x86_FTOP 0x98
+#define OFFSET_x86_SSEROUND 0x9c
+#define OFFSET_x86_XMM0 0xa0
+#define OFFSET_x86_XMM1 0xb0
+#define OFFSET_x86_XMM2 0xc0
+#define OFFSET_x86_XMM3 0xd0
+#define OFFSET_x86_XMM4 0xe0
+#define OFFSET_x86_XMM5 0xf0
+#define OFFSET_x86_XMM6 0x100
+#define OFFSET_x86_XMM7 0x110
+#define OFFSET_x86_CS 0x120
+#define OFFSET_x86_DS 0x122
+#define OFFSET_x86_ES 0x124
+#define OFFSET_x86_FS 0x126
+#define OFFSET_x86_GS 0x128
+#define OFFSET_x86_SS 0x12a
+#define OFFSET_x86_LDT 0x130
+#define OFFSET_x86_GDT 0x138
+#define OFFSET_x86_EMNOTE 0x140
+#define OFFSET_x86_CMSTART 0x144
+#define OFFSET_x86_CMLEN 0x148
+#define OFFSET_x86_NRADDR 0x14c
+#define OFFSET_x86_SC_CLASS 0x150
+#define OFFSET_x86_IP_AT_SYSCALL 0x154
+#define OFFSET_amd64_RAX 0x10
+#define OFFSET_amd64_RBX 0x28
+#define OFFSET_amd64_RCX 0x18
+#define OFFSET_amd64_RDX 0x20
+#define OFFSET_amd64_RSI 0x40
+#define OFFSET_amd64_RDI 0x48
+#define OFFSET_amd64_RSP 0x30
+#define OFFSET_amd64_RBP 0x38
+#define OFFSET_amd64_R8 0x50
+#define OFFSET_amd64_R9 0x58
+#define OFFSET_amd64_R10 0x60
+#define OFFSET_amd64_R11 0x68
+#define OFFSET_amd64_R12 0x70
+#define OFFSET_amd64_R13 0x78
+#define OFFSET_amd64_R14 0x80
+#define OFFSET_amd64_R15 0x88
+#define OFFSET_amd64_RIP 0xb8
+#define OFFSET_amd64_IP_AT_SYSCALL 0x410
+#define OFFSET_amd64_RAX 0x10
+#define OFFSET_amd64_RCX 0x18
+#define OFFSET_amd64_RDX 0x20
+#define OFFSET_amd64_RBX 0x28
+#define OFFSET_amd64_RSP 0x30
+#define OFFSET_amd64_RBP 0x38
+#define OFFSET_amd64_RSI 0x40
+#define OFFSET_amd64_RDI 0x48
+#define OFFSET_amd64_R8 0x50
+#define OFFSET_amd64_R9 0x58
+#define OFFSET_amd64_R10 0x60
+#define OFFSET_amd64_R11 0x68
+#define OFFSET_amd64_R12 0x70
+#define OFFSET_amd64_R13 0x78
+#define OFFSET_amd64_R14 0x80
+#define OFFSET_amd64_R15 0x88
+#define OFFSET_amd64_CC_OP 0x90
+#define OFFSET_amd64_CC_DEP1 0x98
+#define OFFSET_amd64_CC_DEP2 0xa0
+#define OFFSET_amd64_CC_NDEP 0xa8
+#define OFFSET_amd64_DFLAG 0xb0
+#define OFFSET_amd64_RIP 0xb8
+#define OFFSET_amd64_ACFLAG 0xc0
+#define OFFSET_amd64_IDFLAG 0xc8
+#define OFFSET_amd64_FS_CONST 0xd0
+#define OFFSET_amd64_SSEROUND 0xd8
+#define OFFSET_amd64_YMM0 0xe0
+#define OFFSET_amd64_YMM1 0x100
+#define OFFSET_amd64_YMM2 0x120
+#define OFFSET_amd64_YMM3 0x140
+#define OFFSET_amd64_YMM4 0x160
+#define OFFSET_amd64_YMM5 0x180
+#define OFFSET_amd64_YMM6 0x1a0
+#define OFFSET_amd64_YMM7 0x1c0
+#define OFFSET_amd64_YMM8 0x1e0
+#define OFFSET_amd64_YMM9 0x200
+#define OFFSET_amd64_YMM10 0x220
+#define OFFSET_amd64_YMM11 0x240
+#define OFFSET_amd64_YMM12 0x260
+#define OFFSET_amd64_YMM13 0x280
+#define OFFSET_amd64_YMM14 0x2a0
+#define OFFSET_amd64_YMM15 0x2c0
+#define OFFSET_amd64_YMM16 0x2e0
+#define OFFSET_amd64_CR0 0x300
+#define OFFSET_amd64_CR1 0x308
+#define OFFSET_amd64_CR2 0x310
+#define OFFSET_amd64_CR3 0x318
+#define OFFSET_amd64_CR4 0x320
+#define OFFSET_amd64_CR5 0x328
+#define OFFSET_amd64_CR6 0x330
+#define OFFSET_amd64_CR7 0x338
+#define OFFSET_amd64_CR8 0x340
+#define OFFSET_amd64_CR9 0x348
+#define OFFSET_amd64_CR10 0x350
+#define OFFSET_amd64_CR11 0x358
+#define OFFSET_amd64_CR12 0x360
+#define OFFSET_amd64_CR13 0x368
+#define OFFSET_amd64_CR14 0x370
+#define OFFSET_amd64_CR15 0x378
+#define OFFSET_amd64_FTOP 0x380
+#define OFFSET_amd64_FPREG 0x388
+#define OFFSET_amd64_FPTAG 0x3c8
+#define OFFSET_amd64_FPROUND 0x3d0
+#define OFFSET_amd64_FC3210 0x3d8
+#define OFFSET_amd64_EMNOTE 0x3e0
+#define OFFSET_amd64_CMSTART 0x3e8
+#define OFFSET_amd64_CMLEN 0x3f0
+#define OFFSET_amd64_NRADDR 0x3f8
+#define OFFSET_amd64_SC_CLASS 0x400
+#define OFFSET_amd64_GS_CONST 0x408
+#define OFFSET_amd64_IP_AT_SYSCALL 0x410
+#define OFFSET_amd64_CS 0x418
+#define OFFSET_amd64_DS 0x41a
+#define OFFSET_amd64_ES 0x41c
+#define OFFSET_amd64_FS 0x41e
+#define OFFSET_amd64_GS 0x420
+#define OFFSET_amd64_SS 0x422
+#define OFFSET_ppc32_GPR0 0x10
+#define OFFSET_ppc32_GPR1 0x14
+#define OFFSET_ppc32_GPR2 0x18
+#define OFFSET_ppc32_GPR3 0x1c
+#define OFFSET_ppc32_GPR4 0x20
+#define OFFSET_ppc32_GPR5 0x24
+#define OFFSET_ppc32_GPR6 0x28
+#define OFFSET_ppc32_GPR7 0x2c
+#define OFFSET_ppc32_GPR8 0x30
+#define OFFSET_ppc32_GPR9 0x34
+#define OFFSET_ppc32_GPR10 0x38
+#define OFFSET_ppc32_GPR11 0x3c
+#define OFFSET_ppc32_GPR12 0x40
+#define OFFSET_ppc32_GPR13 0x44
+#define OFFSET_ppc32_GPR14 0x48
+#define OFFSET_ppc32_GPR15 0x4c
+#define OFFSET_ppc32_GPR16 0x50
+#define OFFSET_ppc32_GPR17 0x54
+#define OFFSET_ppc32_GPR18 0x58
+#define OFFSET_ppc32_GPR19 0x5c
+#define OFFSET_ppc32_GPR20 0x60
+#define OFFSET_ppc32_GPR21 0x64
+#define OFFSET_ppc32_GPR22 0x68
+#define OFFSET_ppc32_GPR23 0x6c
+#define OFFSET_ppc32_GPR24 0x70
+#define OFFSET_ppc32_GPR25 0x74
+#define OFFSET_ppc32_GPR26 0x78
+#define OFFSET_ppc32_GPR27 0x7c
+#define OFFSET_ppc32_GPR28 0x80
+#define OFFSET_ppc32_GPR29 0x84
+#define OFFSET_ppc32_GPR30 0x88
+#define OFFSET_ppc32_GPR31 0x8c
+#define OFFSET_ppc32_VSR0 0x90
+#define OFFSET_ppc32_VSR1 0xa0
+#define OFFSET_ppc32_VSR2 0xb0
+#define OFFSET_ppc32_VSR3 0xc0
+#define OFFSET_ppc32_VSR4 0xd0
+#define OFFSET_ppc32_VSR5 0xe0
+#define OFFSET_ppc32_VSR6 0xf0
+#define OFFSET_ppc32_VSR7 0x100
+#define OFFSET_ppc32_VSR8 0x110
+#define OFFSET_ppc32_VSR9 0x120
+#define OFFSET_ppc32_VSR10 0x130
+#define OFFSET_ppc32_VSR11 0x140
+#define OFFSET_ppc32_VSR12 0x150
+#define OFFSET_ppc32_VSR13 0x160
+#define OFFSET_ppc32_VSR14 0x170
+#define OFFSET_ppc32_VSR15 0x180
+#define OFFSET_ppc32_VSR16 0x190
+#define OFFSET_ppc32_VSR17 0x1a0
+#define OFFSET_ppc32_VSR18 0x1b0
+#define OFFSET_ppc32_VSR19 0x1c0
+#define OFFSET_ppc32_VSR20 0x1d0
+#define OFFSET_ppc32_VSR21 0x1e0
+#define OFFSET_ppc32_VSR22 0x1f0
+#define OFFSET_ppc32_VSR23 0x200
+#define OFFSET_ppc32_VSR24 0x210
+#define OFFSET_ppc32_VSR25 0x220
+#define OFFSET_ppc32_VSR26 0x230
+#define OFFSET_ppc32_VSR27 0x240
+#define OFFSET_ppc32_VSR28 0x250
+#define OFFSET_ppc32_VSR29 0x260
+#define OFFSET_ppc32_VSR30 0x270
+#define OFFSET_ppc32_VSR31 0x280
+#define OFFSET_ppc32_VSR32 0x290
+#define OFFSET_ppc32_VSR33 0x2a0
+#define OFFSET_ppc32_VSR34 0x2b0
+#define OFFSET_ppc32_VSR35 0x2c0
+#define OFFSET_ppc32_VSR36 0x2d0
+#define OFFSET_ppc32_VSR37 0x2e0
+#define OFFSET_ppc32_VSR38 0x2f0
+#define OFFSET_ppc32_VSR39 0x300
+#define OFFSET_ppc32_VSR40 0x310
+#define OFFSET_ppc32_VSR41 0x320
+#define OFFSET_ppc32_VSR42 0x330
+#define OFFSET_ppc32_VSR43 0x340
+#define OFFSET_ppc32_VSR44 0x350
+#define OFFSET_ppc32_VSR45 0x360
+#define OFFSET_ppc32_VSR46 0x370
+#define OFFSET_ppc32_VSR47 0x380
+#define OFFSET_ppc32_VSR48 0x390
+#define OFFSET_ppc32_VSR49 0x3a0
+#define OFFSET_ppc32_VSR50 0x3b0
+#define OFFSET_ppc32_VSR51 0x3c0
+#define OFFSET_ppc32_VSR52 0x3d0
+#define OFFSET_ppc32_VSR53 0x3e0
+#define OFFSET_ppc32_VSR54 0x3f0
+#define OFFSET_ppc32_VSR55 0x400
+#define OFFSET_ppc32_VSR56 0x410
+#define OFFSET_ppc32_VSR57 0x420
+#define OFFSET_ppc32_VSR58 0x430
+#define OFFSET_ppc32_VSR59 0x440
+#define OFFSET_ppc32_VSR60 0x450
+#define OFFSET_ppc32_VSR61 0x460
+#define OFFSET_ppc32_VSR62 0x470
+#define OFFSET_ppc32_VSR63 0x480
+#define OFFSET_ppc32_CIA 0x490
+#define OFFSET_ppc32_LR 0x494
+#define OFFSET_ppc32_CTR 0x498
+#define OFFSET_ppc32_XER_SO 0x49c
+#define OFFSET_ppc32_XER_OV 0x49d
+#define OFFSET_ppc32_XER_CA 0x49e
+#define OFFSET_ppc32_XER_BC 0x49f
+#define OFFSET_ppc32_CR0_321 0x4a0
+#define OFFSET_ppc32_CR0_0 0x4a1
+#define OFFSET_ppc32_CR1_321 0x4a2
+#define OFFSET_ppc32_CR1_0 0x4a3
+#define OFFSET_ppc32_CR2_321 0x4a4
+#define OFFSET_ppc32_CR2_0 0x4a5
+#define OFFSET_ppc32_CR3_321 0x4a6
+#define OFFSET_ppc32_CR3_0 0x4a7
+#define OFFSET_ppc32_CR4_321 0x4a8
+#define OFFSET_ppc32_CR4_0 0x4a9
+#define OFFSET_ppc32_CR5_321 0x4aa
+#define OFFSET_ppc32_CR5_0 0x4ab
+#define OFFSET_ppc32_CR6_321 0x4ac
+#define OFFSET_ppc32_CR6_0 0x4ad
+#define OFFSET_ppc32_CR7_321 0x4ae
+#define OFFSET_ppc32_CR7_0 0x4af
+#define OFFSET_ppc32_FPROUND 0x4b0
+#define OFFSET_ppc32_DFPROUND 0x4b1
+#define OFFSET_ppc32_C_FPCC 0x4b2
+#define OFFSET_ppc32_VRSAVE 0x4b4
+#define OFFSET_ppc32_VSCR 0x4b8
+#define OFFSET_ppc32_EMNOTE 0x4bc
+#define OFFSET_ppc32_CMSTART 0x4c0
+#define OFFSET_ppc32_CMLEN 0x4c4
+#define OFFSET_ppc32_NRADDR 0x4c8
+#define OFFSET_ppc32_NRADDR_GPR2 0x4cc
+#define OFFSET_ppc32_REDIR_SP 0x4d0
+#define OFFSET_ppc32_REDIR_STACK 0x4d4
+#define OFFSET_ppc32_IP_AT_SYSCALL 0x554
+#define OFFSET_ppc32_SPRG3_RO 0x558
+#define OFFSET_ppc32_TFHAR 0x560
+#define OFFSET_ppc32_TEXASR 0x568
+#define OFFSET_ppc32_TFIAR 0x570
+#define OFFSET_ppc32_PPR 0x578
+#define OFFSET_ppc32_TEXASRU 0x580
+#define OFFSET_ppc32_PSPB 0x584
+#define OFFSET_ppc64_GPR0 0x10
+#define OFFSET_ppc64_GPR1 0x18
+#define OFFSET_ppc64_GPR2 0x20
+#define OFFSET_ppc64_GPR3 0x28
+#define OFFSET_ppc64_GPR4 0x30
+#define OFFSET_ppc64_GPR5 0x38
+#define OFFSET_ppc64_GPR6 0x40
+#define OFFSET_ppc64_GPR7 0x48
+#define OFFSET_ppc64_GPR8 0x50
+#define OFFSET_ppc64_GPR9 0x58
+#define OFFSET_ppc64_GPR10 0x60
+#define OFFSET_ppc64_GPR11 0x68
+#define OFFSET_ppc64_GPR12 0x70
+#define OFFSET_ppc64_GPR13 0x78
+#define OFFSET_ppc64_GPR14 0x80
+#define OFFSET_ppc64_GPR15 0x88
+#define OFFSET_ppc64_GPR16 0x90
+#define OFFSET_ppc64_GPR17 0x98
+#define OFFSET_ppc64_GPR18 0xa0
+#define OFFSET_ppc64_GPR19 0xa8
+#define OFFSET_ppc64_GPR20 0xb0
+#define OFFSET_ppc64_GPR21 0xb8
+#define OFFSET_ppc64_GPR22 0xc0
+#define OFFSET_ppc64_GPR23 0xc8
+#define OFFSET_ppc64_GPR24 0xd0
+#define OFFSET_ppc64_GPR25 0xd8
+#define OFFSET_ppc64_GPR26 0xe0
+#define OFFSET_ppc64_GPR27 0xe8
+#define OFFSET_ppc64_GPR28 0xf0
+#define OFFSET_ppc64_GPR29 0xf8
+#define OFFSET_ppc64_GPR30 0x100
+#define OFFSET_ppc64_GPR31 0x108
+#define OFFSET_ppc64_VSR0 0x110
+#define OFFSET_ppc64_VSR1 0x120
+#define OFFSET_ppc64_VSR2 0x130
+#define OFFSET_ppc64_VSR3 0x140
+#define OFFSET_ppc64_VSR4 0x150
+#define OFFSET_ppc64_VSR5 0x160
+#define OFFSET_ppc64_VSR6 0x170
+#define OFFSET_ppc64_VSR7 0x180
+#define OFFSET_ppc64_VSR8 0x190
+#define OFFSET_ppc64_VSR9 0x1a0
+#define OFFSET_ppc64_VSR10 0x1b0
+#define OFFSET_ppc64_VSR11 0x1c0
+#define OFFSET_ppc64_VSR12 0x1d0
+#define OFFSET_ppc64_VSR13 0x1e0
+#define OFFSET_ppc64_VSR14 0x1f0
+#define OFFSET_ppc64_VSR15 0x200
+#define OFFSET_ppc64_VSR16 0x210
+#define OFFSET_ppc64_VSR17 0x220
+#define OFFSET_ppc64_VSR18 0x230
+#define OFFSET_ppc64_VSR19 0x240
+#define OFFSET_ppc64_VSR20 0x250
+#define OFFSET_ppc64_VSR21 0x260
+#define OFFSET_ppc64_VSR22 0x270
+#define OFFSET_ppc64_VSR23 0x280
+#define OFFSET_ppc64_VSR24 0x290
+#define OFFSET_ppc64_VSR25 0x2a0
+#define OFFSET_ppc64_VSR26 0x2b0
+#define OFFSET_ppc64_VSR27 0x2c0
+#define OFFSET_ppc64_VSR28 0x2d0
+#define OFFSET_ppc64_VSR29 0x2e0
+#define OFFSET_ppc64_VSR30 0x2f0
+#define OFFSET_ppc64_VSR31 0x300
+#define OFFSET_ppc64_VSR32 0x310
+#define OFFSET_ppc64_VSR33 0x320
+#define OFFSET_ppc64_VSR34 0x330
+#define OFFSET_ppc64_VSR35 0x340
+#define OFFSET_ppc64_VSR36 0x350
+#define OFFSET_ppc64_VSR37 0x360
+#define OFFSET_ppc64_VSR38 0x370
+#define OFFSET_ppc64_VSR39 0x380
+#define OFFSET_ppc64_VSR40 0x390
+#define OFFSET_ppc64_VSR41 0x3a0
+#define OFFSET_ppc64_VSR42 0x3b0
+#define OFFSET_ppc64_VSR43 0x3c0
+#define OFFSET_ppc64_VSR44 0x3d0
+#define OFFSET_ppc64_VSR45 0x3e0
+#define OFFSET_ppc64_VSR46 0x3f0
+#define OFFSET_ppc64_VSR47 0x400
+#define OFFSET_ppc64_VSR48 0x410
+#define OFFSET_ppc64_VSR49 0x420
+#define OFFSET_ppc64_VSR50 0x430
+#define OFFSET_ppc64_VSR51 0x440
+#define OFFSET_ppc64_VSR52 0x450
+#define OFFSET_ppc64_VSR53 0x460
+#define OFFSET_ppc64_VSR54 0x470
+#define OFFSET_ppc64_VSR55 0x480
+#define OFFSET_ppc64_VSR56 0x490
+#define OFFSET_ppc64_VSR57 0x4a0
+#define OFFSET_ppc64_VSR58 0x4b0
+#define OFFSET_ppc64_VSR59 0x4c0
+#define OFFSET_ppc64_VSR60 0x4d0
+#define OFFSET_ppc64_VSR61 0x4e0
+#define OFFSET_ppc64_VSR62 0x4f0
+#define OFFSET_ppc64_VSR63 0x500
+#define OFFSET_ppc64_CIA 0x510
+#define OFFSET_ppc64_LR 0x518
+#define OFFSET_ppc64_CTR 0x520
+#define OFFSET_ppc64_XER_SO 0x528
+#define OFFSET_ppc64_XER_OV 0x529
+#define OFFSET_ppc64_XER_CA 0x52a
+#define OFFSET_ppc64_XER_BC 0x52b
+#define OFFSET_ppc64_CR0_321 0x52c
+#define OFFSET_ppc64_CR0_0 0x52d
+#define OFFSET_ppc64_CR1_321 0x52e
+#define OFFSET_ppc64_CR1_0 0x52f
+#define OFFSET_ppc64_CR2_321 0x530
+#define OFFSET_ppc64_CR2_0 0x531
+#define OFFSET_ppc64_CR3_321 0x532
+#define OFFSET_ppc64_CR3_0 0x533
+#define OFFSET_ppc64_CR4_321 0x534
+#define OFFSET_ppc64_CR4_0 0x535
+#define OFFSET_ppc64_CR5_321 0x536
+#define OFFSET_ppc64_CR5_0 0x537
+#define OFFSET_ppc64_CR6_321 0x538
+#define OFFSET_ppc64_CR6_0 0x539
+#define OFFSET_ppc64_CR7_321 0x53a
+#define OFFSET_ppc64_CR7_0 0x53b
+#define OFFSET_ppc64_FPROUND 0x53c
+#define OFFSET_ppc64_DFPROUND 0x53d
+#define OFFSET_ppc64_C_FPCC 0x53e
+#define OFFSET_ppc64_VRSAVE 0x540
+#define OFFSET_ppc64_VSCR 0x544
+#define OFFSET_ppc64_EMNOTE 0x548
+#define OFFSET_ppc64_CMSTART 0x550
+#define OFFSET_ppc64_CMLEN 0x558
+#define OFFSET_ppc64_NRADDR 0x560
+#define OFFSET_ppc64_NRADDR_GPR2 0x568
+#define OFFSET_ppc64_REDIR_SP 0x570
+#define OFFSET_ppc64_REDIR_STACK 0x578
+#define OFFSET_ppc64_IP_AT_SYSCALL 0x678
+#define OFFSET_ppc64_SPRG3_RO 0x680
+#define OFFSET_ppc64_TFHAR 0x688
+#define OFFSET_ppc64_TEXASR 0x690
+#define OFFSET_ppc64_TFIAR 0x698
+#define OFFSET_ppc64_PPR 0x6a0
+#define OFFSET_ppc64_TEXASRU 0x6a8
+#define OFFSET_ppc64_PSPB 0x6ac
+#define OFFSET_arm_R0 0x8
+#define OFFSET_arm_R1 0xc
+#define OFFSET_arm_R2 0x10
+#define OFFSET_arm_R3 0x14
+#define OFFSET_arm_R4 0x18
+#define OFFSET_arm_R5 0x1c
+#define OFFSET_arm_R6 0x20
+#define OFFSET_arm_R7 0x24
+#define OFFSET_arm_R8 0x28
+#define OFFSET_arm_R9 0x2c
+#define OFFSET_arm_R10 0x30
+#define OFFSET_arm_R11 0x34
+#define OFFSET_arm_R12 0x38
+#define OFFSET_arm_R13 0x3c
+#define OFFSET_arm_R14 0x40
+#define OFFSET_arm_R15T 0x44
+#define OFFSET_arm_CC_OP 0x48
+#define OFFSET_arm_CC_DEP1 0x4c
+#define OFFSET_arm_CC_DEP2 0x50
+#define OFFSET_arm_CC_NDEP 0x54
+#define OFFSET_arm_QFLAG32 0x58
+#define OFFSET_arm_GEFLAG0 0x5c
+#define OFFSET_arm_GEFLAG1 0x60
+#define OFFSET_arm_GEFLAG2 0x64
+#define OFFSET_arm_GEFLAG3 0x68
+#define OFFSET_arm_EMNOTE 0x6c
+#define OFFSET_arm_CMSTART 0x70
+#define OFFSET_arm_CMLEN 0x74
+#define OFFSET_arm_NRADDR 0x78
+#define OFFSET_arm_IP_AT_SYSCALL 0x7c
+#define OFFSET_arm_D0 0x80
+#define OFFSET_arm_D1 0x88
+#define OFFSET_arm_D2 0x90
+#define OFFSET_arm_D3 0x98
+#define OFFSET_arm_D4 0xa0
+#define OFFSET_arm_D5 0xa8
+#define OFFSET_arm_D6 0xb0
+#define OFFSET_arm_D7 0xb8
+#define OFFSET_arm_D8 0xc0
+#define OFFSET_arm_D9 0xc8
+#define OFFSET_arm_D10 0xd0
+#define OFFSET_arm_D11 0xd8
+#define OFFSET_arm_D12 0xe0
+#define OFFSET_arm_D13 0xe8
+#define OFFSET_arm_D14 0xf0
+#define OFFSET_arm_D15 0xf8
+#define OFFSET_arm_D16 0x100
+#define OFFSET_arm_D17 0x108
+#define OFFSET_arm_D18 0x110
+#define OFFSET_arm_D19 0x118
+#define OFFSET_arm_D20 0x120
+#define OFFSET_arm_D21 0x128
+#define OFFSET_arm_D22 0x130
+#define OFFSET_arm_D23 0x138
+#define OFFSET_arm_D24 0x140
+#define OFFSET_arm_D25 0x148
+#define OFFSET_arm_D26 0x150
+#define OFFSET_arm_D27 0x158
+#define OFFSET_arm_D28 0x160
+#define OFFSET_arm_D29 0x168
+#define OFFSET_arm_D30 0x170
+#define OFFSET_arm_D31 0x178
+#define OFFSET_arm_FPSCR 0x180
+#define OFFSET_arm_TPIDRURO 0x184
+#define OFFSET_arm_ITSTATE 0x188
+#define OFFSET_arm64_X0 0x10
+#define OFFSET_arm64_X1 0x18
+#define OFFSET_arm64_X2 0x20
+#define OFFSET_arm64_X3 0x28
+#define OFFSET_arm64_X4 0x30
+#define OFFSET_arm64_X5 0x38
+#define OFFSET_arm64_X6 0x40
+#define OFFSET_arm64_X7 0x48
+#define OFFSET_arm64_X8 0x50
+#define OFFSET_arm64_X9 0x58
+#define OFFSET_arm64_X10 0x60
+#define OFFSET_arm64_X11 0x68
+#define OFFSET_arm64_X12 0x70
+#define OFFSET_arm64_X13 0x78
+#define OFFSET_arm64_X14 0x80
+#define OFFSET_arm64_X15 0x88
+#define OFFSET_arm64_X16 0x90
+#define OFFSET_arm64_X17 0x98
+#define OFFSET_arm64_X18 0xa0
+#define OFFSET_arm64_X19 0xa8
+#define OFFSET_arm64_X20 0xb0
+#define OFFSET_arm64_X21 0xb8
+#define OFFSET_arm64_X22 0xc0
+#define OFFSET_arm64_X23 0xc8
+#define OFFSET_arm64_X24 0xd0
+#define OFFSET_arm64_X25 0xd8
+#define OFFSET_arm64_X26 0xe0
+#define OFFSET_arm64_X27 0xe8
+#define OFFSET_arm64_X28 0xf0
+#define OFFSET_arm64_X29 0xf8
+#define OFFSET_arm64_X30 0x100
+#define OFFSET_arm64_XSP 0x108
+#define OFFSET_arm64_PC 0x110
+#define OFFSET_arm64_CC_OP 0x118
+#define OFFSET_arm64_CC_DEP1 0x120
+#define OFFSET_arm64_CC_DEP2 0x128
+#define OFFSET_arm64_CC_NDEP 0x130
+#define OFFSET_arm64_TPIDR_EL0 0x138
+#define OFFSET_arm64_Q0 0x140
+#define OFFSET_arm64_Q1 0x150
+#define OFFSET_arm64_Q2 0x160
+#define OFFSET_arm64_Q3 0x170
+#define OFFSET_arm64_Q4 0x180
+#define OFFSET_arm64_Q5 0x190
+#define OFFSET_arm64_Q6 0x1a0
+#define OFFSET_arm64_Q7 0x1b0
+#define OFFSET_arm64_Q8 0x1c0
+#define OFFSET_arm64_Q9 0x1d0
+#define OFFSET_arm64_Q10 0x1e0
+#define OFFSET_arm64_Q11 0x1f0
+#define OFFSET_arm64_Q12 0x200
+#define OFFSET_arm64_Q13 0x210
+#define OFFSET_arm64_Q14 0x220
+#define OFFSET_arm64_Q15 0x230
+#define OFFSET_arm64_Q16 0x240
+#define OFFSET_arm64_Q17 0x250
+#define OFFSET_arm64_Q18 0x260
+#define OFFSET_arm64_Q19 0x270
+#define OFFSET_arm64_Q20 0x280
+#define OFFSET_arm64_Q21 0x290
+#define OFFSET_arm64_Q22 0x2a0
+#define OFFSET_arm64_Q23 0x2b0
+#define OFFSET_arm64_Q24 0x2c0
+#define OFFSET_arm64_Q25 0x2d0
+#define OFFSET_arm64_Q26 0x2e0
+#define OFFSET_arm64_Q27 0x2f0
+#define OFFSET_arm64_Q28 0x300
+#define OFFSET_arm64_Q29 0x310
+#define OFFSET_arm64_Q30 0x320
+#define OFFSET_arm64_Q31 0x330
+#define OFFSET_arm64_QCFLAG 0x340
+#define OFFSET_arm64_EMNOTE 0x350
+#define OFFSET_arm64_CMSTART 0x358
+#define OFFSET_arm64_CMLEN 0x360
+#define OFFSET_arm64_NRADDR 0x368
+#define OFFSET_arm64_IP_AT_SYSCALL 0x370
+#define OFFSET_arm64_FPCR 0x378
+#define OFFSET_s390x_a0 0
+#define OFFSET_s390x_a1 0x4
+#define OFFSET_s390x_a2 0x8
+#define OFFSET_s390x_a3 0xc
+#define OFFSET_s390x_a4 0x10
+#define OFFSET_s390x_a5 0x14
+#define OFFSET_s390x_a6 0x18
+#define OFFSET_s390x_a7 0x1c
+#define OFFSET_s390x_a8 0x20
+#define OFFSET_s390x_a9 0x24
+#define OFFSET_s390x_a10 0x28
+#define OFFSET_s390x_a11 0x2c
+#define OFFSET_s390x_a12 0x30
+#define OFFSET_s390x_a13 0x34
+#define OFFSET_s390x_a14 0x38
+#define OFFSET_s390x_a15 0x3c
+#define OFFSET_s390x_v0 0x40
+#define OFFSET_s390x_v1 0x50
+#define OFFSET_s390x_v2 0x60
+#define OFFSET_s390x_v3 0x70
+#define OFFSET_s390x_v4 0x80
+#define OFFSET_s390x_v5 0x90
+#define OFFSET_s390x_v6 0xa0
+#define OFFSET_s390x_v7 0xb0
+#define OFFSET_s390x_v8 0xc0
+#define OFFSET_s390x_v9 0xd0
+#define OFFSET_s390x_v10 0xe0
+#define OFFSET_s390x_v11 0xf0
+#define OFFSET_s390x_v12 0x100
+#define OFFSET_s390x_v13 0x110
+#define OFFSET_s390x_v14 0x120
+#define OFFSET_s390x_v15 0x130
+#define OFFSET_s390x_v16 0x140
+#define OFFSET_s390x_v17 0x150
+#define OFFSET_s390x_v18 0x160
+#define OFFSET_s390x_v19 0x170
+#define OFFSET_s390x_v20 0x180
+#define OFFSET_s390x_v21 0x190
+#define OFFSET_s390x_v22 0x1a0
+#define OFFSET_s390x_v23 0x1b0
+#define OFFSET_s390x_v24 0x1c0
+#define OFFSET_s390x_v25 0x1d0
+#define OFFSET_s390x_v26 0x1e0
+#define OFFSET_s390x_v27 0x1f0
+#define OFFSET_s390x_v28 0x200
+#define OFFSET_s390x_v29 0x210
+#define OFFSET_s390x_v30 0x220
+#define OFFSET_s390x_v31 0x230
+#define OFFSET_s390x_r0 0x240
+#define OFFSET_s390x_r1 0x248
+#define OFFSET_s390x_r2 0x250
+#define OFFSET_s390x_r3 0x258
+#define OFFSET_s390x_r4 0x260
+#define OFFSET_s390x_r5 0x268
+#define OFFSET_s390x_r6 0x270
+#define OFFSET_s390x_r7 0x278
+#define OFFSET_s390x_r8 0x280
+#define OFFSET_s390x_r9 0x288
+#define OFFSET_s390x_r10 0x290
+#define OFFSET_s390x_r11 0x298
+#define OFFSET_s390x_r12 0x2a0
+#define OFFSET_s390x_r13 0x2a8
+#define OFFSET_s390x_r14 0x2b0
+#define OFFSET_s390x_r15 0x2b8
+#define OFFSET_s390x_counter 0x2c0
+#define OFFSET_s390x_fpc 0x2c8
+#define OFFSET_s390x_IA 0x2d0
+#define OFFSET_s390x_SYSNO 0x2d8
+#define OFFSET_s390x_CC_OP 0x2e0
+#define OFFSET_s390x_CC_DEP1 0x2e8
+#define OFFSET_s390x_CC_DEP2 0x2f0
+#define OFFSET_s390x_CC_NDEP 0x2f8
+#define OFFSET_s390x_NRADDR 0x300
+#define OFFSET_s390x_CMSTART 0x308
+#define OFFSET_s390x_CMLEN 0x310
+#define OFFSET_s390x_IP_AT_SYSCALL 0x318
+#define OFFSET_s390x_EMNOTE 0x320
+#define OFFSET_mips32_r0 0x8
+#define OFFSET_mips32_r1 0xc
+#define OFFSET_mips32_r2 0x10
+#define OFFSET_mips32_r3 0x14
+#define OFFSET_mips32_r4 0x18
+#define OFFSET_mips32_r5 0x1c
+#define OFFSET_mips32_r6 0x20
+#define OFFSET_mips32_r7 0x24
+#define OFFSET_mips32_r8 0x28
+#define OFFSET_mips32_r9 0x2c
+#define OFFSET_mips32_r10 0x30
+#define OFFSET_mips32_r11 0x34
+#define OFFSET_mips32_r12 0x38
+#define OFFSET_mips32_r13 0x3c
+#define OFFSET_mips32_r14 0x40
+#define OFFSET_mips32_r15 0x44
+#define OFFSET_mips32_r16 0x48
+#define OFFSET_mips32_r17 0x4c
+#define OFFSET_mips32_r18 0x50
+#define OFFSET_mips32_r19 0x54
+#define OFFSET_mips32_r20 0x58
+#define OFFSET_mips32_r21 0x5c
+#define OFFSET_mips32_r22 0x60
+#define OFFSET_mips32_r23 0x64
+#define OFFSET_mips32_r24 0x68
+#define OFFSET_mips32_r25 0x6c
+#define OFFSET_mips32_r26 0x70
+#define OFFSET_mips32_r27 0x74
+#define OFFSET_mips32_r28 0x78
+#define OFFSET_mips32_r29 0x7c
+#define OFFSET_mips32_r30 0x80
+#define OFFSET_mips32_r31 0x84
+#define OFFSET_mips32_PC 0x88
+#define OFFSET_mips32_HI 0x8c
+#define OFFSET_mips32_LO 0x90
+#define OFFSET_mips32_f0 0x98
+#define OFFSET_mips32_f1 0xa0
+#define OFFSET_mips32_f2 0xa8
+#define OFFSET_mips32_f3 0xb0
+#define OFFSET_mips32_f4 0xb8
+#define OFFSET_mips32_f5 0xc0
+#define OFFSET_mips32_f6 0xc8
+#define OFFSET_mips32_f7 0xd0
+#define OFFSET_mips32_f8 0xd8
+#define OFFSET_mips32_f9 0xe0
+#define OFFSET_mips32_f10 0xe8
+#define OFFSET_mips32_f11 0xf0
+#define OFFSET_mips32_f12 0xf8
+#define OFFSET_mips32_f13 0x100
+#define OFFSET_mips32_f14 0x108
+#define OFFSET_mips32_f15 0x110
+#define OFFSET_mips32_f16 0x118
+#define OFFSET_mips32_f17 0x120
+#define OFFSET_mips32_f18 0x128
+#define OFFSET_mips32_f19 0x130
+#define OFFSET_mips32_f20 0x138
+#define OFFSET_mips32_f21 0x140
+#define OFFSET_mips32_f22 0x148
+#define OFFSET_mips32_f23 0x150
+#define OFFSET_mips32_f24 0x158
+#define OFFSET_mips32_f25 0x160
+#define OFFSET_mips32_f26 0x168
+#define OFFSET_mips32_f27 0x170
+#define OFFSET_mips32_f28 0x178
+#define OFFSET_mips32_f29 0x180
+#define OFFSET_mips32_f30 0x188
+#define OFFSET_mips32_f31 0x190
+#define OFFSET_mips32_FIR 0x198
+#define OFFSET_mips32_FCCR 0x19c
+#define OFFSET_mips32_FEXR 0x1a0
+#define OFFSET_mips32_FENR 0x1a4
+#define OFFSET_mips32_FCSR 0x1a8
+#define OFFSET_mips32_ULR 0x1ac
+#define OFFSET_mips32_EMNOTE 0x1b0
+#define OFFSET_mips32_CMSTART 0x1b4
+#define OFFSET_mips32_CMLEN 0x1b8
+#define OFFSET_mips32_NRADDR 0x1bc
+#define OFFSET_mips32_COND 0x1c0
+#define OFFSET_mips32_DSPControl 0x1c4
+#define OFFSET_mips32_ac0 0x1c8
+#define OFFSET_mips32_ac1 0x1d0
+#define OFFSET_mips32_ac2 0x1d8
+#define OFFSET_mips32_ac3 0x1e0
+#define OFFSET_mips32_CP0_status 0x1e8
+#define OFFSET_mips32_IP_AT_SYSCALL 0x1ec
+#define OFFSET_mips64_r0 0x10
+#define OFFSET_mips64_r1 0x18
+#define OFFSET_mips64_r2 0x20
+#define OFFSET_mips64_r3 0x28
+#define OFFSET_mips64_r4 0x30
+#define OFFSET_mips64_r5 0x38
+#define OFFSET_mips64_r6 0x40
+#define OFFSET_mips64_r7 0x48
+#define OFFSET_mips64_r8 0x50
+#define OFFSET_mips64_r9 0x58
+#define OFFSET_mips64_r10 0x60
+#define OFFSET_mips64_r11 0x68
+#define OFFSET_mips64_r12 0x70
+#define OFFSET_mips64_r13 0x78
+#define OFFSET_mips64_r14 0x80
+#define OFFSET_mips64_r15 0x88
+#define OFFSET_mips64_r16 0x90
+#define OFFSET_mips64_r17 0x98
+#define OFFSET_mips64_r18 0xa0
+#define OFFSET_mips64_r19 0xa8
+#define OFFSET_mips64_r20 0xb0
+#define OFFSET_mips64_r21 0xb8
+#define OFFSET_mips64_r22 0xc0
+#define OFFSET_mips64_r23 0xc8
+#define OFFSET_mips64_r24 0xd0
+#define OFFSET_mips64_r25 0xd8
+#define OFFSET_mips64_r26 0xe0
+#define OFFSET_mips64_r27 0xe8
+#define OFFSET_mips64_r28 0xf0
+#define OFFSET_mips64_r29 0xf8
+#define OFFSET_mips64_r30 0x100
+#define OFFSET_mips64_r31 0x108
+#define OFFSET_mips64_PC 0x110
+#define OFFSET_mips64_HI 0x118
+#define OFFSET_mips64_LO 0x120
+#define OFFSET_mips64_f0 0x128
+#define OFFSET_mips64_f1 0x130
+#define OFFSET_mips64_f2 0x138
+#define OFFSET_mips64_f3 0x140
+#define OFFSET_mips64_f4 0x148
+#define OFFSET_mips64_f5 0x150
+#define OFFSET_mips64_f6 0x158
+#define OFFSET_mips64_f7 0x160
+#define OFFSET_mips64_f8 0x168
+#define OFFSET_mips64_f9 0x170
+#define OFFSET_mips64_f10 0x178
+#define OFFSET_mips64_f11 0x180
+#define OFFSET_mips64_f12 0x188
+#define OFFSET_mips64_f13 0x190
+#define OFFSET_mips64_f14 0x198
+#define OFFSET_mips64_f15 0x1a0
+#define OFFSET_mips64_f16 0x1a8
+#define OFFSET_mips64_f17 0x1b0
+#define OFFSET_mips64_f18 0x1b8
+#define OFFSET_mips64_f19 0x1c0
+#define OFFSET_mips64_f20 0x1c8
+#define OFFSET_mips64_f21 0x1d0
+#define OFFSET_mips64_f22 0x1d8
+#define OFFSET_mips64_f23 0x1e0
+#define OFFSET_mips64_f24 0x1e8
+#define OFFSET_mips64_f25 0x1f0
+#define OFFSET_mips64_f26 0x1f8
+#define OFFSET_mips64_f27 0x200
+#define OFFSET_mips64_f28 0x208
+#define OFFSET_mips64_f29 0x210
+#define OFFSET_mips64_f30 0x218
+#define OFFSET_mips64_f31 0x220
+#define OFFSET_mips64_FIR 0x228
+#define OFFSET_mips64_FCCR 0x22c
+#define OFFSET_mips64_FEXR 0x230
+#define OFFSET_mips64_FENR 0x234
+#define OFFSET_mips64_FCSR 0x238
+#define OFFSET_mips64_CP0_status 0x23c
+#define OFFSET_mips64_ULR 0x240
+#define OFFSET_mips64_EMNOTE 0x248
+#define OFFSET_mips64_COND 0x24c
+#define OFFSET_mips64_CMSTART 0x250
+#define OFFSET_mips64_CMLEN 0x258
+#define OFFSET_mips64_NRADDR 0x260
+#define OFFSET_mips64_IP_AT_SYSCALL 0x268
+#define OFFSET_tilegx_r0 0
+#define OFFSET_tilegx_r1 0x8
+#define OFFSET_tilegx_r2 0x10
+#define OFFSET_tilegx_r3 0x18
+#define OFFSET_tilegx_r4 0x20
+#define OFFSET_tilegx_r5 0x28
+#define OFFSET_tilegx_r6 0x30
+#define OFFSET_tilegx_r7 0x38
+#define OFFSET_tilegx_r8 0x40
+#define OFFSET_tilegx_r9 0x48
+#define OFFSET_tilegx_r10 0x50
+#define OFFSET_tilegx_r11 0x58
+#define OFFSET_tilegx_r12 0x60
+#define OFFSET_tilegx_r13 0x68
+#define OFFSET_tilegx_r14 0x70
+#define OFFSET_tilegx_r15 0x78
+#define OFFSET_tilegx_r16 0x80
+#define OFFSET_tilegx_r17 0x88
+#define OFFSET_tilegx_r18 0x90
+#define OFFSET_tilegx_r19 0x98
+#define OFFSET_tilegx_r20 0xa0
+#define OFFSET_tilegx_r21 0xa8
+#define OFFSET_tilegx_r22 0xb0
+#define OFFSET_tilegx_r23 0xb8
+#define OFFSET_tilegx_r24 0xc0
+#define OFFSET_tilegx_r25 0xc8
+#define OFFSET_tilegx_r26 0xd0
+#define OFFSET_tilegx_r27 0xd8
+#define OFFSET_tilegx_r28 0xe0
+#define OFFSET_tilegx_r29 0xe8
+#define OFFSET_tilegx_r30 0xf0
+#define OFFSET_tilegx_r31 0xf8
+#define OFFSET_tilegx_r32 0x100
+#define OFFSET_tilegx_r33 0x108
+#define OFFSET_tilegx_r34 0x110
+#define OFFSET_tilegx_r35 0x118
+#define OFFSET_tilegx_r36 0x120
+#define OFFSET_tilegx_r37 0x128
+#define OFFSET_tilegx_r38 0x130
+#define OFFSET_tilegx_r39 0x138
+#define OFFSET_tilegx_r40 0x140
+#define OFFSET_tilegx_r41 0x148
+#define OFFSET_tilegx_r42 0x150
+#define OFFSET_tilegx_r43 0x158
+#define OFFSET_tilegx_r44 0x160
+#define OFFSET_tilegx_r45 0x168
+#define OFFSET_tilegx_r46 0x170
+#define OFFSET_tilegx_r47 0x178
+#define OFFSET_tilegx_r48 0x180
+#define OFFSET_tilegx_r49 0x188
+#define OFFSET_tilegx_r50 0x190
+#define OFFSET_tilegx_r51 0x198
+#define OFFSET_tilegx_r52 0x1a0
+#define OFFSET_tilegx_r53 0x1a8
+#define OFFSET_tilegx_r54 0x1b0
+#define OFFSET_tilegx_r55 0x1b8
+#define OFFSET_tilegx_r56 0x1c0
+#define OFFSET_tilegx_r57 0x1c8
+#define OFFSET_tilegx_r58 0x1d0
+#define OFFSET_tilegx_r59 0x1d8
+#define OFFSET_tilegx_r60 0x1e0
+#define OFFSET_tilegx_r61 0x1e8
+#define OFFSET_tilegx_r62 0x1f0
+#define OFFSET_tilegx_r63 0x1f8
+#define OFFSET_tilegx_pc 0x200
+#define OFFSET_tilegx_spare 0x208
+#define OFFSET_tilegx_EMNOTE 0x210
+#define OFFSET_tilegx_CMSTART 0x218
+#define OFFSET_tilegx_CMLEN 0x220
+#define OFFSET_tilegx_NRADDR 0x228
+#define OFFSET_tilegx_cmpexch 0x230
+#define OFFSET_tilegx_zero 0x238
+#define OFFSET_tilegx_ex_context_0 0x240
+#define OFFSET_tilegx_ex_context_1 0x248
+#define OFFSET_tilegx_COND 0x260
+#define OFFSET_riscv64_x0 0x10
+#define OFFSET_riscv64_x1 0x18
+#define OFFSET_riscv64_x2 0x20
+#define OFFSET_riscv64_x3 0x28
+#define OFFSET_riscv64_x4 0x30
+#define OFFSET_riscv64_x5 0x38
+#define OFFSET_riscv64_x6 0x40
+#define OFFSET_riscv64_x7 0x48
+#define OFFSET_riscv64_x9 0x58
+#define OFFSET_riscv64_x9 0x58
+#define OFFSET_riscv64_x10 0x60
+#define OFFSET_riscv64_x11 0x68
+#define OFFSET_riscv64_x12 0x70
+#define OFFSET_riscv64_x13 0x78
+#define OFFSET_riscv64_x14 0x80
+#define OFFSET_riscv64_x15 0x88
+#define OFFSET_riscv64_x16 0x90
+#define OFFSET_riscv64_x17 0x98
+#define OFFSET_riscv64_x18 0xa0
+#define OFFSET_riscv64_x19 0xa8
+#define OFFSET_riscv64_x20 0xb0
+#define OFFSET_riscv64_x21 0xb8
+#define OFFSET_riscv64_x22 0xc0
+#define OFFSET_riscv64_x23 0xc8
+#define OFFSET_riscv64_x24 0xd0
+#define OFFSET_riscv64_x25 0xd8
+#define OFFSET_riscv64_x26 0xe0
+#define OFFSET_riscv64_x27 0xe8
+#define OFFSET_riscv64_x28 0xf0
+#define OFFSET_riscv64_x29 0xf8
+#define OFFSET_riscv64_x30 0x100
+#define OFFSET_riscv64_x31 0x108
+#define OFFSET_riscv64_pc 0x110
+#define OFFSET_riscv64_f0 0x118
+#define OFFSET_riscv64_f1 0x120
+#define OFFSET_riscv64_f2 0x128
+#define OFFSET_riscv64_f3 0x130
+#define OFFSET_riscv64_f4 0x138
+#define OFFSET_riscv64_f5 0x140
+#define OFFSET_riscv64_f6 0x148
+#define OFFSET_riscv64_f7 0x150
+#define OFFSET_riscv64_f9 0x160
+#define OFFSET_riscv64_f9 0x160
+#define OFFSET_riscv64_f10 0x168
+#define OFFSET_riscv64_f11 0x170
+#define OFFSET_riscv64_f12 0x178
+#define OFFSET_riscv64_f13 0x180
+#define OFFSET_riscv64_f14 0x188
+#define OFFSET_riscv64_f15 0x190
+#define OFFSET_riscv64_f16 0x198
+#define OFFSET_riscv64_f17 0x1a0
+#define OFFSET_riscv64_f18 0x1a8
+#define OFFSET_riscv64_f19 0x1b0
+#define OFFSET_riscv64_f20 0x1b8
+#define OFFSET_riscv64_f21 0x1c0
+#define OFFSET_riscv64_f22 0x1c8
+#define OFFSET_riscv64_f23 0x1d0
+#define OFFSET_riscv64_f24 0x1d8
+#define OFFSET_riscv64_f25 0x1e0
+#define OFFSET_riscv64_f26 0x1e8
+#define OFFSET_riscv64_f27 0x1f0
+#define OFFSET_riscv64_f28 0x1f8
+#define OFFSET_riscv64_f29 0x200
+#define OFFSET_riscv64_f30 0x208
+#define OFFSET_riscv64_f31 0x210