mlonmcu 0.3.0.dev0__3-none-any.whl

resources/platforms/zephyr/project2/cmake/features/muriscvnn.cmake

@@ -0,0 +1,87 @@
+IF(NOT MURISCVNN_DIR)
+    MESSAGE(FATAL_ERROR "Missing value: MURISCVNN_DIR")
+ENDIF()
+
+IF(NOT RISCV_VEXT)
+    SET(USE_VEXT OFF)
+ELSE()
+    SET(USE_VEXT ON)
+ENDIF()
+
+IF(NOT RISCV_PEXT)
+    SET(USE_PEXT OFF)
+ELSE()
+    SET(USE_PEXT ON)
+ENDIF()
+
+IF(NOT MURISCVNN_TOOLCHAIN)
+    SET(MURISCVVN_TOOLCHAIN GCC)
+    # SET(MURISCVVN_TOOLCHAIN NONE)
+ENDIF()
+
+SET(MURISCVNN_INCLUDE_DIRS ${MURISCVNN_DIR}/Include ${MURISCVNN_DIR}/Include/CMSIS/NN/Include)
+
+# TODO: propagarting all toolchain specific vars does not scale well
+
+INCLUDE(ExternalProject)
+EXTERNALPROJECT_ADD(
+    muriscvnn
+    PREFIX muriscvnn
+    SOURCE_DIR ${MURISCVNN_DIR}
+    CMAKE_ARGS -DCMAKE_BUILD_TYPE:STRING=${CMAKE_BUILD_TYPE}
+               -DUSE_VEXT=${USE_VEXT}
+               -DUSE_PEXT=${USE_PEXT}
+               -DTOOLCHAIN=${MURISCVNN_TOOLCHAIN}
+               -DCMAKE_TOOLCHAIN_FILE=${TOOLCHAIN_FILE}
+               -DENABLE_TESTS=OFF
+               -DTC_PREFIX=${TC_PREFIX}
+               -DEXE_EXT=${EXE_EXT}
+               -DRISCV_ARCH=${RISCV_ARCH}
+               -DRISCV_ABI=${RISCV_ABI}
+               -DARM_CPU=${ARM_CPU}
+               -DARM_FLOAT_ABI=${ARM_FLOAT_ABI}
+               -DARM_FPU=${ARM_FPU}
+    BUILD_COMMAND "${CMAKE_COMMAND}" --build .
+    INSTALL_COMMAND ""
+)
+
+EXTERNALPROJECT_GET_PROPERTY(muriscvnn BINARY_DIR)
+SET(MURISCVNN_LIB ${BINARY_DIR}/Source/libmuriscv_nn.a)
+
+# TFLite integration
+IF(TFLM_OPTIMIZED_KERNEL_LIB)
+    LIST(APPEND TFLM_OPTIMIZED_KERNEL_LIB ${MURISCVNN_LIB})
+ELSE()
+    SET(TFLM_OPTIMIZED_KERNEL_LIB ${MURISCVNN_LIB})
+ENDIF()
+
+IF(TFLM_OPTIMIZED_KERNEL_INCLUDE_DIR)
+    LIST(APPEND TFLM_OPTIMIZED_KERNEL_INCLUDE_DIR ${MURISCVNN_INCLUDE_DIRS})
+ELSE()
+    SET(TFLM_OPTIMIZED_KERNEL_INCLUDE_DIR ${MURISCVNN_INCLUDE_DIRS})
+ENDIF()
+
+IF(TFLM_OPTIMIZED_KERNEL_DEPS)
+    LIST(APPEND TFLM_OPTIMIZED_KERNEL_DEPS muriscvnn)
+ELSE()
+    SET(TFLM_OPTIMIZED_KERNEL_DEPS muriscvnn)
+ENDIF()
+
+# TVM integration
+IF(TVM_EXTRA_LIBS)
+    LIST(APPEND TVM_EXTRA_LIBS ${MURISCVNN_LIB})
+ELSE()
+    SET(TVM_EXTRA_LIBS ${MURISCVNN_LIB})
+ENDIF()
+
+IF(TVM_EXTRA_INCS)
+    LIST(APPEND TVM_EXTRA_INCS ${MURISCVNN_INCLUDE_DIRS})
+ELSE()
+    SET(TVM_EXTRA_INCS ${MURISCVNN_INCLUDE_DIRS})
+ENDIF()
+
+IF(TVM_EXTRA_DEPS)
+    LIST(APPEND TVM_EXTRA_DEPS muriscvnn)
+ELSE()
+    SET(TVM_EXTRA_DEPS muriscvnn)
+ENDIF()

resources/platforms/zephyr/project2/cmake/frameworks/tflm.cmake

@@ -0,0 +1 @@
+

resources/platforms/zephyr/project2/cmake/frameworks/tflm_mlif.cmake

@@ -0,0 +1,8 @@
+SET(TF_OUT_DIR ${CONFIG_MLONMCU_CODEGEN_DIR}/)
+SET(GEN_SRC ${TF_OUT_DIR}/model.cc)
+GET_FILENAME_COMPONENT(GEN_SRC ${GEN_SRC} REALPATH)
+GET_FILENAME_COMPONENT(EXTRA_INC ${GEN_SRC} DIRECTORY)
+SET(EXTRA_SRC ml_interface_tflm.cc ${GEN_SRC})
+SET(EXTRA_LIBS tflm)
+SET(CMAKE_CXX_FLAGS_DEBUG "${CMAKE_CXX_FLAGS_DEBUG} -DTFLMC_DEBUG_ALLOCATIONS")
+LIST(APPEND EXTRA_LIBS ${CUSTOM_OPS_LIBS})

resources/platforms/zephyr/project2/cmake/frameworks/tvm.cmake

@@ -0,0 +1 @@
+

resources/platforms/zephyr/project2/cmake/frameworks/tvm_mlif.cmake

@@ -0,0 +1,37 @@
+SET(TVM_OUT_DIR ${CONFIG_MLONMCU_CODEGEN_DIR}/codegen/host/)
+SET(EXTRA_SRC ml_interface_tvm.c)
+
+FILE(GLOB TVM_SRCS ${TVM_OUT_DIR}/src/*_lib*.c ${TVM_OUT_DIR}/src/*_lib*.cc)
+
+# IF(NOT TVM_SRCS)
+#     MESSAGE(STATUS "NO SOURCES")
+#     FILE(GLOB TVM_OBJS ${TVM_OUT_DIR}/lib/*_lib*.o)
+#     MESSAGE(STATUS "TVM_OBJS=${TVM_OBJS}")
+#     # ADD_LIBRARY(tvm_extension OBJECT IMPORTED)
+#
+#     # SET_PROPERTY(TARGET tvm_extension PROPERTY
+#     #     IMPORTED_OBJECTS ${TVM_OBJS}
+#     # )
+# ELSE()
+#     # Need this in extra target to avoid circular dependency .
+#     # ADD_LIBRARY(tvm_extension STATIC ${TVM_SRCS})
+#     TARGET_INCLUDE_DIRECTORIES(tvm_extension PUBLIC ${TVM_HEADERS} ${TVM_OUT_DIR}/include ${CONFIG_MLONMCU_CODEGEN_DIR})
+#     TARGET_LINK_LIBRARIES(tvm_extension PUBLIC m)
+#     TARGET_LINK_LIBRARIES(tvm_extension PUBLIC ${TVM_LIB})
+# ENDIF()
+#
+# SET(EXTRA_SRC ${EXTRA_SRC} ${CONFIG_MLONMCU_CODEGEN_DIR}/${TVM_WRAPPER_FILENAME})
+# TARGET_LINK_LIBRARIES(${TVM_LIB} PUBLIC tvm_extension)
+# SET(EXTRA_INC ${TVM_OUT_DIR}/include ${CONFIG_MLONMCU_CODEGEN_DIR})
+#
+# SET(EXTRA_LIBS tvm_extension ${TVM_LIB})
+#
+# FOREACH(ENTRY ${CONFIG_TVM_EXTRA_LIBS})
+#     TARGET_LINK_LIBRARIES(tvm_extension PUBLIC ${ENTRY})
+# ENDFOREACH()
+# FOREACH(ENTRY ${CONFIG_TVM_EXTRA_INCS})
+#     TARGET_INCLUDE_DIRECTORIES(tvm_extension PUBLIC ${ENTRY})
+# ENDFOREACH()
+# FOREACH(ENTRY ${CONFIG_TVM_EXTRA_DEPS})
+#     ADD_DEPENDENCIES(tvm_extension ${ENTRY})
+# ENDFOREACH()

resources/platforms/zephyr/project2/default_data.c

@@ -0,0 +1,8 @@
+#include "ml_interface.h"
+#include <stddef.h>
+const int num_data_buffers_in = 0;
+const int num_data_buffers_out = 0;
+const unsigned char *const data_buffers_in[] = {};
+const unsigned char *const data_buffers_out[] = {};
+const size_t data_size_in[] = {};
+const size_t data_size_out[] = {};

resources/platforms/zephyr/project2/default_model_support/CMakeLists.txt

@@ -0,0 +1,3 @@
+ADD_LIBRARY(model_support STATIC process_input.c process_output.c)
+# TARGET_LINK_LIBRARIES(model_support PUBLIC ml_interface_base)
+TARGET_INCLUDE_DIRECTORIES(model_support PUBLIC ../lib/support)

resources/platforms/zephyr/project2/default_model_support/process_input.c

@@ -0,0 +1,17 @@
+#include <stdlib.h>
+#include <memory.h>
+
+#include "printing.h"
+#include "exit.h"
+
+void mlif_process_input(const void *in_data, size_t in_size, void *model_input_ptr, size_t model_input_sz) {
+  if (in_size != 0) {
+    if (in_size != model_input_sz) {
+      DBGPRINTF("MLIF: Given input size (%lu) does not match model input buffer size (%lu)!\n", in_size,
+                model_input_sz);
+      exit(EXIT_MLIF_INVALID_SIZE);
+    }
+  }
+
+  memcpy(model_input_ptr, in_data, in_size);
+}

resources/platforms/zephyr/project2/default_model_support/process_output.c

@@ -0,0 +1,27 @@
+#include <stdlib.h>
+#include <memory.h>
+
+#include "printing.h"
+#include "exit.h"
+
+void mlif_process_output(void *model_output_ptr, size_t model_output_sz, const void *expected_out_data,
+                         size_t expected_out_size) {
+#ifdef _DEBUG
+  if (model_output_sz >= 4) {
+    DBGPRINTF("MLIF: First float of output: %f\n", *(float *)model_output_ptr);
+  }
+  DBGPRINTF("MLIF: Model output data: ");
+  for (size_t i = 0; i < model_output_sz; i++) {
+    DBGPRINTF("\\x%02X", ((unsigned char *)model_output_ptr)[i]);
+    fflush(0);
+  }
+  DBGPRINTF("\n");
+#endif
+
+  if (model_output_sz == expected_out_size && memcmp(model_output_ptr, expected_out_data, model_output_sz) == 0) {
+    DBGPRINTF("MLIF: Output data matches expected data\n");
+  } else {
+    DBGPRINTF("MLIF: Wrong output data!\n");
+    exit(EXIT_MLIF_MISSMATCH);
+  }
+}

resources/platforms/zephyr/project2/lib/CMakeLists.txt

@@ -0,0 +1,13 @@
+PROJECT(target_sw_lib)
+
+ADD_SUBDIRECTORY(support)
+# ADD_SUBDIRECTORY(ml_interface)
+
+SET(TARGET_LIB_SOURCE targets/${TARGET_SYSTEM}.c)
+IF(NOT EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/${TARGET_LIB_SOURCE})
+    SET(TARGET_LIB_SOURCE targets/default.c)
+ENDIF()
+
+ADD_LIBRARY(${PROJECT_NAME} STATIC drivers/fake_input.c ${TARGET_LIB_SOURCE})
+TARGET_INCLUDE_DIRECTORIES(${PROJECT_NAME} PUBLIC lib/drivers lib/targets)
+# TARGET_LINK_LIBRARIES(${PROJECT_NAME} PUBLIC support ml_interface)

resources/platforms/zephyr/project2/lib/drivers/fake_input.c

@@ -0,0 +1,10 @@
+#include "fake_input.h"
+#include <stdint.h>
+
+void FakeInput_GetData(void *out, size_t len) {
+  volatile uint8_t *p = 0xc0000000;
+
+  for (size_t i = 0; i < len; i++) {
+    *(uint8_t *)out = *(p + i);
+  }
+}

resources/platforms/zephyr/project2/lib/drivers/fake_input.h

@@ -0,0 +1,8 @@
+#ifndef DRIVER_FAKE_INPUT_H
+#define DRIVER_FAKE_INPUT_H
+
+#include <stddef.h>
+
+void FakeInput_GetData(void *out, size_t len);
+
+#endif

resources/platforms/zephyr/project2/lib/support/CMakeLists.txt

@@ -0,0 +1,2 @@
+ADD_LIBRARY(support STATIC dummy.c)
+TARGET_INCLUDE_DIRECTORIES(support PUBLIC .)

resources/platforms/zephyr/project2/lib/support/exit.h

@@ -0,0 +1,8 @@
+#ifndef SUPPORT_EXIT_H
+#define SUPPORT_EXIT_H
+
+#define EXIT_MLIF_BASE (0x10)
+#define EXIT_MLIF_INVALID_SIZE (EXIT_MLIF_BASE + 1)
+#define EXIT_MLIF_MISSMATCH (EXIT_MLIF_BASE + 2)
+
+#endif  // SUPPORT_EXIT_H

resources/platforms/zephyr/project2/lib/support/printing.h

@@ -0,0 +1,11 @@
+#ifndef SUPPORT_PRINTING_H
+#define SUPPORT_PRINTING_H
+
+#ifdef _DEBUG
+#include <stdio.h>
+#define DBGPRINTF(format, ...) printf(format, ##__VA_ARGS__)
+#else
+#define DBGPRINTF(format, ...)
+#endif
+
+#endif

resources/platforms/zephyr/project2/lib/support/quantize.h

@@ -0,0 +1,23 @@
+#ifndef SUPPORT_QUANTIZE_H
+#define SUPPORT_QUANTIZE_H
+
+#include <stdint.h>
+#include <limits.h>
+#include <math.h>
+
+inline float DequantizeInt8ToFloat(int8_t value, float scale, int zero_point) {
+  return static_cast<float>(value - zero_point) * scale;
+}
+
+inline int8_t QuantizeFloatToInt8(float value, float scale, int zero_point) {
+  int32_t result = round(value / scale) + zero_point;
+  if (result < INT8_MIN) {
+    result = INT8_MIN;
+  }
+  if (result > INT8_MAX) {
+    result = INT8_MAX;
+  }
+  return static_cast<int8_t>(result);
+}
+
+#endif

resources/platforms/zephyr/project2/lib/targets/corstone300.c

@@ -0,0 +1,62 @@
+#include <stdio.h>
+
+// DWT (Data Watchpoint and Trace) registers, only exists on ARM Cortex with a
+// DWT unit.
+#define KIN1_DWT_CONTROL (*((volatile uint32_t*)0xE0001000))
+
+// DWT Control register.
+#define KIN1_DWT_CYCCNTENA_BIT (1UL << 0)
+
+// CYCCNTENA bit in DWT_CONTROL register.
+#define KIN1_DWT_CYCCNT (*((volatile uint32_t*)0xE0001004))
+
+// DWT Cycle Counter register.
+#define KIN1_DEMCR (*((volatile uint32_t*)0xE000EDFC))
+
+// DEMCR: Debug Exception and Monitor Control Register.
+#define KIN1_TRCENA_BIT (1UL << 24)
+
+// Trace enable bit in DEMCR register.
+#define KIN1_LAR (*((volatile uint32_t*)0xE0001FB0))
+
+// Unlock access to DWT (ITM, etc.)registers.
+#define KIN1_UnlockAccessToDWT() KIN1_LAR = 0xC5ACCE55;
+
+// TRCENA: Enable trace and debug block DEMCR (Debug Exception and Monitor
+// Control Register.
+#define KIN1_InitCycleCounter() KIN1_DEMCR |= KIN1_TRCENA_BIT
+
+#define KIN1_ResetCycleCounter() KIN1_DWT_CYCCNT = 0
+#define KIN1_EnableCycleCounter() KIN1_DWT_CONTROL |= KIN1_DWT_CYCCNTENA_BIT
+#define KIN1_DisableCycleCounter() KIN1_DWT_CONTROL &= ~KIN1_DWT_CYCCNTENA_BIT
+#define KIN1_GetCycleCounter() KIN1_DWT_CYCCNT
+
+int32_t ticks_per_second() { return 25e6; }
+
+int32_t GetCurrentTimeTicks() { return KIN1_GetCycleCounter(); }
+
+extern void uart_init(void);
+
+static int32_t start_cycles = 0;
+
+void init_target() {
+  uart_init();
+  KIN1_UnlockAccessToDWT();
+  KIN1_InitCycleCounter();
+  KIN1_ResetCycleCounter();
+  KIN1_EnableCycleCounter();
+  int32_t ticks = GetCurrentTimeTicks();
+  start_cycles = ticks;
+  printf("GetCurrentTimeTicks=%ld\n", ticks);
+}
+
+void deinit_target() {
+  int32_t stop_cycles = GetCurrentTimeTicks();
+  int32_t diff_cycles = stop_cycles - start_cycles;
+  // int32_t diff_ms = diff_cycles / (ticks_per_second() / 1000);
+  // printf("Total Time: %ld ms\n", diff_ms);
+  printf("Total Cycles: %ld\n", diff_cycles);
+  printf("EXITTHESIM\n");
+  while (1)
+    ;
+}

resources/platforms/zephyr/project2/lib/targets/default.c

@@ -0,0 +1,2 @@
+__attribute__((weak)) void init_target() {}
+__attribute__((weak)) void deinit_target() {}

resources/platforms/zephyr/project2/lib/targets/etiss_pulpino.c

@@ -0,0 +1,112 @@
+#include <stdio.h>
+
+/* How many cycles (rdcycle) per second (OVPsim and Spike). */
+#define RDCYCLE_PER_SECOND 100000000UL
+
+/**
+ * @brief Returns the number of clock cycles executed by the processor.
+ * Overflows after 42.9 seconds on a 100 MIPS and with CPI = 1 (OVPsim).
+ */
+static inline uint32_t rdcycle(void) {
+#if defined(__riscv) || defined(__riscv__)
+  uint32_t cycles;
+  __asm__ volatile("rdcycle %0" : "=r"(cycles));
+  return cycles;
+#else
+  return 0;
+#endif
+}
+
+/**
+ * @brief Returns the full 64bit register cycle register, which holds the
+ * number of clock cycles executed by the processor.
+ */
+static inline uint64_t rdcycle64() {
+#if defined(__riscv) || defined(__riscv__)
+  uint32_t cycles;
+  uint32_t cyclesh1;
+  uint32_t cyclesh2;
+
+  /* Reads are not atomic. So ensure, that we are never reading inconsistent
+   * values from the 64bit hardware register. */
+  do {
+    __asm__ volatile("rdcycleh %0" : "=r"(cyclesh1));
+    __asm__ volatile("rdcycle %0" : "=r"(cycles));
+    __asm__ volatile("rdcycleh %0" : "=r"(cyclesh2));
+  } while (cyclesh1 != cyclesh2);
+
+  return (((uint64_t)cyclesh1) << 32) | cycles;
+#else
+  return 0;
+#endif
+}
+
+/* How many time cycles (rdtime) per second (OVPsim and Spike). */
+#define RDTIME_PER_SECOND 1000000UL
+
+/**
+ * @brief Returns wall-clock real time that has passed from an arbitrary start time in the past.
+ */
+static inline uint32_t rdtime(void) {
+#if defined(__riscv) || defined(__riscv__)
+  uint32_t time;
+  __asm__ volatile("rdtime %0" : "=r"(time));
+  return time;
+#else
+  return 0;
+#endif
+}
+
+/**
+ * @brief Returns the number of instructions retired by the processor.
+ */
+static inline uint32_t rdinstret(void) {
+#if defined(__riscv) || defined(__riscv__)
+  uint32_t instret;
+  __asm__ volatile("rdinstret %0" : "=r"(instret));
+  return instret;
+#else
+  return 0;
+#endif
+}
+
+/**
+ * @brief Enables the vector extension (as well as the floating point extension).
+ */
+static inline void enable_fext(void)
+{
+#if defined(__riscv) || defined(__riscv__)
+    __asm__ volatile("li t0, 1<<13 \n"
+                     "csrs mstatus, t0 \n" ::
+                         : "t0");
+#endif
+}
+
+/**
+ * @brief Enables the vector extension (as well as the floating point extension).
+ */
+static inline void enable_vext(void)
+{
+#if defined(__riscv) || defined(__riscv__)
+    __asm__ volatile("li t0, 1<<9+1<<13 \n"
+                     "csrs mstatus, t0 \n" ::
+                         : "t0");
+#endif
+}
+
+static uint64_t start_cycles = 0;
+
+void init_target() {
+  // enable_fext();
+#ifdef USE_VEXT
+  // enable_vext();
+#endif
+  start_cycles = rdcycle64();
+}
+
+void deinit_target() {
+  uint64_t stop_cycles = rdcycle64();
+  uint64_t diff_cycles = stop_cycles - start_cycles;
+  float diff_ms = 0;  // unimplemented (see RDCYCLE_PER_SECOND)
+  printf("Total Cycles: %lld\n", stop_cycles - start_cycles);
+}

resources/platforms/zephyr/project2/lib/targets/generic_riscv.c

@@ -0,0 +1,112 @@
+#include <stdio.h>
+
+/* How many cycles (rdcycle) per second (OVPsim and Spike). */
+#define RDCYCLE_PER_SECOND 100000000UL
+
+/**
+ * @brief Returns the number of clock cycles executed by the processor.
+ * Overflows after 42.9 seconds on a 100 MIPS and with CPI = 1 (OVPsim).
+ */
+static inline uint32_t rdcycle(void) {
+#if defined(__riscv) || defined(__riscv__)
+  uint32_t cycles;
+  __asm__ volatile("rdcycle %0" : "=r"(cycles));
+  return cycles;
+#else
+  return 0;
+#endif
+}
+
+/**
+ * @brief Returns the full 64bit register cycle register, which holds the
+ * number of clock cycles executed by the processor.
+ */
+static inline uint64_t rdcycle64() {
+#if defined(__riscv) || defined(__riscv__)
+  uint32_t cycles;
+  uint32_t cyclesh1;
+  uint32_t cyclesh2;
+
+  /* Reads are not atomic. So ensure, that we are never reading inconsistent
+   * values from the 64bit hardware register. */
+  do {
+    __asm__ volatile("rdcycleh %0" : "=r"(cyclesh1));
+    __asm__ volatile("rdcycle %0" : "=r"(cycles));
+    __asm__ volatile("rdcycleh %0" : "=r"(cyclesh2));
+  } while (cyclesh1 != cyclesh2);
+
+  return (((uint64_t)cyclesh1) << 32) | cycles;
+#else
+  return 0;
+#endif
+}
+
+/* How many time cycles (rdtime) per second (OVPsim and Spike). */
+#define RDTIME_PER_SECOND 1000000UL
+
+/**
+ * @brief Returns wall-clock real time that has passed from an arbitrary start time in the past.
+ */
+static inline uint32_t rdtime(void) {
+#if defined(__riscv) || defined(__riscv__)
+  uint32_t time;
+  __asm__ volatile("rdtime %0" : "=r"(time));
+  return time;
+#else
+  return 0;
+#endif
+}
+
+/**
+ * @brief Returns the number of instructions retired by the processor.
+ */
+static inline uint32_t rdinstret(void) {
+#if defined(__riscv) || defined(__riscv__)
+  uint32_t instret;
+  __asm__ volatile("rdinstret %0" : "=r"(instret));
+  return instret;
+#else
+  return 0;
+#endif
+}
+
+/**
+ * @brief Enables the vector extension (as well as the floating point extension).
+ */
+static inline void enable_fext(void)
+{
+#if defined(__riscv) || defined(__riscv__)
+    __asm__ volatile("li t0, 1<<13 \n"
+                     "csrs mstatus, t0 \n" ::
+                         : "t0");
+#endif
+}
+
+/**
+ * @brief Enables the vector extension (as well as the floating point extension).
+ */
+static inline void enable_vext(void)
+{
+#if defined(__riscv) || defined(__riscv__)
+    __asm__ volatile("li t0, 1<<9+1<<13 \n"
+                     "csrs mstatus, t0 \n" ::
+                         : "t0");
+#endif
+}
+
+static uint64_t start_cycles = 0;
+
+void init_target() {
+  // enable_fext();
+#ifdef USE_VEXT
+  // enable_vext();
+#endif
+  start_cycles = rdcycle64();
+}
+
+void deinit_target() {
+  uint64_t stop_cycles = rdcycle64();
+  uint64_t diff_cycles = stop_cycles - start_cycles;
+  float diff_ms = 0;  // unimplemented (see RDCYCLE_PER_SECOND)
+  printf("Total Cycles: %lld\n", stop_cycles - start_cycles);
+}