mlonmcu 0.3.0.dev0__3-none-any.whl

resources/platforms/zephyr/project/lib/targets/corstone300.c

@@ -0,0 +1,62 @@
+#include <stdio.h>
+
+// DWT (Data Watchpoint and Trace) registers, only exists on ARM Cortex with a
+// DWT unit.
+#define KIN1_DWT_CONTROL (*((volatile uint32_t*)0xE0001000))
+
+// DWT Control register.
+#define KIN1_DWT_CYCCNTENA_BIT (1UL << 0)
+
+// CYCCNTENA bit in DWT_CONTROL register.
+#define KIN1_DWT_CYCCNT (*((volatile uint32_t*)0xE0001004))
+
+// DWT Cycle Counter register.
+#define KIN1_DEMCR (*((volatile uint32_t*)0xE000EDFC))
+
+// DEMCR: Debug Exception and Monitor Control Register.
+#define KIN1_TRCENA_BIT (1UL << 24)
+
+// Trace enable bit in DEMCR register.
+#define KIN1_LAR (*((volatile uint32_t*)0xE0001FB0))
+
+// Unlock access to DWT (ITM, etc.)registers.
+#define KIN1_UnlockAccessToDWT() KIN1_LAR = 0xC5ACCE55;
+
+// TRCENA: Enable trace and debug block DEMCR (Debug Exception and Monitor
+// Control Register.
+#define KIN1_InitCycleCounter() KIN1_DEMCR |= KIN1_TRCENA_BIT
+
+#define KIN1_ResetCycleCounter() KIN1_DWT_CYCCNT = 0
+#define KIN1_EnableCycleCounter() KIN1_DWT_CONTROL |= KIN1_DWT_CYCCNTENA_BIT
+#define KIN1_DisableCycleCounter() KIN1_DWT_CONTROL &= ~KIN1_DWT_CYCCNTENA_BIT
+#define KIN1_GetCycleCounter() KIN1_DWT_CYCCNT
+
+int32_t ticks_per_second() { return 25e6; }
+
+int32_t GetCurrentTimeTicks() { return KIN1_GetCycleCounter(); }
+
+extern void uart_init(void);
+
+static int32_t start_cycles = 0;
+
+void init_target() {
+  uart_init();
+  KIN1_UnlockAccessToDWT();
+  KIN1_InitCycleCounter();
+  KIN1_ResetCycleCounter();
+  KIN1_EnableCycleCounter();
+  int32_t ticks = GetCurrentTimeTicks();
+  start_cycles = ticks;
+  printf("GetCurrentTimeTicks=%ld\n", ticks);
+}
+
+void deinit_target() {
+  int32_t stop_cycles = GetCurrentTimeTicks();
+  int32_t diff_cycles = stop_cycles - start_cycles;
+  // int32_t diff_ms = diff_cycles / (ticks_per_second() / 1000);
+  // printf("Total Time: %ld ms\n", diff_ms);
+  printf("Total Cycles: %ld\n", diff_cycles);
+  printf("EXITTHESIM\n");
+  while (1)
+    ;
+}

resources/platforms/zephyr/project/lib/targets/default.c

@@ -0,0 +1,2 @@
+__attribute__((weak)) void init_target() {}
+__attribute__((weak)) void deinit_target() {}

resources/platforms/zephyr/project/lib/targets/etiss_pulpino.c

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+#include <stdio.h>
+
+/* How many cycles (rdcycle) per second (OVPsim and Spike). */
+#define RDCYCLE_PER_SECOND 100000000UL
+
+/**
+ * @brief Returns the number of clock cycles executed by the processor.
+ * Overflows after 42.9 seconds on a 100 MIPS and with CPI = 1 (OVPsim).
+ */
+static inline uint32_t rdcycle(void) {
+#if defined(__riscv) || defined(__riscv__)
+  uint32_t cycles;
+  __asm__ volatile("rdcycle %0" : "=r"(cycles));
+  return cycles;
+#else
+  return 0;
+#endif
+}
+
+/**
+ * @brief Returns the full 64bit register cycle register, which holds the
+ * number of clock cycles executed by the processor.
+ */
+static inline uint64_t rdcycle64() {
+#if defined(__riscv) || defined(__riscv__)
+  uint32_t cycles;
+  uint32_t cyclesh1;
+  uint32_t cyclesh2;
+
+  /* Reads are not atomic. So ensure, that we are never reading inconsistent
+   * values from the 64bit hardware register. */
+  do {
+    __asm__ volatile("rdcycleh %0" : "=r"(cyclesh1));
+    __asm__ volatile("rdcycle %0" : "=r"(cycles));
+    __asm__ volatile("rdcycleh %0" : "=r"(cyclesh2));
+  } while (cyclesh1 != cyclesh2);
+
+  return (((uint64_t)cyclesh1) << 32) | cycles;
+#else
+  return 0;
+#endif
+}
+
+/* How many time cycles (rdtime) per second (OVPsim and Spike). */
+#define RDTIME_PER_SECOND 1000000UL
+
+/**
+ * @brief Returns wall-clock real time that has passed from an arbitrary start time in the past.
+ */
+static inline uint32_t rdtime(void) {
+#if defined(__riscv) || defined(__riscv__)
+  uint32_t time;
+  __asm__ volatile("rdtime %0" : "=r"(time));
+  return time;
+#else
+  return 0;
+#endif
+}
+
+/**
+ * @brief Returns the number of instructions retired by the processor.
+ */
+static inline uint32_t rdinstret(void) {
+#if defined(__riscv) || defined(__riscv__)
+  uint32_t instret;
+  __asm__ volatile("rdinstret %0" : "=r"(instret));
+  return instret;
+#else
+  return 0;
+#endif
+}
+
+/**
+ * @brief Enables the vector extension (as well as the floating point extension).
+ */
+static inline void enable_fext(void)
+{
+#if defined(__riscv) || defined(__riscv__)
+    __asm__ volatile("li t0, 1<<13 \n"
+                     "csrs mstatus, t0 \n" ::
+                         : "t0");
+#endif
+}
+
+/**
+ * @brief Enables the vector extension (as well as the floating point extension).
+ */
+static inline void enable_vext(void)
+{
+#if defined(__riscv) || defined(__riscv__)
+    __asm__ volatile("li t0, 1<<9+1<<13 \n"
+                     "csrs mstatus, t0 \n" ::
+                         : "t0");
+#endif
+}
+
+static uint64_t start_cycles = 0;
+
+void init_target() {
+  // enable_fext();
+#ifdef USE_VEXT
+  // enable_vext();
+#endif
+  start_cycles = rdcycle64();
+}
+
+void deinit_target() {
+  uint64_t stop_cycles = rdcycle64();
+  uint64_t diff_cycles = stop_cycles - start_cycles;
+  float diff_ms = 0;  // unimplemented (see RDCYCLE_PER_SECOND)
+  printf("Total Cycles: %lld\n", stop_cycles - start_cycles);
+}

resources/platforms/zephyr/project/lib/targets/generic_riscv.c

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+#include <stdio.h>
+
+/* How many cycles (rdcycle) per second (OVPsim and Spike). */
+#define RDCYCLE_PER_SECOND 100000000UL
+
+/**
+ * @brief Returns the number of clock cycles executed by the processor.
+ * Overflows after 42.9 seconds on a 100 MIPS and with CPI = 1 (OVPsim).
+ */
+static inline uint32_t rdcycle(void) {
+#if defined(__riscv) || defined(__riscv__)
+  uint32_t cycles;
+  __asm__ volatile("rdcycle %0" : "=r"(cycles));
+  return cycles;
+#else
+  return 0;
+#endif
+}
+
+/**
+ * @brief Returns the full 64bit register cycle register, which holds the
+ * number of clock cycles executed by the processor.
+ */
+static inline uint64_t rdcycle64() {
+#if defined(__riscv) || defined(__riscv__)
+  uint32_t cycles;
+  uint32_t cyclesh1;
+  uint32_t cyclesh2;
+
+  /* Reads are not atomic. So ensure, that we are never reading inconsistent
+   * values from the 64bit hardware register. */
+  do {
+    __asm__ volatile("rdcycleh %0" : "=r"(cyclesh1));
+    __asm__ volatile("rdcycle %0" : "=r"(cycles));
+    __asm__ volatile("rdcycleh %0" : "=r"(cyclesh2));
+  } while (cyclesh1 != cyclesh2);
+
+  return (((uint64_t)cyclesh1) << 32) | cycles;
+#else
+  return 0;
+#endif
+}
+
+/* How many time cycles (rdtime) per second (OVPsim and Spike). */
+#define RDTIME_PER_SECOND 1000000UL
+
+/**
+ * @brief Returns wall-clock real time that has passed from an arbitrary start time in the past.
+ */
+static inline uint32_t rdtime(void) {
+#if defined(__riscv) || defined(__riscv__)
+  uint32_t time;
+  __asm__ volatile("rdtime %0" : "=r"(time));
+  return time;
+#else
+  return 0;
+#endif
+}
+
+/**
+ * @brief Returns the number of instructions retired by the processor.
+ */
+static inline uint32_t rdinstret(void) {
+#if defined(__riscv) || defined(__riscv__)
+  uint32_t instret;
+  __asm__ volatile("rdinstret %0" : "=r"(instret));
+  return instret;
+#else
+  return 0;
+#endif
+}
+
+/**
+ * @brief Enables the vector extension (as well as the floating point extension).
+ */
+static inline void enable_fext(void)
+{
+#if defined(__riscv) || defined(__riscv__)
+    __asm__ volatile("li t0, 1<<13 \n"
+                     "csrs mstatus, t0 \n" ::
+                         : "t0");
+#endif
+}
+
+/**
+ * @brief Enables the vector extension (as well as the floating point extension).
+ */
+static inline void enable_vext(void)
+{
+#if defined(__riscv) || defined(__riscv__)
+    __asm__ volatile("li t0, 1<<9+1<<13 \n"
+                     "csrs mstatus, t0 \n" ::
+                         : "t0");
+#endif
+}
+
+static uint64_t start_cycles = 0;
+
+void init_target() {
+  // enable_fext();
+#ifdef USE_VEXT
+  // enable_vext();
+#endif
+  start_cycles = rdcycle64();
+}
+
+void deinit_target() {
+  uint64_t stop_cycles = rdcycle64();
+  uint64_t diff_cycles = stop_cycles - start_cycles;
+  float diff_ms = 0;  // unimplemented (see RDCYCLE_PER_SECOND)
+  printf("Total Cycles: %lld\n", stop_cycles - start_cycles);
+}

resources/platforms/zephyr/project/lib/targets/riscv_qemu.c

@@ -0,0 +1,112 @@
+#include <stdio.h>
+
+/* How many cycles (rdcycle) per second (OVPsim and Spike). */
+#define RDCYCLE_PER_SECOND 100000000UL
+
+/**
+ * @brief Returns the number of clock cycles executed by the processor.
+ * Overflows after 42.9 seconds on a 100 MIPS and with CPI = 1 (OVPsim).
+ */
+static inline uint32_t rdcycle(void) {
+#if defined(__riscv) || defined(__riscv__)
+  uint32_t cycles;
+  __asm__ volatile("rdcycle %0" : "=r"(cycles));
+  return cycles;
+#else
+  return 0;
+#endif
+}
+
+/**
+ * @brief Returns the full 64bit register cycle register, which holds the
+ * number of clock cycles executed by the processor.
+ */
+static inline uint64_t rdcycle64() {
+#if defined(__riscv) || defined(__riscv__)
+  uint32_t cycles;
+  uint32_t cyclesh1;
+  uint32_t cyclesh2;
+
+  /* Reads are not atomic. So ensure, that we are never reading inconsistent
+   * values from the 64bit hardware register. */
+  do {
+    __asm__ volatile("rdcycleh %0" : "=r"(cyclesh1));
+    __asm__ volatile("rdcycle %0" : "=r"(cycles));
+    __asm__ volatile("rdcycleh %0" : "=r"(cyclesh2));
+  } while (cyclesh1 != cyclesh2);
+
+  return (((uint64_t)cyclesh1) << 32) | cycles;
+#else
+  return 0;
+#endif
+}
+
+/* How many time cycles (rdtime) per second (OVPsim and Spike). */
+#define RDTIME_PER_SECOND 1000000UL
+
+/**
+ * @brief Returns wall-clock real time that has passed from an arbitrary start time in the past.
+ */
+static inline uint32_t rdtime(void) {
+#if defined(__riscv) || defined(__riscv__)
+  uint32_t time;
+  __asm__ volatile("rdtime %0" : "=r"(time));
+  return time;
+#else
+  return 0;
+#endif
+}
+
+/**
+ * @brief Returns the number of instructions retired by the processor.
+ */
+static inline uint32_t rdinstret(void) {
+#if defined(__riscv) || defined(__riscv__)
+  uint32_t instret;
+  __asm__ volatile("rdinstret %0" : "=r"(instret));
+  return instret;
+#else
+  return 0;
+#endif
+}
+
+/**
+ * @brief Enables the vector extension (as well as the floating point extension).
+ */
+static inline void enable_fext(void)
+{
+#if defined(__riscv) || defined(__riscv__)
+    __asm__ volatile("li t0, 1<<13 \n"
+                     "csrs mstatus, t0 \n" ::
+                         : "t0");
+#endif
+}
+
+/**
+ * @brief Enables the vector extension (as well as the floating point extension).
+ */
+static inline void enable_vext(void)
+{
+#if defined(__riscv) || defined(__riscv__)
+    __asm__ volatile("li t0, 1<<9+1<<13 \n"
+                     "csrs mstatus, t0 \n" ::
+                         : "t0");
+#endif
+}
+
+static uint64_t start_cycles = 0;
+
+void init_target() {
+  enable_fext();
+#ifdef USE_VEXT
+  enable_vext();
+#endif
+  start_cycles = rdcycle64();
+}
+
+void deinit_target() {
+  uint64_t stop_cycles = rdcycle64();
+  uint64_t diff_cycles = stop_cycles - start_cycles;
+  float diff_ms = 0;  // unimplemented (see RDCYCLE_PER_SECOND)
+  printf("Total Cycles: %lld\n", stop_cycles - start_cycles);
+}

resources/platforms/zephyr/project/lib/targets/target.h

@@ -0,0 +1,2 @@
+void init_target();
+void deinit_target();

resources/platforms/zephyr/project/prj.conf

@@ -0,0 +1,11 @@
+CONFIG_NEWLIB_LIBC=n
+CONFIG_MLONMCU_FRAMEWORK="tvm"
+CONFIG_MLONMCU_BACKEND="tvmaot"
+CONFIG_TVM_DIR="/nas/ei/share/TUEIEDAscratch/ga87puy/work/mlonmcu/workspace/deps/src/tvm"
+CONFIG_TF_DIR="?"
+CONFIG_MLONMCU_CODEGEN_DIR="/work/tools/zephyr_stuff/run/"
+CONFIG_CPLUSPLUS=y
+CONFIG_STD_CPP17=y
+CONFIG_LIB_CPLUSPLUS=y
+CONFIG_EXCEPTIONS=y
+CONFIG_REBOOT=y

resources/platforms/zephyr/project/sample.yaml

@@ -0,0 +1,19 @@
+sample:
+  description: Hello World sample, the simplest Zephyr
+    application
+  name: hello world
+common:
+    tags: introduction
+    integration_platforms:
+      - native_posix
+    harness: console
+    harness_config:
+      type: one_line
+      regex:
+        - "Hello World! (.*)"
+tests:
+  sample.basic.helloworld:
+    tags: introduction
+  sample.basic.helloworld.uefi:
+    platform_allow: qemu_x86_64
+    extra_args: CONF_FILE=prj_uefi.conf

resources/platforms/zephyr/project/src/main.c

@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2012-2014 Wind River Systems, Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr.h>
+#include <stdint.h>
+#include <sys/printk.h>
+#include <sys/reboot.h>
+#include <timing/timing.h>
+// #include <zephyr/kernel.h>
+
+// void init_target();
+// void deinit_target();
+
+int main() {
+  // init_target();
+  timing_init();
+  timing_start();
+  printk("MLonMCU: START\n");
+  // uint32_t start_time;
+  // uint32_t start_time_;
+  // uint32_t stop_time;
+  // uint32_t stop_time_;
+  // uint32_t cycles_spent;
+  // uint64_t cycles_spent_;
+  // uint32_t nanoseconds_spent;
+  // uint64_t nanoseconds_spent_;
+  /* capture initial time stamp */
+  // start_time = k_cycle_get_32();
+  // start_time_ = k_cycle_get_64();
+  timing_t start_time, end_time;
+  // printk("start_time_=%llu", start_time_);
+  start_time = timing_counter_get();
+  mlif_run();
+  // stop_time = k_cycle_get_32();
+  // stop_time_ = k_cycle_get_64();
+  end_time = timing_counter_get();
+  uint64_t cycles = timing_cycles_get(&start_time, &end_time);
+  uint64_t ns_spent = timing_cycles_to_ns(cycles);
+  // printk("stop_time_=%llu", stop_time_);
+
+  /* compute how long the work took (assumes no counter rollover) */
+  // if (start_time >= stop_time) {
+  //     cycles_spent_ = stop_time - start_time;
+  // } else {
+  //     cycles_spent_ = stop_time + ((1 << 31) - start_time);
+  // }
+  // cycles_spent_ = stop_time_ - start_time_;
+  // nanoseconds_spent = k_cyc_to_ns_ceil32(cycles_spent);
+  // nanoseconds_spent_ = k_cyc_to_ns_ceil64(cycles_spent_);
+  // printk("Total Time: %u us\n", (uint32_t) (nanoseconds_spent/1000));
+  printk("Total Time: %llu us\n", (ns_spent/1000));
+  // printk("Total Cycles: %u\n", cycles_spent);
+  printk("Total Cycles: %llu\n", cycles);
+  printk("MLonMCU: STOP\n");
+  // deinit_target();
+  sys_reboot(0);
+  return 0;
+}
+//
+// /* do work for some (short) period of time */
+// ...
+//
+// /* capture final time stamp */
+// stop_time = k_cycle_get_32();
+//
+// /* compute how long the work took (assumes no counter rollover) */
+// cycles_spent = stop_time - start_time;
+// nanoseconds_spent = SYS_CLOCK_HW_CYCLES_TO_NS(cycles_spent);

resources/platforms/zephyr/project2/CMakeLists.txt

@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: Apache-2.0
+
+cmake_minimum_required(VERSION 3.20.0)
+
+find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
+project(mlonmcu_template)
+SET(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} "${CMAKE_CURRENT_SOURCE_DIR}/cmake")
+
+SET(TVM_ALIGNMENT_BYTES 4)
+
+# cmake-format: off
+SET(TVM_HEADERS
+    ${CONFIG_TVM_DIR}/include
+    ${CONFIG_TVM_DIR}/3rdparty/dlpack/include
+    ${CONFIG_TVM_DIR}/apps/bundle_deploy
+    ${CONFIG_TVM_DIR}/src/runtime/crt/include
+)
+# cmake-format: on
+
+IF(CONFIG_TVM_CRT_CONFIG_DIR)
+    LIST(APPEND TVM_HEADERS ${CONFIG_TVM_CRT_CONFIG_DIR})
+ELSE()
+    LIST(APPEND TVM_HEADERS ${CONFIG_TVM_DIR}/apps/bundle_deploy/crt_config)
+ENDIF()
+
+INCLUDE(backends/${CONFIG_MLONMCU_BACKEND})
+INCLUDE(frameworks/${CONFIG_MLONMCU_FRAMEWORK})
+
+TARGET_INCLUDE_DIRECTORIES(app PUBLIC ${TVM_HEADERS})
+
+TARGET_COMPILE_DEFINITIONS(app PUBLIC
+    -DTVM_RUNTIME_ALLOC_ALIGNMENT_BYTES=${TVM_ALIGNMENT_BYTES}
+)
+
+
+
+INCLUDE(extras)
+
+INCLUDE(frameworks/${CONFIG_MLONMCU_FRAMEWORK}_mlif)
+
+IF(CONFIG_MODEL_DIR)
+    GET_FILENAME_COMPONENT(MODEL_SUPPORT_DIR ${CONFIG_MODEL_DIR}/support REALPATH)
+    GET_FILENAME_COMPONENT(MODEL_NAME ${CONFIG_MODEL_DIR} NAME)
+ENDIF()
+
+IF(MODEL_SUPPORT_DIR AND EXISTS ${MODEL_SUPPORT_DIR})
+    ADD_SUBDIRECTORY(${MODEL_SUPPORT_DIR} model_support_bin_${MODEL_NAME})
+ELSE()
+    ADD_SUBDIRECTORY(default_model_support)
+ENDIF()
+
+IF(NOT CONFIG_DATA_SRC)
+    SET(CONFIG_DATA_SRC "default_data.c")
+ENDIF()
+
+IF(CONFIG_NUM_RUNS)
+    TARGET_COMPILE_DEFINITIONS(${PROJECT_NAME} PUBLIC NUM_RUNS=${CONFIG_NUM_RUNS})
+ENDIF()
+
+TARGET_INCLUDE_DIRECTORIES(app PUBLIC ${TVM_HEADERS} ${TVM_OUT_DIR}/include ${CONFIG_MLONMCU_CODEGEN_DIR} lib/support)
+SET(TVM_WRAPPER_FILENAME aot_wrapper.c)
+SET(EXTRA_SRC ${EXTRA_SRC} ${CONFIG_MLONMCU_CODEGEN_DIR}/${TVM_WRAPPER_FILENAME})
+target_sources(app PRIVATE
+    src/main.c
+    ml_interface.c
+    ${CONFIG_TVM_DIR}/src/runtime/crt/common/crt_backend_api.c
+    ${CONFIG_TVM_DIR}/src/runtime/crt/memory/stack_allocator.c
+    ${CONFIG_DATA_SRC}
+    ${EXTRA_SRC}
+    ${TVM_SRCS}
+)
+target_link_libraries(app PRIVATE model_support)

resources/platforms/zephyr/project2/Kconfig

@@ -0,0 +1,101 @@
+mainmenu "MLonMCU"
+
+source "Kconfig.zephyr"
+menu "MLonMCU Options"
+
+    config MLONMCU_CODEGEN_DIR
+        string "Codegen Directory"
+        default "$(CODEGEN_SRC)"
+        help
+            Path to the directory with the codegen results.
+
+    # choice MLONMCU_FRAMEWORK
+    #     prompt "MLonMCU framework"
+    #     default MLONMCU_FRAMEWORK_TFLM
+    #     help
+    #         Choose a MLonMCU framework from the list.
+
+    #     config MLONMCU_FRAMEWORK_TFLM
+    #         bool "TFLite Micro"
+    #     config MLONMCU_FRAMEWORK_TVM
+    #         bool "TVM"
+    # endchoice
+
+    config MLONMCU_FRAMEWORK
+        string "Ued Framework"
+        # default "tflm" if MLONMCU_FRAMEWORK_TFLM
+        # default "tvm" if MLONMCU_FRAMEWORK_TVM
+        default "none"
+        help
+            TODO
+
+    # choice MLONMCU_BACKEND
+    #     prompt "MLonMCU backend"
+    #     default MLONMCU_BACKEND_TFLMI if MLONMCU_FRAMEWORK_TFLM
+    #     default MLONMCU_BACKEND_TVMAOT if MLONMCU_FRAMEWORK_TVM
+    #     help
+    #         Choose a MLonMCU backend for the chosen framwork.
+
+    #     config MLONMCU_BACKEND_TFLMI
+    #         bool "TFLite Micro Default Interpreter"
+    #         depends on MLONMCU_FRAMEWORK_TFLM
+    #     config MLONMCU_BACKEND_TFLMC
+    #         bool "TFLite Micro Compiler"
+    #         depends on MLONMCU_FRAMEWORK_TFLM
+    #     config MLONMCU_BACKEND_TVMAOT
+    #         bool "TVM AoT Executor"
+    #         depends on MLONMCU_FRAMEWORK_TVM
+    #     config MLONMCU_BACKEND_TVMRT
+    #         bool "TVM Graph Executor"
+    #         depends on MLONMCU_FRAMEWORK_TVM
+    #     config MLONMCU_BACKEND_TVMCG
+    #         bool "TVM Custom Codegenerator"
+    #         depends on MLONMCU_FRAMEWORK_TVM
+    # endchoice
+
+    config MLONMCU_BACKEND
+        string "Used backend"
+        default "none"
+        help
+            TODO
+
+    config MLONMCU_NUM_RUNS
+        int "Number of inferences"
+        default 1
+        help
+            How many times the network should be invoked. A negative value maps to a infinite number of runs.
+
+    config MLONMCU_VALIDATE
+        bool "Validate model output data"
+        default false
+        help
+            Compare model outputs with expected results (if available). Only works in DEBUG mode.
+
+    config MLONMCU_MODLE_DIR
+        string "Model Directory"
+        depends on MLONMCU_VALIDATE
+        default "$(MODEL_DIR)"
+        help
+            Directory where model support code and reference data can be found.
+endmenu
+
+menu "TVM Build Options"
+    config TVM_DIR
+        string "Path to TVM"
+        default "$(TVM_SRC)"
+        help
+            TVM directory path.
+    config TVM_CRT_CONFIG_DIR
+        string "Path to TVM CRT config directory"
+        default ""
+        help
+            TVM crt path.
+endmenu
+menu "TFLite Micro Build Options"
+
+    config TF_DIR
+        string "Path to TFLite Micro"
+        default "$(TF_SRC)"
+        help
+            TFLite Micro directory path.
+endmenu