librelane 2.4.0__py3-none-any.whl

librelane/scripts/pyosys/ys_common.py

@@ -0,0 +1,153 @@
+# Copyright 2020-2024 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+import os
+import sys
+from typing import Iterable, List, Union
+
+try:
+    import libyosys as ys
+except ImportError:
+    try:
+        from pyosys import libyosys as ys
+    except ImportError:
+        ys.log_error(
+            "Could not find pyosys in 'PYTHONPATH'-- make sure Yosys is compiled with ENABLE_PYTHON set to 1.",
+            file=sys.stderr,
+        )
+        exit(-1)
+
+
+def _Design_run_pass(self, *command):
+    ys.Pass.call__YOSYS_NAMESPACE_RTLIL_Design__std_vector_string_(self, list(command))
+
+
+ys.Design.run_pass = _Design_run_pass  # type: ignore
+
+
+def _Design_tee(self, *command: Union[List[str], str], o: str):
+    self.run_pass("tee", "-o", o, *command)
+
+
+ys.Design.tee = _Design_tee  # type: ignore
+
+
+def _Design_read_verilog_files(
+    self: ys.Design,
+    files: Iterable[str],
+    *,
+    top: str,
+    synth_parameters: Iterable[str],
+    includes: Iterable[str],
+    defines: Iterable[str],
+    use_synlig: bool = False,
+    synlig_defer: bool = False,
+):
+    files = list(files)  # for easier concatenation
+    include_args = [f"-I{dir}" for dir in includes]
+    define_args = [f"-D{define}" for define in defines]
+    chparams = {}
+    synlig_chparam_args = []
+    for chparam in synth_parameters:
+        param, value = chparam.split("=", maxsplit=1)  # validate
+        chparams[param] = value
+        synlig_chparam_args.append(f"-P{param}={value}")
+
+    if use_synlig and synlig_defer:
+        self.run_pass("plugin", "-i", "synlig-sv")
+        for file in files:
+            self.run_pass(
+                "read_systemverilog",
+                "-defer",
+                "-sverilog",
+                *define_args,
+                *include_args,
+                file,
+            )
+        self.run_pass(
+            "read_systemverilog",
+            "-link",
+            "-sverilog",
+            "-top",
+            top,
+            *synlig_chparam_args,
+        )
+    elif use_synlig:
+        self.run_pass("plugin", "-i", "synlig-sv")
+        self.run_pass(
+            "read_systemverilog",
+            "-sverilog",
+            "-top",
+            top,
+            *define_args,
+            *include_args,
+            *synlig_chparam_args,
+            *files,
+        )
+    else:
+        for file in files:
+            self.run_pass(
+                "read_verilog",
+                "-defer",
+                "-noautowire",
+                "-sv",
+                *include_args,
+                *define_args,
+                file,
+            )
+        for param, value in chparams.items():
+            self.run_pass("chparam", "-set", param, value, top)
+
+
+ys.Design.read_verilog_files = _Design_read_verilog_files  # type: ignore
+
+
+def _Design_add_blackbox_models(
+    self,
+    models: Iterable[str],
+    *,
+    includes: Iterable[str],
+    defines: Iterable[str],
+):
+    include_args = [f"-I{dir}" for dir in includes]
+    define_args = [f"-D{define}" for define in defines]
+
+    for model in models:
+        model_path, ext = os.path.splitext(model)
+        if ext == ".gz":
+            # Yosys transparently handles gzip compression
+            model_path, ext = os.path.splitext(model_path)
+
+        if ext in [".v", ".sv", ".vh"]:
+            self.run_pass(
+                "read_verilog", "-sv", "-lib", *include_args, *define_args, model
+            )
+        elif ext in [".lib"]:
+            self.run_pass(
+                "read_liberty",
+                "-lib",
+                "-ignore_miss_dir",
+                "-setattr",
+                "blackbox",
+                model,
+            )
+        else:
+            ys.log_error(
+                f"Black-box model '{model}' has an unrecognized file extension: '{ext}'.",
+                file=sys.stderr,
+            )
+            sys.stderr.flush()
+            exit(-1)
+
+
+ys.Design.add_blackbox_models = _Design_add_blackbox_models  # type: ignore

librelane/scripts/tclsh/hello.tcl

@@ -0,0 +1 @@
+puts stdout "Hello, $::env(USER)!"

librelane/state/__init__.py

@@ -0,0 +1,24 @@
+# Copyright 2023 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+"""
+The State Module
+----------------
+
+This module manages the State of a Design before and after the execution of an
+LibreLane step. The State is essentially a list of views in various formats in
+addition to the cumulative set of metrics created by previous Steps.
+"""
+from .design_format import DesignFormat, DesignFormatObject
+from .state import State, InvalidState, StateElement

librelane/state/__main__.py

@@ -0,0 +1,61 @@
+# Copyright 2023 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+import sys
+import json
+from typing import Optional
+
+import cloup
+
+from ..common import get_latest_file
+from ..common.cli import formatter_settings
+
+
+@cloup.group(
+    no_args_is_help=True,
+    formatter_settings=formatter_settings,
+)
+def cli():
+    pass
+
+
+@cloup.command()
+@cloup.option(
+    "--extract-metrics-to",
+    default=None,
+)
+@cloup.argument("run_dir")
+def latest(extract_metrics_to: Optional[str], run_dir: str):
+    exit_code = 0
+
+    if latest_state := get_latest_file(run_dir, "state_*.json"):
+        try:
+            state = json.load(open(latest_state, encoding="utf8"))
+        except json.JSONDecodeError as e:
+            print(f"Latest state at {latest_state} is invalid: {e}", file=sys.stderr)
+            exit(1)
+        metrics = state["metrics"]
+        print(latest_state, end="")
+        if output := extract_metrics_to:
+            json.dump(metrics, open(output, "w", encoding="utf8"))
+    else:
+        print("No state_*.json files found", file=sys.stderr)
+        exit_code = 1
+
+    exit(exit_code)
+
+
+cli.add_command(latest)
+
+if __name__ == "__main__":
+    cli()

librelane/state/design_format.py

@@ -0,0 +1,195 @@
+# Copyright 2023 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+from enum import Enum
+from typing import Dict, Optional
+from dataclasses import dataclass, replace
+
+
+@dataclass
+class DesignFormatObject:
+    """
+    Metadata about the various possible text or binary representations (views)
+    of any design.
+
+    For example, ``DesignFormat.NETLIST.value`` has the metadata for Netlist
+    views.
+
+    :param id: A lowercase alphanumeric identifier for the design format.
+        Some IDs in LibreLane 2.X use dashes. This is an inconsistency that will
+        be addressed in the next major version of LibreLane as it would be a
+        breaking change.
+    :param extension: The file extension for designs saved in this format.
+    :param name: A human-readable name for this design format.
+    :param folder_override: The subdirectory when
+        :meth:`librelane.state.State.save_snapshot` is called on a state. If
+        unset, the value for ``id`` will be used.
+    :param multiple: Whether this view may have multiple files (typically, files
+        that are different across multiple corners or similar.)
+    """
+
+    id: str
+    extension: str
+    name: str
+    folder_override: Optional[str] = None
+    multiple: bool = False
+
+    _instance_optional: bool = False
+
+    @property
+    def folder(self) -> str:
+        return self.folder_override or self.id
+
+    @property
+    def optional(self) -> bool:
+        return self._instance_optional
+
+
+class DesignFormat(Enum):
+    """
+    An `enumeration <https://docs.python.org/3/library/enum.html>`_ of a number
+    of :class:`librelane.state.DesignFormatObject`\\s representing the various
+    possible text or binary representations (views) supported by LibreLane
+    states.
+
+    Members of this enumeration are used as the keys of
+    :class:`librelane.state.State` objects.
+    """
+
+    NETLIST: DesignFormatObject = DesignFormatObject(
+        "nl",
+        "nl.v",
+        "Verilog Netlist",
+    )
+    POWERED_NETLIST: DesignFormatObject = DesignFormatObject(
+        "pnl",
+        "pnl.v",
+        "Powered Verilog Netlist",
+    )
+    POWERED_NETLIST_SDF_FRIENDLY: DesignFormatObject = DesignFormatObject(
+        "pnl-sdf-friendly",
+        "pnl-sdf.v",
+        "Powered Verilog Netlist For SDF Simulation (Without Fill Cells)",
+        folder_override="pnl",
+    )
+    POWERED_NETLIST_NO_PHYSICAL_CELLS: DesignFormatObject = DesignFormatObject(
+        "pnl-npc",
+        "pnl-npc.v",
+        "Powered Verilog Netlist Without Physical Cells (Fill Cells and Diode Cells)",
+        folder_override="pnl",
+    )
+
+    DEF: DesignFormatObject = DesignFormatObject(
+        "def",
+        "def",
+        "Design Exchange Format",
+    )
+    LEF: DesignFormatObject = DesignFormatObject(
+        "lef",
+        "lef",
+        "Library Exchange Format",
+    )
+    OPENROAD_LEF: DesignFormatObject = DesignFormatObject(
+        "openroad-lef",
+        "openroad.lef",
+        "Library Exchange Format Generated by OpenROAD",
+        folder_override="lef",
+    )
+    ODB: DesignFormatObject = DesignFormatObject(
+        "odb",
+        "odb",
+        "OpenDB Database",
+    )
+
+    SDC: DesignFormatObject = DesignFormatObject(
+        "sdc",
+        "sdc",
+        "Design Constraints",
+    )
+    SDF: DesignFormatObject = DesignFormatObject(
+        "sdf",
+        "sdf",
+        "Standard Delay Format",
+        multiple=True,
+    )
+    SPEF: DesignFormatObject = DesignFormatObject(
+        "spef",
+        "spef",
+        "Standard Parasitics Extraction Format",
+        multiple=True,  # nom, min, max, ...
+    )
+    LIB: DesignFormatObject = DesignFormatObject(
+        "lib",
+        "lib",
+        "LIB Timing Library Format",
+        multiple=True,
+    )
+    SPICE: DesignFormatObject = DesignFormatObject(
+        "spice",
+        "spice",
+        "Simulation Program with Integrated Circuit Emphasis",
+    )
+
+    MAG: DesignFormatObject = DesignFormatObject(
+        "mag",
+        "mag",
+        "Magic VLSI View",
+    )
+
+    GDS: DesignFormatObject = DesignFormatObject(
+        "gds",
+        "gds",
+        "GDSII Stream",
+    )
+    MAG_GDS: DesignFormatObject = DesignFormatObject(
+        "mag_gds",
+        "magic.gds",
+        "GDSII Stream (Magic)",
+    )
+    KLAYOUT_GDS: DesignFormatObject = DesignFormatObject(
+        "klayout_gds",
+        "klayout.gds",
+        "GDSII Stream (KLayout)",
+    )
+
+    JSON_HEADER: DesignFormatObject = DesignFormatObject(
+        "json_h",
+        "h.json",
+        "Design JSON Header File",
+    )
+    VERILOG_HEADER: DesignFormatObject = DesignFormatObject(
+        "vh",
+        "vh",
+        "Verilog Header",
+    )
+
+    def __str__(self) -> str:
+        return self.value.id
+
+    @staticmethod
+    def by_id(id: str) -> Optional["DesignFormat"]:
+        return _designformat_by_id.get(id)
+
+    def mkOptional(self) -> "DesignFormat":
+        # HACK: Create ephemeral DesignFormat copy until 3.0.0 lets us do this
+        # a bit more appropriately.
+        clone = object.__new__(DesignFormat)
+        clone._name_ = self._name_
+        clone._value_ = replace(self._value_)
+        clone._value_._instance_optional = True
+        return clone
+
+
+_designformat_by_id: Dict[str, "DesignFormat"] = {
+    format.value.id: format for format in DesignFormat
+}