librelane 2.4.0__py3-none-any.whl

librelane/examples/spm-user_project_wrapper/user_project_wrapper.v

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+// SPDX-FileCopyrightText: 2020-2024 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ *-------------------------------------------------------------
+ *
+ * user_project_wrapper
+ *
+ * This wrapper enumerates all of the pins available to the
+ * user for the user project.
+ *
+ * An example user project is provided in this wrapper.  The
+ * example should be removed and replaced with the actual
+ * user project.
+ *
+ *-------------------------------------------------------------
+ */
+
+module user_project_wrapper #(
+    parameter BITS = 32
+) (
+`ifdef USE_POWER_PINS
+    inout vdda1,	// User area 1 3.3V supply
+    inout vdda2,	// User area 2 3.3V supply
+    inout vssa1,	// User area 1 analog ground
+    inout vssa2,	// User area 2 analog ground
+    inout vccd1,	// User area 1 1.8V supply
+    inout vccd2,	// User area 2 1.8v supply
+    inout vssd1,	// User area 1 digital ground
+    inout vssd2,	// User area 2 digital ground
+`endif
+
+    // Wishbone Slave ports (WB MI A)
+    input wb_clk_i,
+    input wb_rst_i,
+    input wbs_stb_i,
+    input wbs_cyc_i,
+    input wbs_we_i,
+    input [3:0] wbs_sel_i,
+    input [31:0] wbs_dat_i,
+    input [31:0] wbs_adr_i,
+    output wbs_ack_o,
+    output [31:0] wbs_dat_o,
+
+    // Logic Analyzer Signals
+    input  [127:0] la_data_in,
+    output [127:0] la_data_out,
+    input  [127:0] la_oenb,
+
+    // IOs
+    input  [`MPRJ_IO_PADS-1:0] io_in,
+    output [`MPRJ_IO_PADS-1:0] io_out,
+    output [`MPRJ_IO_PADS-1:0] io_oeb,
+
+    // Analog (direct connection to GPIO pad---use with caution)
+    // Note that analog I/O is not available on the 7 lowest-numbered
+    // GPIO pads, and so the analog_io indexing is offset from the
+    // GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
+    inout [`MPRJ_IO_PADS-10:0] analog_io,
+
+    // Independent clock (on independent integer divider)
+    input   user_clock2,
+
+    // User maskable interrupt signals
+    output [2:0] user_irq
+);
+
+/*--------------------------------------*/
+/* User project is instantiated  here   */
+/*--------------------------------------*/
+
+SPM_example mprj (
+`ifdef USE_POWER_PINS
+	.vccd1(vccd1),	// User area 1 1.8V power
+	.vssd1(vssd1),	// User area 1 digital ground
+`endif
+
+    .wb_clk_i(wb_clk_i),
+    .wb_rst_i(wb_rst_i),
+
+    // MGMT SoC Wishbone Slave
+
+    .wbs_cyc_i(wbs_cyc_i),
+    .wbs_stb_i(wbs_stb_i),
+    .wbs_we_i(wbs_we_i),
+    .wbs_sel_i(wbs_sel_i),
+    .wbs_adr_i(wbs_adr_i),
+    .wbs_dat_i(wbs_dat_i),
+    .wbs_ack_o(wbs_ack_o),
+    .wbs_dat_o(wbs_dat_o),
+
+    // Logic Analyzer
+
+    .la_data_in(la_data_in),
+    .la_data_out(la_data_out),
+    .la_oenb (la_oenb),
+
+    // IO Pads
+
+    .io_in (io_in),
+    .io_out(io_out),
+    .io_oeb(io_oeb),
+
+    // IRQ
+    .irq(user_irq)
+);
+
+endmodule	// user_project_wrapper
+
+`default_nettype wire

librelane/flows/__init__.py

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+# Copyright 2023 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+"""
+The Flow Module
+---------------
+
+An API for implementing new flows using the LibreLane infrastructure, as well
+as a number of built-in flows.
+"""
+from .flow import FlowError, FlowException, FlowProgressBar, Flow
+from .sequential import SequentialFlow
+from . import builtins
+from .cli import cloup_flow_opts

librelane/flows/builtins.py

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+# Copyright 2023 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# flake8: noqa
+from .optimizing import Optimizing
+from .classic import Classic, VHDLClassic
+from .misc import OpenInKLayout, OpenInOpenROAD
+from .synth_explore import SynthesisExploration

librelane/flows/classic.py

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+# Copyright 2023 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+from .flow import Flow
+from .sequential import SequentialFlow
+from ..config import Variable
+from ..steps import (
+    Yosys,
+    OpenROAD,
+    Magic,
+    KLayout,
+    Odb,
+    Netgen,
+    Checker,
+    Verilator,
+    Misc,
+)
+
+
+@Flow.factory.register()
+class Classic(SequentialFlow):
+    """
+    A flow of type :class:`librelane.flows.SequentialFlow` that is the most
+    similar to the original OpenLane flow, running the Verilog RTL through
+    Yosys, OpenROAD, KLayout and Magic to produce a valid GDSII for simpler designs.
+
+    This is the default when using LibreLane via the command-line.
+    """
+
+    Steps = [
+        Verilator.Lint,
+        Checker.LintTimingConstructs,
+        Checker.LintErrors,
+        Checker.LintWarnings,
+        Yosys.JsonHeader,
+        Yosys.Synthesis,
+        Checker.YosysUnmappedCells,
+        Checker.YosysSynthChecks,
+        Checker.NetlistAssignStatements,
+        OpenROAD.CheckSDCFiles,
+        OpenROAD.CheckMacroInstances,
+        OpenROAD.STAPrePNR,
+        OpenROAD.Floorplan,
+        Odb.CheckMacroAntennaProperties,
+        Odb.SetPowerConnections,
+        Odb.ManualMacroPlacement,
+        OpenROAD.CutRows,
+        OpenROAD.TapEndcapInsertion,
+        Odb.AddPDNObstructions,
+        OpenROAD.GeneratePDN,
+        Odb.RemovePDNObstructions,
+        Odb.AddRoutingObstructions,
+        OpenROAD.GlobalPlacementSkipIO,
+        OpenROAD.IOPlacement,
+        Odb.CustomIOPlacement,
+        Odb.ApplyDEFTemplate,
+        OpenROAD.GlobalPlacement,
+        Odb.WriteVerilogHeader,
+        Checker.PowerGridViolations,
+        OpenROAD.STAMidPNR,
+        OpenROAD.RepairDesignPostGPL,
+        Odb.ManualGlobalPlacement,
+        OpenROAD.DetailedPlacement,
+        OpenROAD.CTS,
+        OpenROAD.STAMidPNR,
+        OpenROAD.ResizerTimingPostCTS,
+        OpenROAD.STAMidPNR,
+        OpenROAD.GlobalRouting,
+        OpenROAD.CheckAntennas,
+        OpenROAD.RepairDesignPostGRT,
+        Odb.DiodesOnPorts,
+        Odb.HeuristicDiodeInsertion,
+        OpenROAD.RepairAntennas,
+        OpenROAD.ResizerTimingPostGRT,
+        OpenROAD.STAMidPNR,
+        OpenROAD.DetailedRouting,
+        Odb.RemoveRoutingObstructions,
+        OpenROAD.CheckAntennas,
+        Checker.TrDRC,
+        Odb.ReportDisconnectedPins,
+        Checker.DisconnectedPins,
+        Odb.ReportWireLength,
+        Checker.WireLength,
+        OpenROAD.FillInsertion,
+        Odb.CellFrequencyTables,
+        OpenROAD.RCX,
+        OpenROAD.STAPostPNR,
+        OpenROAD.IRDropReport,
+        Magic.StreamOut,
+        KLayout.StreamOut,
+        Magic.WriteLEF,
+        Odb.CheckDesignAntennaProperties,
+        KLayout.XOR,
+        Checker.XOR,
+        Magic.DRC,
+        KLayout.DRC,
+        Checker.MagicDRC,
+        Checker.KLayoutDRC,
+        Magic.SpiceExtraction,
+        Checker.IllegalOverlap,
+        Netgen.LVS,
+        Checker.LVS,
+        Yosys.EQY,
+        Checker.SetupViolations,
+        Checker.HoldViolations,
+        Checker.MaxSlewViolations,
+        Checker.MaxCapViolations,
+        Misc.ReportManufacturability,
+    ]
+
+    config_vars = [
+        Variable(
+            "RUN_TAP_ENDCAP_INSERTION",
+            bool,
+            "Enables the OpenROAD.TapEndcapInsertion step.",
+            default=True,
+            deprecated_names=["TAP_DECAP_INSERTION", "RUN_TAP_DECAP_INSERTION"],
+        ),
+        Variable(
+            "RUN_POST_GPL_DESIGN_REPAIR",
+            bool,
+            "Enables resizer design repair after global placement using the OpenROAD.RepairDesignPostGPL step.",
+            default=True,
+            deprecated_names=["PL_RESIZER_DESIGN_OPTIMIZATIONS", "RUN_REPAIR_DESIGN"],
+        ),
+        Variable(
+            "RUN_POST_GRT_DESIGN_REPAIR",
+            bool,
+            "Enables resizer design repair after global placement using the OpenROAD.RepairDesignPostGPL step. This is experimental and may result in hangs and/or extended run times.",
+            default=False,
+        ),
+        Variable(
+            "RUN_CTS",
+            bool,
+            "Enables clock tree synthesis using the OpenROAD.CTS step.",
+            default=True,
+            deprecated_names=["CLOCK_TREE_SYNTH"],
+        ),
+        Variable(
+            "RUN_POST_CTS_RESIZER_TIMING",
+            bool,
+            "Enables resizer timing optimizations after clock tree synthesis using the OpenROAD.ResizerTimingPostCTS step.",
+            default=True,
+            deprecated_names=["PL_RESIZER_TIMING_OPTIMIZATIONS"],
+        ),
+        Variable(
+            "RUN_POST_GRT_RESIZER_TIMING",
+            bool,
+            "Enables resizer timing optimizations after global routing using the OpenROAD.ResizerTimingPostGRT step. This is experimental and may result in hangs and/or extended run times.",
+            default=False,
+            deprecated_names=["GLB_RESIZER_TIMING_OPTIMIZATIONS"],
+        ),
+        Variable(
+            "RUN_HEURISTIC_DIODE_INSERTION",
+            bool,
+            "Enables the Odb.HeuristicDiodeInsertion step.",
+            default=False,  # For compatibility with OL1
+        ),
+        Variable(
+            "RUN_ANTENNA_REPAIR",
+            bool,
+            "Enables the OpenROAD.RepairAntennas step.",
+            default=True,
+            deprecated_names=["GRT_REPAIR_ANTENNAS"],
+        ),
+        Variable(
+            "RUN_DRT",
+            bool,
+            "Enables the OpenROAD.DetailedRouting step.",
+            default=True,
+        ),
+        Variable(
+            "RUN_FILL_INSERTION",
+            bool,
+            "Enables the OpenROAD.FillInsertion step.",
+            default=True,
+        ),
+        Variable(
+            "RUN_MCSTA",
+            bool,
+            "Enables multi-corner static timing analysis using the OpenROAD.STAPostPNR step.",
+            default=True,
+            deprecated_names=["RUN_SPEF_STA"],
+        ),
+        Variable(
+            "RUN_SPEF_EXTRACTION",
+            bool,
+            "Enables parasitics extraction using the OpenROAD.RCX step.",
+            default=True,
+        ),
+        Variable(
+            "RUN_IRDROP_REPORT",
+            bool,
+            "Enables generation of an IR Drop report using the OpenROAD.IRDropReport step.",
+            default=True,
+        ),
+        Variable(
+            "RUN_LVS",
+            bool,
+            "Enables the Netgen.LVS step.",
+            default=True,
+        ),
+        Variable(
+            "RUN_MAGIC_STREAMOUT",
+            bool,
+            "Enables the Magic.StreamOut step to generate GDSII.",
+            default=True,
+            deprecated_names=["RUN_MAGIC"],
+        ),
+        Variable(
+            "RUN_KLAYOUT_STREAMOUT",
+            bool,
+            "Enables the KLayout.StreamOut step to generate GDSII.",
+            default=True,
+            deprecated_names=["RUN_KLAYOUT"],
+        ),
+        Variable(
+            "RUN_MAGIC_WRITE_LEF",
+            bool,
+            "Enables the Magic.WriteLEF step.",
+            default=True,
+            deprecated_names=["MAGIC_GENERATE_LEF"],
+        ),
+        Variable(
+            "RUN_KLAYOUT_XOR",
+            bool,
+            "Enables running the KLayout.XOR step on the two GDSII files generated by Magic and Klayout. Stream-outs for both KLayout and Magic should have already run, and the PDK must support both signoff tools.",
+            default=True,
+        ),
+        Variable(
+            "RUN_MAGIC_DRC",
+            bool,
+            "Enables the Magic.DRC step.",
+            default=True,
+        ),
+        Variable(
+            "RUN_KLAYOUT_DRC",
+            bool,
+            "Enables the KLayout.DRC step.",
+            default=True,
+        ),
+        Variable(
+            "RUN_EQY",
+            bool,
+            "Enables the Yosys.EQY step. Not valid for VHDLClassic.",
+            default=False,
+        ),
+        Variable(
+            "RUN_LINTER",
+            bool,
+            "Enables the Verilator.Lint step and associated checker steps. Not valid for VHDLClassic.",
+            default=True,
+            deprecated_names=["RUN_VERILATOR"],
+        ),
+    ]
+
+    gating_config_vars = {
+        "OpenROAD.RepairDesignPostGPL": ["RUN_POST_GPL_DESIGN_REPAIR"],
+        "OpenROAD.RepairDesignPostGRT": ["RUN_POST_GRT_DESIGN_REPAIR"],
+        "OpenROAD.ResizerTimingPostCTS": ["RUN_POST_CTS_RESIZER_TIMING"],
+        "OpenROAD.ResizerTimingPostGRT": ["RUN_POST_GRT_RESIZER_TIMING"],
+        "OpenROAD.CTS": ["RUN_CTS"],
+        "OpenROAD.RCX": ["RUN_SPEF_EXTRACTION"],
+        "OpenROAD.TapEndcapInsertion": ["RUN_TAP_ENDCAP_INSERTION"],
+        "Odb.HeuristicDiodeInsertion": ["RUN_HEURISTIC_DIODE_INSERTION"],
+        "OpenROAD.RepairAntennas": ["RUN_ANTENNA_REPAIR"],
+        "OpenROAD.DetailedRouting": ["RUN_DRT"],
+        "OpenROAD.FillInsertion": ["RUN_FILL_INSERTION"],
+        "OpenROAD.STAPostPNR": ["RUN_MCSTA"],
+        "OpenROAD.IRDropReport": ["RUN_IRDROP_REPORT"],
+        "Magic.StreamOut": ["RUN_MAGIC_STREAMOUT"],
+        "KLayout.StreamOut": ["RUN_KLAYOUT_STREAMOUT"],
+        "Magic.WriteLEF": ["RUN_MAGIC_WRITE_LEF"],
+        "Magic.DRC": ["RUN_MAGIC_DRC"],
+        "KLayout.DRC": ["RUN_KLAYOUT_DRC"],
+        "KLayout.XOR": [
+            "RUN_KLAYOUT_XOR",
+            "RUN_MAGIC_STREAMOUT",
+            "RUN_KLAYOUT_STREAMOUT",
+        ],
+        "Netgen.LVS": ["RUN_LVS"],
+        "Checker.TrDRC": ["RUN_DRT"],
+        "Checker.MagicDRC": ["RUN_MAGIC_DRC"],
+        "Checker.XOR": [
+            "RUN_KLAYOUT_XOR",
+            "RUN_MAGIC_STREAMOUT",
+            "RUN_KLAYOUT_STREAMOUT",
+        ],
+        "Checker.LVS": ["RUN_LVS"],
+        "Checker.KLayoutDRC": ["RUN_KLAYOUT_DRC"],
+        # Not in VHDLClassic
+        "Yosys.EQY": ["RUN_EQY"],
+        "Verilator.Lint": ["RUN_LINTER"],
+        "Checker.LintErrors": ["RUN_LINTER"],
+        "Checker.LintWarnings": ["RUN_LINTER"],
+        "Checker.LintTimingConstructs": [
+            "RUN_LINTER",
+        ],
+    }
+
+
+@Flow.factory.register()
+class VHDLClassic(Classic):
+    """
+    A variant of Classic that accepts VHDL files for Synthesis instead of
+    Verilog files (and removes Verilog linting/equivalence steps.)
+    """
+
+    Substitutions = {
+        "Verilator.Lint": None,
+        "Checker.Lint*": None,
+        "Yosys.JsonHeader": None,
+        "Yosys.Synthesis": Yosys.VHDLSynthesis,
+        "Odb.SetPowerConnections": None,
+        "Odb.WriteVerilogHeader": None,
+        "Yosys.EQY": None,
+    }