librelane 2.4.0.dev0__py3-none-any.whl

librelane/steps/yosys.py

@@ -0,0 +1,371 @@
+# Copyright 2023 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+import os
+import textwrap
+import subprocess
+from abc import abstractmethod
+from typing import List, Literal, Optional, Set, Tuple
+
+from .tclstep import TclStep
+from .step import ViewsUpdate, MetricsUpdate, Step
+from .pyosys import JsonHeader, verilog_rtl_cfg_vars, Synthesis, VHDLSynthesis
+
+from ..config import Variable, Config
+from ..state import State, DesignFormat
+from ..logging import info
+from ..common import Path, Toolbox, TclUtils, process_list_file
+
+# Re-export for back-compat
+JsonHeader
+Synthesis
+VHDLSynthesis
+
+
+# This is now only used by EQY since we moved our Yosys scripts to Python.
+def _generate_read_deps(
+    config: Config,
+    toolbox: Toolbox,
+    power_defines: bool = False,
+    tcl: bool = True,
+) -> str:
+    commands = ""
+
+    synth_defines = [
+        f"PDK_{config['PDK']}",
+        f"SCL_{config['STD_CELL_LIBRARY']}",
+        "__librelane__",
+        "__pnr__",
+    ]
+    synth_defines += (
+        config.get("VERILOG_DEFINES") or []
+    )  # VERILOG_DEFINES not defined for VHDLSynthesis
+    if tcl:
+        commands += "set ::_synlig_defines [list]\n"
+    for define in synth_defines:
+        commands += f"verilog_defines {TclUtils.escape(f'-D{define}')}\n"
+        if tcl:
+            commands += (
+                f"lappend ::_synlig_defines {TclUtils.escape(f'+define+{define}')}\n"
+            )
+
+    scl_lib_list = toolbox.filter_views(config, config["LIB"])
+
+    if power_defines:
+        if power_define := config.get(
+            "VERILOG_POWER_DEFINE"
+        ):  # VERILOG_POWER_DEFINE not defined for VHDLSynthesis
+            commands += f"verilog_defines {TclUtils.escape(f'-D{power_define}')}\n"
+            if tcl:
+                commands += f"lappend ::_synlig_defines {TclUtils.escape(f'+define+{power_define}')}\n"
+
+    # Try your best to use powered blackbox models if power_defines is true
+    if power_defines and config["CELL_VERILOG_MODELS"] is not None:
+        scl_blackbox_models = toolbox.create_blackbox_model(
+            frozenset(config["CELL_VERILOG_MODELS"]),
+            frozenset(["USE_POWER_PINS"]),
+        )
+        commands += f"read_verilog -sv -lib {scl_blackbox_models}\n"
+    else:
+        # Fall back to scl_lib_list if you cant
+        for lib in scl_lib_list:
+            lib_str = TclUtils.escape(str(lib))
+            commands += (
+                f"read_liberty -lib -ignore_miss_dir -setattr blackbox {lib_str}\n"
+            )
+
+    excluded_cells: Set[str] = set(config["EXTRA_EXCLUDED_CELLS"] or [])
+    excluded_cells.update(process_list_file(config["SYNTH_EXCLUDED_CELL_FILE"]))
+    excluded_cells.update(process_list_file(config["PNR_EXCLUDED_CELL_FILE"]))
+
+    lib_synth = toolbox.remove_cells_from_lib(
+        frozenset([str(lib) for lib in scl_lib_list]),
+        excluded_cells=frozenset(excluded_cells),
+    )
+    if tcl:
+        commands += (
+            f"set ::env(SYNTH_LIBS) {TclUtils.escape(TclUtils.join(lib_synth))}\n"
+        )
+
+    verilog_include_args = []
+    if dirs := config.get("VERILOG_INCLUDE_DIRS"):
+        for dir in dirs:
+            verilog_include_args.append(f"-I{dir}")
+
+    # Priorities from higher to lower
+    format_list = (
+        [
+            DesignFormat.VERILOG_HEADER,
+            DesignFormat.POWERED_NETLIST,
+            DesignFormat.NETLIST,
+            DesignFormat.LIB,
+        ]
+        if power_defines
+        else [
+            DesignFormat.VERILOG_HEADER,
+            DesignFormat.NETLIST,
+            DesignFormat.POWERED_NETLIST,
+            DesignFormat.LIB,
+        ]
+    )
+    for view, format in toolbox.get_macro_views_by_priority(config, format_list):
+        view_escaped = TclUtils.escape(str(view))
+        if format == DesignFormat.LIB:
+            commands += (
+                f"read_liberty -lib -ignore_miss_dir -setattr blackbox {view_escaped}\n"
+            )
+        else:
+            commands += f"read_verilog -sv -lib {TclUtils.join(verilog_include_args)} {view_escaped}\n"
+
+    if libs := config.get("EXTRA_LIBS"):
+        for lib in libs:
+            lib_str = TclUtils.escape(str(lib))
+            commands += (
+                f"read_liberty -lib -ignore_miss_dir -setattr blackbox {lib_str}\n"
+            )
+
+    if models := config["EXTRA_VERILOG_MODELS"]:
+        for model in models:
+            model_str = TclUtils.escape(str(model))
+            commands += f"read_verilog -sv -lib {TclUtils.join(verilog_include_args)} {model_str}\n"
+
+    return commands
+
+
+# No longer used by us, kept for back-compat
+class YosysStep(TclStep):
+    config_vars = [
+        Variable(
+            "SYNTH_LATCH_MAP",
+            Optional[Path],
+            "A path to a file containing the latch mapping for Yosys.",
+            pdk=True,
+        ),
+        Variable(
+            "SYNTH_TRISTATE_MAP",
+            Optional[Path],
+            "A path to a file containing the tri-state buffer mapping for Yosys.",
+            deprecated_names=["TRISTATE_BUFFER_MAP"],
+            pdk=True,
+        ),
+        Variable(
+            "SYNTH_CSA_MAP",
+            Optional[Path],
+            "A path to a file containing the carry-select adder mapping for Yosys.",
+            deprecated_names=["CARRY_SELECT_ADDER_MAP"],
+            pdk=True,
+        ),
+        Variable(
+            "SYNTH_RCA_MAP",
+            Optional[Path],
+            "A path to a file containing the ripple-carry adder mapping for Yosys.",
+            deprecated_names=["RIPPLE_CARRY_ADDER_MAP"],
+            pdk=True,
+        ),
+        Variable(
+            "SYNTH_FA_MAP",
+            Optional[Path],
+            "A path to a file containing the full adder mapping for Yosys.",
+            deprecated_names=["FULL_ADDER_MAP"],
+            pdk=True,
+        ),
+        Variable(
+            "SYNTH_MUX_MAP",
+            Optional[Path],
+            "A path to a file containing the mux mapping for Yosys.",
+            pdk=True,
+        ),
+        Variable(
+            "SYNTH_MUX4_MAP",
+            Optional[Path],
+            "A path to a file containing the mux4 mapping for Yosys.",
+            pdk=True,
+        ),
+        Variable(
+            "USE_LIGHTER",
+            bool,
+            "Activates Lighter, an experimental plugin that attempts to optimize clock-gated flip-flops.",
+            default=False,
+        ),
+        Variable(
+            "LIGHTER_DFF_MAP",
+            Optional[Path],
+            "An override to the custom DFF map file provided for the given SCL by Lighter.",
+        ),
+        Variable(
+            "YOSYS_LOG_LEVEL",
+            Literal["ALL", "WARNING", "ERROR"],
+            "Which log level for Yosys. At WARNING or higher, the initialization splash is also disabled.",
+            default="ALL",
+        ),
+    ]
+
+    def get_command(self) -> List[str]:
+        script_path = self.get_script_path()
+        cmd = ["yosys", "-c", script_path]
+        if self.config["YOSYS_LOG_LEVEL"] != "ALL":
+            cmd += ["-Q"]
+        if self.config["YOSYS_LOG_LEVEL"] == "WARNING":
+            cmd += ["-q"]
+        elif self.config["YOSYS_LOG_LEVEL"] == "ERROR":
+            cmd += ["-qq"]
+        return cmd
+
+    @abstractmethod
+    def get_script_path(self) -> str:
+        pass
+
+    def run(self, state_in: State, **kwargs) -> Tuple[ViewsUpdate, MetricsUpdate]:
+        power_defines = False
+        if "power_defines" in kwargs:
+            power_defines = kwargs.pop("power_defines")
+
+        kwargs, env = self.extract_env(kwargs)
+
+        _deps_script = os.path.join(self.step_dir, "_deps.tcl")
+
+        with open(_deps_script, "w") as f:
+            f.write(
+                _generate_read_deps(
+                    self.config, self.toolbox, power_defines=power_defines
+                )
+            )
+
+        env["_DEPS_SCRIPT"] = _deps_script
+
+        return super().run(state_in, env=env, **kwargs)
+
+
+@Step.factory.register()
+class EQY(Step):
+    id = "Yosys.EQY"
+    name = "Equivalence Check"
+    long_name = "RTL/Netlist Equivalence Check"
+
+    inputs = [DesignFormat.NETLIST]
+    outputs = []
+
+    config_vars = (
+        YosysStep.config_vars
+        + verilog_rtl_cfg_vars
+        + [
+            Variable(
+                "EQY_SCRIPT",
+                Optional[Path],
+                "An optional override for the automatically generated EQY script for more complex designs.",
+            ),
+            Variable(
+                "MACRO_PLACEMENT_CFG",
+                Optional[Path],
+                "This step will warn if this deprecated variable is used, as it indicates Macros are used without the new Macro object.",
+            ),
+            Variable(
+                "EQY_FORCE_ACCEPT_PDK",
+                bool,
+                "Attempt to run EQY even if the PDK's Verilog models are supported by this step. Will likely result in a failure.",
+                default=False,
+            ),
+        ]
+    )
+
+    def run(self, state_in: State, **kwargs) -> Tuple[ViewsUpdate, MetricsUpdate]:
+        processed_pdk = os.path.join(self.step_dir, "formal_pdk.v")
+
+        if self.config["PDK"].startswith("sky130A"):
+            subprocess.check_call(
+                [
+                    "eqy.formal_pdk_proc",
+                    "--output",
+                    processed_pdk,
+                ]
+                + [str(model) for model in self.config["CELL_VERILOG_MODELS"]]
+            )
+        elif self.config["EQY_FORCE_ACCEPT_PDK"]:
+            subprocess.check_call(
+                ["iverilog", "-E", "-o", processed_pdk, "-DFUNCTIONAL"]
+                + [str(model) for model in self.config["CELL_VERILOG_MODELS"]]
+            )
+        else:
+            info(
+                f"PDK {self.config['PDK']} is not supported by the EQY step. Skipping…"
+            )
+            return {}, {}
+
+        eqy_script_path = os.path.join(
+            self.step_dir, f"{self.config['DESIGN_NAME']}.eqy"
+        )
+
+        with open(eqy_script_path, "w", encoding="utf8") as f:
+            if eqy_script := self.config["EQY_SCRIPT"]:
+                for line in open(eqy_script, "r", encoding="utf8"):
+                    f.write(line)
+            else:
+                script = textwrap.dedent(
+                    """
+                    [script]
+                    {dep_commands}
+                    blackbox
+
+                    [gold]
+                    read_verilog -formal -sv {files}
+
+                    [gate]
+                    read_verilog -formal -sv {processed_pdk} {nl}
+
+                    [script]
+                    hierarchy -top {design_name}
+                    proc
+                    prep -top {design_name} -flatten
+
+                    memory -nomap
+                    async2sync
+
+                    [gold]
+                    write_verilog {step_dir}/gold.v
+                    
+                    [gate]
+                    write_verilog {step_dir}/gate.v
+
+                    [strategy sat]
+                    use sat
+                    depth 5
+
+                    [strategy pdr]
+                    use sby
+                    engine abc pdr -rfi
+
+                    [strategy bitwuzla]
+                    use sby
+                    depth 2
+                    engine smtbmc bitwuzla
+                    """
+                ).format(
+                    design_name=self.config["DESIGN_NAME"],
+                    dep_commands=_generate_read_deps(
+                        self.config, self.toolbox, tcl=False
+                    ),
+                    files=TclUtils.join(
+                        [str(file) for file in self.config["VERILOG_FILES"]]
+                    ),
+                    nl=state_in[DesignFormat.NETLIST],
+                    processed_pdk=processed_pdk,
+                    step_dir=self.step_dir,
+                )
+                f.write(script)
+        work_dir = os.path.join(self.step_dir, "scratch")
+
+        subprocess_result = self.run_subprocess(
+            ["eqy", "-f", eqy_script_path, "-d", work_dir]
+        )
+
+        return {}, subprocess_result["generated_metrics"]

librelane-2.4.0.dev0.dist-info/METADATA

@@ -0,0 +1,151 @@
+Metadata-Version: 2.3
+Name: librelane
+Version: 2.4.0.dev0
+Summary: An infrastructure for implementing chip design flows
+License: Apache-2.0
+Author: Mohamed Gaber
+Author-email: me@donn.website
+Requires-Python: >=3.8,<4
+Classifier: License :: OSI Approved :: Apache Software License
+Classifier: Programming Language :: Python :: 3
+Classifier: Programming Language :: Python :: 3.8
+Classifier: Programming Language :: Python :: 3.9
+Classifier: Programming Language :: Python :: 3.10
+Classifier: Programming Language :: Python :: 3.11
+Classifier: Programming Language :: Python :: 3.12
+Classifier: Programming Language :: Python :: 3.13
+Requires-Dist: ciel (>=0.16.0)
+Requires-Dist: click (>=8,<9)
+Requires-Dist: cloup (>=3.0.5,<4)
+Requires-Dist: deprecated (>=1.2.10,<2)
+Requires-Dist: httpx (>=0.22.0,<0.29)
+Requires-Dist: ioplace-parser (>=0.3.0,<0.5.0)
+Requires-Dist: klayout (>=0.29.0,<0.30.0)
+Requires-Dist: libparse (>=0.3.1,<1)
+Requires-Dist: lxml (>=4.9.0)
+Requires-Dist: psutil (>=5.9.0)
+Requires-Dist: pyyaml (>=5,<7)
+Requires-Dist: rapidfuzz (>=3.9.0,<4)
+Requires-Dist: rich (>=12,<14)
+Requires-Dist: semver (>=3.0.2,<4.0.0)
+Requires-Dist: yamlcore (>=0.0.2,<0.0.3)
+Project-URL: Documentation, https://librelane.readthedocs.io
+Project-URL: Repository, https://github.com/librelane/librelane
+Description-Content-Type: text/markdown
+
+<h1 align="center">LibreLane</h1>
+<p align="center">
+    <a href="https://opensource.org/licenses/Apache-2.0"><img src="https://img.shields.io/badge/License-Apache%202.0-blue.svg" alt="License: Apache 2.0"/></a>
+    <a href="https://www.python.org"><img src="https://img.shields.io/badge/Python-3.8-3776AB.svg?style=flat&logo=python&logoColor=white" alt="Python 3.8 or higher" /></a>
+    <a href="https://github.com/psf/black"><img src="https://img.shields.io/badge/code%20style-black-000000.svg" alt="Code Style: black"/></a>
+    <a href="https://mypy-lang.org/"><img src="https://www.mypy-lang.org/static/mypy_badge.svg" alt="Checked with mypy"/></a>
+    <a href="https://nixos.org/"><img src="https://img.shields.io/static/v1?logo=nixos&logoColor=white&label=&message=Built%20with%20Nix&color=41439a" alt="Built with Nix"/></a>
+</p>
+<p align="center">
+    <a href="https://colab.research.google.com/github/librelane/librelane/blob/main/notebook.ipynb"><img src="https://colab.research.google.com/assets/colab-badge.svg" alt="Open in Colab"></a>
+    <a href="https://librelane.readthedocs.io/"><img src="https://readthedocs.org/projects/librelane/badge/?version=latest" alt="Documentation Build Status Badge"/></a>
+    <a href="https://fossi-chat.org"><img src="https://img.shields.io/badge/Community-FOSSi%20Chat-1bb378?logo=element" alt="Invite to FOSSi Chat"/></a>
+</p>
+
+LibreLane is an ASIC infrastructure library based on several components including
+OpenROAD, Yosys, Magic, Netgen, CVC, KLayout and a number of custom scripts for
+design exploration and optimization, currently developed and maintained by the
+American University in Cairo Open Hardware Lab (AUCOHL.)
+
+A reference flow, "Classic", performs all ASIC implementation steps from RTL all
+the way down to GDSII.
+
+You can find the documentation
+[here](https://librelane.readthedocs.io/en/latest/getting_started/) to get
+started. You can discuss LibreLane in the
+[FOSSi Chat Matrix Server](https://fossi-chat.org).
+
+
+## Try it out
+
+You can try LibreLane right in your browser, free-of-charge, using Google
+Colaboratory by following
+[**this link**](https://colab.research.google.com/github/librelane/librelane/blob/main/notebook.ipynb).
+
+## Installation
+
+You'll need the following:
+
+* Python **3.8** or higher with PIP, Venv and Tkinter
+
+### Nix (Recommended)
+
+Works for macOS and Linux (x86-64 and aarch64). Recommended, as it is more
+integrated with your filesystem and overall has less upload and download deltas.
+
+See
+[Nix-based installation](https://librelane.readthedocs.io/en/latest/getting_started/common/nix_installation/index.html)
+in the docs for more info.
+
+### Docker
+
+Works for Windows, macOS and Linux (x86-64 and aarch64).
+
+See
+[Docker-based installation](https://librelane.readthedocs.io/en/latest/getting_started/common/docker_installation/index.html)
+in the docs for more info.
+
+Do note you'll need to add `--dockerized` right after `librelane` in most CLI
+invocations.
+
+### Python-only Installation (Advanced, Not Recommended)
+
+**You'll need to bring your own compiled utilities**, but otherwise, simply
+install LibreLane as follows:
+
+```sh
+python3 -m pip install --upgrade librelane
+```
+
+Python-only installations are presently unsupported and entirely at your own
+risk.
+
+## Usage
+
+In the root folder of the repository, you may invoke:
+
+```sh
+python3 -m librelane --pdk-root <path/to/pdk> </path/to/config.json>
+```
+
+To start with, you can try:
+
+```sh
+python3 -m librelane --pdk-root $HOME/.ciel ./designs/spm/config.json
+```
+
+## Publication
+
+If you use LibreLane in your research, please cite the following paper.
+
+* M. Shalan and T. Edwards, “Building OpenLANE: A 130nm OpenROAD-based
+  Tapeout-Proven Flow: Invited Paper,” *2020 IEEE/ACM International Conference
+  On Computer Aided Design (ICCAD)*, San Diego, CA, USA, 2020, pp. 1-6.
+  [Paper](https://ieeexplore.ieee.org/document/9256623)
+
+```bibtex
+@INPROCEEDINGS{9256623,
+  author={Shalan, Mohamed and Edwards, Tim},
+  booktitle={2020 IEEE/ACM International Conference On Computer Aided Design (ICCAD)}, 
+  title={Building OpenLANE: A 130nm OpenROAD-based Tapeout- Proven Flow : Invited Paper}, 
+  year={2020},
+  volume={},
+  number={},
+  pages={1-6},
+  doi={}}
+```
+
+## License and Legal Info
+
+LibreLane is a trademark of the FOSSi Foundation.
+
+[The Apache License, version 2.0](https://www.apache.org/licenses/LICENSE-2.0.txt).
+
+LibreLane is based on OpenLane 2.0 by Efabless Corporation
+(https://github.com/efabless/openlane2) under the same license. 
+