librelane 2.4.0.dev0__py3-none-any.whl

librelane/examples/spm/src/signoff.sdc

@@ -0,0 +1,68 @@
+# Compared to the implementation SDC, the signoff SDC relaxes
+# max capacitance and transition constraints. (Which are intentionally over-
+# constrained for implementation to yield better results.)
+
+set clock_port __VIRTUAL_CLK__
+if { [info exists ::env(CLOCK_PORT)] } {
+    set port_count [llength $::env(CLOCK_PORT)]
+
+    if { $port_count == "0" } {
+        puts stderr "\[WARNING] No CLOCK_PORT found. A dummy clock will be used."
+    } elseif { $port_count != "1" } {
+        puts stderr "\[WARNING] Multi-clock files are not currently supported by the base SDC file. Only the first clock will be constrained."
+    }
+
+    if { $port_count > "0" } {
+        set ::clock_port [lindex $::env(CLOCK_PORT) 0]
+    }
+}
+set port_args [get_ports $clock_port]
+puts "\[INFO] Using clock $clock_port…"
+create_clock {*}$port_args -name $clock_port -period $::env(CLOCK_PERIOD)
+
+set input_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_DELAY_CONSTRAINT) / 100]
+set output_delay_value [expr $::env(CLOCK_PERIOD) * $::env(IO_DELAY_CONSTRAINT) / 100]
+puts "\[INFO] Setting output delay to: $output_delay_value"
+puts "\[INFO] Setting input delay to: $input_delay_value"
+
+set_max_fanout $::env(MAX_FANOUT_CONSTRAINT) [current_design]
+
+set clk_input [get_port $clock_port]
+set clk_indx [lsearch [all_inputs] $clk_input]
+set all_inputs_wo_clk [lreplace [all_inputs] $clk_indx $clk_indx ""]
+
+#set rst_input [get_port resetn]
+#set rst_indx [lsearch [all_inputs] $rst_input]
+#set all_inputs_wo_clk_rst [lreplace $all_inputs_wo_clk $rst_indx $rst_indx ""]
+set all_inputs_wo_clk_rst $all_inputs_wo_clk
+
+# correct resetn
+set clocks [get_clocks $clock_port]
+
+set_input_delay $input_delay_value -clock $clocks $all_inputs_wo_clk_rst
+set_output_delay $output_delay_value -clock $clocks [all_outputs]
+
+if { ![info exists ::env(SYNTH_CLK_DRIVING_CELL)] } {
+    set ::env(SYNTH_CLK_DRIVING_CELL) $::env(SYNTH_DRIVING_CELL)
+}
+
+set_driving_cell \
+    -lib_cell [lindex [split $::env(SYNTH_DRIVING_CELL) "/"] 0] \
+    -pin [lindex [split $::env(SYNTH_DRIVING_CELL) "/"] 1] \
+    $all_inputs_wo_clk_rst
+
+set_driving_cell \
+    -lib_cell [lindex [split $::env(SYNTH_CLK_DRIVING_CELL) "/"] 0] \
+    -pin [lindex [split $::env(SYNTH_CLK_DRIVING_CELL) "/"] 1] \
+    $clk_input
+
+set cap_load [expr $::env(OUTPUT_CAP_LOAD) / 1000.0]
+puts "\[INFO] Setting load to: $cap_load"
+set_load $cap_load [all_outputs]
+
+puts "\[INFO] Setting clock uncertainty to: 0.1"
+set_clock_uncertainty 0.1 $clocks
+
+puts "\[INFO] Setting timing derate to: $::env(TIME_DERATING_CONSTRAINT)%"
+set_timing_derate -early [expr 1-[expr $::env(TIME_DERATING_CONSTRAINT) / 100]]
+set_timing_derate -late [expr 1+[expr $::env(TIME_DERATING_CONSTRAINT) / 100]]

librelane/examples/spm/src/spm.v

@@ -0,0 +1,73 @@
+// Copyright 2023 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// (Parameterized) Unsigned Serial/Parallel Multiplier:
+// - Multiplicand x (Input bit-serially)
+// - Multiplier a (All bits at the same time/Parallel)
+// - Product y (Output bit-serial)
+module spm #(parameter bits=32) (
+    input clk,
+    input rst,
+    input x,
+    input[bits-1: 0] a,
+    output y
+);
+    wire[bits: 0] y_chain;
+    assign y_chain[0] = 0;
+    assign y = y_chain[bits];
+
+    wire[bits-1:0] a_flip;
+    genvar i;
+    generate 
+        for (i = 0; i < bits; i = i + 1) begin : flip_block
+            assign a_flip[i] = a[bits - i - 1];
+        end 
+    endgenerate
+
+    delayed_serial_adder dsa[bits-1:0](
+        .clk(clk),
+        .rst(rst),
+        .x(x),
+        .a(a_flip),
+        .y_in(y_chain[bits-1:0]),
+        .y_out(y_chain[bits:1])
+    );
+
+endmodule
+
+module delayed_serial_adder(
+    input clk,
+    input rst,
+    input x,
+    input a,
+    input y_in,
+    output reg y_out
+);
+    reg last_carry;
+    wire last_carry_next;
+    wire y_out_next;
+
+    wire g = x & a;
+    assign {last_carry_next, y_out_next} = g + y_in + last_carry;
+
+    always @ (posedge clk or negedge rst) begin
+        if (!rst) begin
+            last_carry <= 1'b0;
+            y_out <= 1'b0;
+        end else begin
+            last_carry <= last_carry_next;
+            y_out <= y_out_next;
+        end
+    end
+endmodule

librelane/examples/spm/verify/spm_tb.v

@@ -0,0 +1,106 @@
+// Copyright 2023 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+module spm_tb;
+	localparam bits = 32;
+	reg clk;
+	reg rst;
+	reg load;
+	reg[bits-1:0] x;
+	reg[bits-1:0] a;
+
+	wire[bits-1:0] srx_value;
+	sreg #(bits) srx(
+		.clk(clk),
+		.rst(rst),
+		.direction(1'b1),
+		.serial_msb(1'b0),
+		.serial_lsb(1'b0),
+		.load(load),
+		.load_value(x),
+		.value(srx_value)
+	);
+
+	wire y;
+	wire [bits*2-1:0] y_value;
+	sreg #(bits * 2) sry(
+		.clk(clk),
+		.rst(rst),
+		.direction(1'b1),
+		.serial_msb(y),
+		.serial_lsb(1'b0),
+		.load(1'b0),
+		.load_value({(bits*2){1'b0}}),
+		.value(y_value)
+	);
+
+	spm dut(
+		.clk(clk),
+		.rst(rst),
+		.x(srx_value[0]),
+		.a(a),
+		.y(y)
+	);
+
+	always #1 clk = ~clk;
+
+	reg [bits*2-1:0] expected;
+
+	initial begin
+		$dumpvars(0, spm_tb);
+		for (integer i = 0; i < 20; i = i + 1) begin
+			clk = 0;
+			rst = 0;
+			load = 0;
+			x = $random;
+			a = $random;
+			expected = x * a;
+			#2;
+			load = 1;
+			rst = 1;
+			#2;
+			load = 0;
+			#2; // No useful bit at the first clock cycle
+			#(bits * 2 * 2); // 2 * bits * clock cycle duration
+			$display("%h * %h", x, a);
+			$display("expected %h, got %h (%s)", expected, y_value, expected==y_value ? "ok " : "err");
+		end
+		$finish;
+	end
+endmodule
+
+module sreg #(parameter width = 32) (
+    input clk,
+    input rst,
+    input direction, // 0 -> load from lsb side; 1 -> load from msb side
+    input serial_msb,
+    input serial_lsb,
+    input load,
+    input[width-1:0] load_value,
+    output[width-1:0] value
+);
+    reg[width-1:0] store;
+
+    assign value = store;
+
+    always @ (posedge clk or negedge rst) begin
+        if (!rst) begin
+            store <= {(width){1'b0}};
+        end else begin
+            store <= load ? load_value  :
+                            direction   ?   {serial_msb, store[width-1:1]}:
+                                            {store[width-2:0], serial_lsb};
+        end
+    end
+endmodule

librelane/examples/spm-user_project_wrapper/SPM_example.v

@@ -0,0 +1,286 @@
+// Copyright 2023 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+// (Parameterized) Unsigned Serial/Parallel Multiplier:
+// - Multiplicand x (Input bit-serially)
+// - Multiplier a (All bits at the same time/Parallel)
+// - Product y (Output bit-serial)
+
+`default_nettype none
+/*
+ *-------------------------------------------------------------
+ *
+ * user_proj_example
+ *
+ * This is an example of a (trivially simple) user project,
+ * showing how the user project can connect to the logic
+ * analyzer, the wishbone bus, and the I/O pads.
+ *
+ * This project generates an integer count, which is output
+ * on the user area GPIO pads (digital output only).  The
+ * wishbone connection allows the project to be controlled
+ * (start and stop) from the management SoC program.
+ *
+ * See the testbenches in directory "mprj_counter" for the
+ * example programs that drive this user project.  The three
+ * testbenches are "io_ports", "la_test1", and "la_test2".
+ *
+ *-------------------------------------------------------------
+ */
+
+module SPM_example #(
+    parameter BITS = 32
+)(
+`ifdef USE_POWER_PINS
+    inout vccd1,    // User area 1 1.8V supply
+    inout vssd1,    // User area 1 digital ground
+    // inout vdda2,
+    // inout vssd2,
+`endif
+
+    // Wishbone Slave ports (WB MI A)
+    input wb_clk_i,
+    input wb_rst_i,
+    input wbs_stb_i,
+    input wbs_cyc_i,
+    input wbs_we_i,
+    input [3:0] wbs_sel_i,
+    input [31:0] wbs_dat_i,
+    input [31:0] wbs_adr_i,
+    output reg wbs_ack_o,
+    output reg [31:0] wbs_dat_o,
+
+    // Logic Analyzer Signals
+    input  [127:0] la_data_in,
+    output [127:0] la_data_out,
+    input  [127:0] la_oenb,
+
+    // IOs
+    input  wire [`MPRJ_IO_PADS-1:0] io_in,
+    output wire [`MPRJ_IO_PADS-1:0] io_out,
+    output wire [`MPRJ_IO_PADS-1:0] io_oeb,
+
+    // IRQ
+    output [2:0] irq
+);
+    wire clk;
+    wire rst;
+    
+
+    wire [31:0] rdata; 
+    wire [31:0] wdata;
+    wire [BITS-1:0] count;
+
+    wire valid;
+    wire [3:0] wstrb;
+    wire [31:0] la_write;
+
+    //addresses for registers
+    localparam X_OFF = 805306368, Y_OFF = 805306372, Y0_OFF = 805306376, Y1_OFF = 805306380, STAT_OFF = 32'h30000010;
+    //states of the state machine
+    localparam S0 = 0, S1 = 1, S2 = 2, S3 = 3;
+    reg [3:0] STATE, nstate;
+    reg [7:0] CNT, ncnt;
+    //Registers for the multiplicand, multiplier, product
+    reg [31:0] A, X;
+    reg [63:0] Y0;
+    wire status; // status register
+    assign status = STATE == S0 ? 1:0; // if status reg == 1 means data is ready to be read or change the existing data
+    //wire for the current product bit
+    wire y;   
+    //Registers for the WB bus
+    reg [7:0] WB_address;
+    reg WB_Read, WB_Write;
+
+    // WB MI A
+    assign valid = wbs_cyc_i && wbs_stb_i; 
+    assign wstrb = wbs_sel_i & {4{wbs_we_i}};
+    //assign wbs_dat_o = rdata;
+    assign wdata = wbs_dat_i;
+
+    // IO
+    assign io_out = {(`MPRJ_IO_PADS){1'b0}};
+    assign io_oeb = {(`MPRJ_IO_PADS){rst}};
+
+    // IRQ
+    assign irq = 3'b000;    // Unused
+
+    // LA
+    assign la_data_out = {(127){1'b0}};
+    // Assuming LA probes [63:32] are for controlling the count register  
+    assign la_write = ~la_oenb[63:32] & ~{BITS{valid}};
+    // Assuming LA probes [65:64] are for controlling the count clk & reset  
+    // assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
+    // assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;    
+    assign clk = wb_clk_i;
+    assign rst = wb_rst_i;
+
+    always @(posedge clk or posedge rst) begin //assuming that we have posedge rst
+        
+        if(rst) begin
+          A <= 32'b0;
+          //wbs_ack_o <= 1'b0;
+        end
+        else if(valid && wbs_we_i && (wbs_adr_i==X_OFF)) begin
+          A <= wbs_dat_i;
+        //   wbs_dat_o <= A;
+        //   wbs_ack_o <= 1'b1;
+        end
+    end
+    
+    always @(posedge clk or posedge rst) begin //assuming that we have posedge rst
+        // wbs_ack_o <= 1'b0;
+        if(rst) begin
+            //wbs_ack_o <= 1'b0;  
+            X <= 32'b0;
+        end
+        else if(STATE==S1) X <= X >>1; //shift right for the X since we always take the least significant bit in the multiplication
+        else if(valid && wbs_we_i && (wbs_adr_i==Y_OFF)) begin //the reason we have a separate always block for the X is the shift right action
+          X <= wbs_dat_i;
+        //   wbs_dat_o <= X;
+        //   wbs_ack_o <= 1'b1;
+        end
+        
+    end
+
+    always@(posedge clk) begin //a signal such as wbs_dat_o can be manipulated within one always block only
+        if(valid && wbs_we_i && (wbs_adr_i==Y_OFF)) begin
+            wbs_dat_o <= X;
+        end
+        else if(valid && wbs_we_i && (wbs_adr_i==X_OFF)) begin
+            wbs_dat_o <= A;
+        end
+        else if(valid && !wbs_we_i && (wbs_adr_i==Y0_OFF)) begin
+            wbs_dat_o <= Y0[31:0];
+            // wbs_ack_o <= 1'b1;
+        end 
+        else if(valid && !wbs_we_i && (wbs_adr_i==Y1_OFF)) begin
+          wbs_dat_o <= Y0[63:32];
+        end
+        else if(valid && !wbs_we_i && (wbs_adr_i==STAT_OFF)) begin
+          wbs_dat_o <= status;
+        end
+    end
+
+    always@(posedge clk) begin
+        if(wbs_ack_o) begin
+          wbs_ack_o <= 1'b0;
+        end
+        else if((valid && !wbs_we_i && (wbs_adr_i==Y1_OFF)) || (valid && !wbs_we_i && (wbs_adr_i==Y0_OFF)) || (valid && wbs_we_i && (wbs_adr_i==Y_OFF)) || (valid && wbs_we_i && (wbs_adr_i==X_OFF)) || (valid && !wbs_we_i && (wbs_adr_i==STAT_OFF))) begin
+            wbs_ack_o <= 1'b1;
+        end
+    end
+
+    always @(posedge clk or posedge rst) begin
+        if(rst) begin
+           Y0 <= 64'b0;
+        end
+        else if(STATE==S1) 
+            Y0 <= {y, Y0[63:1]}; //taking the result from the SPM and shifting it right one bit at a time
+
+    end
+
+    always @(posedge clk or posedge rst) begin
+        if(rst) begin
+          STATE <= S0;
+        end
+        else 
+            STATE <=nstate; //moving to the next state each clk cycle or on rst
+    end
+
+    always @(*) begin
+        case(STATE) 
+            S0: if(valid && wbs_we_i && (wbs_adr_i==Y_OFF)) nstate=S1; else nstate=S0;
+            S1: if(CNT==64) nstate=S0; else nstate=S1;  //state 1 means that both numbers are ready now.
+            default: nstate=S0; 
+        endcase
+    end
+
+    always @(posedge clk or posedge rst) begin
+        if(rst) begin
+          CNT <= 8'b0;
+        end
+        else 
+            CNT <= ncnt;
+    end
+
+    always @(*) begin
+        ncnt = 0;
+        if(CNT==64) ncnt <=0;
+        else if(STATE==S1) ncnt = CNT + 1;
+    end
+    spm spm(.clk(clk), .rst(!rst), .a(A), .x(X[0]), .y(y));
+    
+
+endmodule
+
+// (Parameterized) Unsigned Serial/Parallel Multiplier:
+// - Multiplicand x (Input bit-serially)
+// - Multiplier a (All bits at the same time/Parallel)
+// - Product y (Output bit-serial)
+module spm #(parameter bits=32) (
+    input clk,
+    input rst,
+    input x,
+    input[bits-1: 0] a,
+    output y
+);
+    wire[bits: 0] y_chain;
+    assign y_chain[0] = 0;
+    assign y = y_chain[bits];
+
+    wire[bits-1:0] a_flip;
+    genvar i;
+    generate 
+        for (i = 0; i < bits; i = i + 1) begin : flip_block
+            assign a_flip[i] = a[bits - i - 1];
+        end 
+    endgenerate
+
+    delayed_serial_adder dsa[bits-1:0](
+        .clk(clk),
+        .rst(rst),
+        .x(x),
+        .a(a_flip),
+        .y_in(y_chain[bits-1:0]),
+        .y_out(y_chain[bits:1])
+    );
+
+endmodule
+
+module delayed_serial_adder(
+    input clk,
+    input rst,
+    input x,
+    input a,
+    input y_in,
+    output reg y_out
+);
+    reg last_carry;
+    wire last_carry_next;
+    wire y_out_next;
+
+    wire g = x & a;
+    assign {last_carry_next, y_out_next} = g + y_in + last_carry;
+
+    always @ (posedge clk or negedge rst) begin
+        if (!rst) begin
+            last_carry <= 1'b0;
+            y_out <= 1'b0;
+        end else begin
+            last_carry <= last_carry_next;
+            y_out <= y_out_next;
+        end
+    end
+endmodule

librelane/examples/spm-user_project_wrapper/base_sdc_file.sdc

@@ -0,0 +1,145 @@
+# generated by get_cup_sdc.py
+# Date: 2023/06/20
+
+### Note:
+# - input clock transition and latency are set for wb_clk_i port.
+#   If your design is using the user_clock2, update the clock constraints to reflect that and use usr_* variables.
+# - IO ports are assumed to be asynchronous. If they're synchronous to the clock, update the variable IO_SYNC to 1.
+#   As well, update in_ext_delay and out_ext_delay with the required I/O external delays.
+
+#------------------------------------------#
+# Pre-defined Constraints
+#------------------------------------------#
+
+# Clock network
+set ::env(IO_SYNC) 0
+if {[info exists ::env(CLOCK_PORT)] && $::env(CLOCK_PORT) != ""} {
+	set clk_input $::env(CLOCK_PORT)
+	create_clock [get_ports $clk_input] -name clk -period $::env(CLOCK_PERIOD)
+	puts "\[INFO\]: Creating clock {clk} for port $clk_input with period: $::env(CLOCK_PERIOD)"
+} else {
+	set clk_input __VIRTUAL_CLK__
+	create_clock -name clk -period $::env(CLOCK_PERIOD)
+	puts "\[INFO\]: Creating virtual clock with period: $::env(CLOCK_PERIOD)"
+}
+if { ![info exists ::env(SYNTH_CLK_DRIVING_CELL)] } {
+	set ::env(SYNTH_CLK_DRIVING_CELL) $::env(SYNTH_DRIVING_CELL)
+}
+if { ![info exists ::env(SYNTH_CLK_DRIVING_CELL_PIN)] } {
+	set ::env(SYNTH_CLK_DRIVING_CELL_PIN) $::env(SYNTH_DRIVING_CELL_PIN)
+}
+
+# Clock non-idealities
+set_propagated_clock [all_clocks]
+set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINTY) [get_clocks {clk}]
+puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINTY)"
+set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {clk}]
+puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
+
+# Maximum transition time for the design nets
+set_max_transition $::env(MAX_TRANSITION_CONSTRAINT) [current_design]
+puts "\[INFO\]: Setting maximum transition to: $::env(MAX_TRANSITION_CONSTRAINT)"
+
+# Maximum fanout
+set_max_fanout $::env(MAX_FANOUT_CONSTRAINT) [current_design]
+puts "\[INFO\]: Setting maximum fanout to: $::env(MAX_FANOUT_CONSTRAINT)"
+
+# Timing paths delays derate
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 100}] %"
+
+# Reset input delay
+set_input_delay [expr $::env(CLOCK_PERIOD) * 0.5] -clock [get_clocks {clk}] [get_ports {wb_rst_i}]
+
+# Multicycle paths
+set_multicycle_path -setup 2 -through [get_ports {wbs_ack_o}]
+set_multicycle_path -hold 1  -through [get_ports {wbs_ack_o}]
+set_multicycle_path -setup 2 -through [get_ports {wbs_cyc_i}]
+set_multicycle_path -hold 1  -through [get_ports {wbs_cyc_i}]
+set_multicycle_path -setup 2 -through [get_ports {wbs_stb_i}]
+set_multicycle_path -hold 1  -through [get_ports {wbs_stb_i}]
+
+#------------------------------------------#
+# Retrieved Constraints
+#------------------------------------------#
+
+# Clock source latency
+set usr_clk_max_latency 4.57
+set usr_clk_min_latency 4.11
+set clk_max_latency 5.57
+set clk_min_latency 4.65
+set_clock_latency -source -max $clk_max_latency [get_clocks {clk}]
+set_clock_latency -source -min $clk_min_latency [get_clocks {clk}]
+puts "\[INFO\]: Setting clock latency range: $clk_min_latency : $clk_max_latency"
+
+# Clock input Transition
+set usr_clk_tran 0.13
+set clk_tran 0.61
+set_input_transition $clk_tran [get_ports $clk_input]
+puts "\[INFO\]: Setting clock transition: $clk_tran"
+
+# Input delays
+set_input_delay -max 1.87 -clock [get_clocks {clk}] [get_ports {la_data_in[*]}]
+set_input_delay -max 1.89 -clock [get_clocks {clk}] [get_ports {la_oenb[*]}]
+set_input_delay -max 3.17 -clock [get_clocks {clk}] [get_ports {wbs_sel_i[*]}]
+set_input_delay -max 3.74 -clock [get_clocks {clk}] [get_ports {wbs_we_i}]
+set_input_delay -max 3.89 -clock [get_clocks {clk}] [get_ports {wbs_adr_i[*]}]
+set_input_delay -max 4.13 -clock [get_clocks {clk}] [get_ports {wbs_stb_i}]
+set_input_delay -max 4.61 -clock [get_clocks {clk}] [get_ports {wbs_dat_i[*]}]
+set_input_delay -max 4.74 -clock [get_clocks {clk}] [get_ports {wbs_cyc_i}]
+set_input_delay -min 0.18 -clock [get_clocks {clk}] [get_ports {la_data_in[*]}]
+set_input_delay -min 0.3  -clock [get_clocks {clk}] [get_ports {la_oenb[*]}]
+set_input_delay -min 0.79 -clock [get_clocks {clk}] [get_ports {wbs_adr_i[*]}]
+set_input_delay -min 1.04 -clock [get_clocks {clk}] [get_ports {wbs_dat_i[*]}]
+set_input_delay -min 1.19 -clock [get_clocks {clk}] [get_ports {wbs_sel_i[*]}]
+set_input_delay -min 1.65 -clock [get_clocks {clk}] [get_ports {wbs_we_i}]
+set_input_delay -min 1.69 -clock [get_clocks {clk}] [get_ports {wbs_cyc_i}]
+set_input_delay -min 1.86 -clock [get_clocks {clk}] [get_ports {wbs_stb_i}]
+if { $::env(IO_SYNC) } {
+	set in_ext_delay 4
+	puts "\[INFO\]: Setting input ports external delay to: $in_ext_delay"
+	set_input_delay -max [expr $in_ext_delay + 4.55] -clock [get_clocks {clk}] [get_ports {io_in[*]}]
+	set_input_delay -min [expr $in_ext_delay + 1.26] -clock [get_clocks {clk}] [get_ports {io_in[*]}]
+}
+
+# Input Transition
+set_input_transition -max 0.14  [get_ports {wbs_we_i}]
+set_input_transition -max 0.15  [get_ports {wbs_stb_i}]
+set_input_transition -max 0.17  [get_ports {wbs_cyc_i}]
+set_input_transition -max 0.18  [get_ports {wbs_sel_i[*]}]
+set_input_transition -max 0.38  [get_ports {io_in[*]}]
+set_input_transition -max 0.84  [get_ports {wbs_dat_i[*]}]
+set_input_transition -max 0.86  [get_ports {la_data_in[*]}]
+set_input_transition -max 0.92  [get_ports {wbs_adr_i[*]}]
+set_input_transition -max 0.97  [get_ports {la_oenb[*]}]
+set_input_transition -min 0.05  [get_ports {io_in[*]}]
+set_input_transition -min 0.06  [get_ports {la_oenb[*]}]
+set_input_transition -min 0.07  [get_ports {la_data_in[*]}]
+set_input_transition -min 0.07  [get_ports {wbs_adr_i[*]}]
+set_input_transition -min 0.07  [get_ports {wbs_dat_i[*]}]
+set_input_transition -min 0.09  [get_ports {wbs_cyc_i}]
+set_input_transition -min 0.09  [get_ports {wbs_sel_i[*]}]
+set_input_transition -min 0.09  [get_ports {wbs_we_i}]
+set_input_transition -min 0.15  [get_ports {wbs_stb_i}]
+
+# Output delays
+set_output_delay -max 0.7  -clock [get_clocks {clk}] [get_ports {user_irq[*]}]
+set_output_delay -max 1.0  -clock [get_clocks {clk}] [get_ports {la_data_out[*]}]
+set_output_delay -max 3.62 -clock [get_clocks {clk}] [get_ports {wbs_dat_o[*]}]
+set_output_delay -max 8.41 -clock [get_clocks {clk}] [get_ports {wbs_ack_o}]
+set_output_delay -min 0    -clock [get_clocks {clk}] [get_ports {la_data_out[*]}]
+set_output_delay -min 0    -clock [get_clocks {clk}] [get_ports {user_irq[*]}]
+set_output_delay -min 1.13 -clock [get_clocks {clk}] [get_ports {wbs_dat_o[*]}]
+set_output_delay -min 1.37 -clock [get_clocks {clk}] [get_ports {wbs_ack_o}]
+if { $::env(IO_SYNC) } {
+	set out_ext_delay 4
+	puts "\[INFO\]: Setting output ports external delay to: $out_ext_delay"
+	set_output_delay -max [expr $out_ext_delay + 9.12] -clock [get_clocks {clk}] [get_ports {io_out[*]}]
+	set_output_delay -max [expr $out_ext_delay + 9.32] -clock [get_clocks {clk}] [get_ports {io_oeb[*]}]
+	set_output_delay -min [expr $out_ext_delay + 2.34] -clock [get_clocks {clk}] [get_ports {io_oeb[*]}]
+	set_output_delay -min [expr $out_ext_delay + 3.9]  -clock [get_clocks {clk}] [get_ports {io_out[*]}]
+}
+
+# Output loads
+set_load 0.19 [all_outputs]

librelane/examples/spm-user_project_wrapper/config-tut.json

@@ -0,0 +1,12 @@
+{
+    "DESIGN_NAME": "user_project_wrapper",
+    "VERILOG_FILES": [
+        "dir::./defines.v",
+        "dir::./SPM_example.v",
+        "dir::./user_project_wrapper.v"
+    ],
+    "CLOCK_PERIOD": 25,
+    "CLOCK_PORT": "wb_clk_i",
+    "FP_CORE_UTIL": 5
+}
+