digsim-logic-simulator 0.3.0__py3-none-any.whl → 0.5.0__py3-none-any.whl

digsim/storage_model/_app.py

@@ -0,0 +1,53 @@
+# Copyright (c) Fredrik Andersson, 2023-2024
+# All rights reserved
+
+"""
+Module that handles the dataclasses for application
+"""
+
+from __future__ import annotations
+
+import json
+from dataclasses import asdict
+from typing import Any
+
+from pydantic import Field
+from pydantic.dataclasses import dataclass
+
+from ._circuit import CircuitDataClass
+
+
+@dataclass
+class GuiPositionDataClass:
+    x: int = 100
+    y: int = 100
+    z: int = 0
+
+
+@dataclass
+class AppFileDataClass:
+    circuit: CircuitDataClass
+    gui: dict[str, GuiPositionDataClass] = Field(default_factory=dict)
+    shortcuts: dict[str, str] = Field(default_factory=dict)
+    settings: dict[str, Any] = Field(default_factory=dict)
+
+    @staticmethod
+    def load(filename):
+        with open(filename, mode="r", encoding="utf-8") as json_file:
+            app_filedata_class = AppFileDataClass(**json.load(json_file))
+        return app_filedata_class
+
+    def save(self, filename):
+        json_object = json.dumps(asdict(self), indent=4)
+        with open(filename, mode="w", encoding="utf-8") as json_file:
+            json_file.write(json_object)
+
+
+@dataclass
+class ModelDataClass:
+    circuit: CircuitDataClass
+    gui: dict[str, GuiPositionDataClass]
+
+    @staticmethod
+    def from_app_file_dc(app_file_dc):
+        return ModelDataClass(circuit=app_file_dc.circuit, gui=app_file_dc.gui)

digsim/storage_model/_circuit.py

@@ -0,0 +1,118 @@
+# Copyright (c) Fredrik Andersson, 2023-2024
+# All rights reserved
+
+"""
+Module that handles the dataclasses for circuit load/save
+"""
+
+from __future__ import annotations
+
+import importlib
+import json
+from dataclasses import asdict
+
+from pydantic import Field
+from pydantic.dataclasses import dataclass
+
+
+@dataclass
+class WireDataClass:
+    src: str
+    dst: str
+
+    def connect(self, circuit):
+        src_comp = circuit.get_component(self.src.split(".")[0])
+        dst_comp = circuit.get_component(self.dst.split(".")[0])
+        src_comp.port(self.src.split(".")[1]).wire = dst_comp.port(self.dst.split(".")[1])
+
+    @classmethod
+    def list_from_port(cls, src_port):
+        wires = []
+        for port in src_port.wired_ports:
+            # Only add port on top-level components
+            if port.parent().is_toplevel():
+                wires.append(
+                    WireDataClass(
+                        src=f"{src_port.parent().name()}.{src_port.name()}",
+                        dst=f"{port.parent().name()}.{port.name()}",
+                    )
+                )
+        return wires
+
+
+@dataclass
+class ComponentDataClass:
+    """Component data class"""
+
+    name: str
+    type: str
+    display_name: str = Field(default="")
+    settings: dict = Field(default_factory=dict)
+
+    def create(self, circuit):
+        """Factory: Create a component from a dict"""
+        if "path" in self.settings:
+            self.settings["path"] = circuit.load_path(self.settings["path"])
+
+        py_module_name = ".".join(self.type.split(".")[0:-1])
+        py_class_name = self.type.split(".")[-1]
+
+        module = importlib.import_module(py_module_name)
+        class_ = getattr(module, py_class_name)
+        component = class_(circuit=circuit, **self.settings)
+        component.set_name(self.name)
+        if self.display_name is not None:
+            component.set_display_name(self.display_name)
+        return component
+
+    @staticmethod
+    def from_component(component):
+        """Return the component information as a dict, used when storing a circuit"""
+        module_split = type(component).__module__.split(".")
+        type_str = ""
+        for module in module_split:
+            if not module.startswith("_"):
+                type_str += f"{module}."
+        type_str += type(component).__name__
+
+        return ComponentDataClass(
+            name=component.name(),
+            display_name=component.display_name(),
+            type=type_str,
+            settings=component.settings_to_dict(),
+        )
+
+
+@dataclass
+class CircuitDataClass:
+    name: str = "unnamed"
+    components: list[ComponentDataClass] = Field(default_factory=list)
+    wires: list[WireDataClass] = Field(default_factory=list)
+
+    @staticmethod
+    def from_circuit(circuit):
+        dc = CircuitDataClass(name=circuit.name)
+        for comp in circuit.get_toplevel_components():
+            dc.components.append(ComponentDataClass.from_component(comp))
+
+        for comp in circuit.get_toplevel_components():
+            for port in comp.ports:
+                dc.wires.extend(WireDataClass.list_from_port(port))
+
+        return dc
+
+
+@dataclass
+class CircuitFileDataClass:
+    circuit: CircuitDataClass
+
+    @staticmethod
+    def load(filename):
+        with open(filename, mode="r", encoding="utf-8") as json_file:
+            dc = CircuitFileDataClass(**json.load(json_file))
+        return dc
+
+    def save(self, filename):
+        json_object = json.dumps(asdict(self), indent=4)
+        with open(filename, mode="w", encoding="utf-8") as json_file:
+            json_file.write(json_object)

digsim/synth/__init__.py

@@ -1,6 +1,6 @@
 # Copyright (c) Fredrik Andersson, 2023
 # All rights reserved
 
-""" All classes within digsim.synth namespace """
+"""All classes within digsim.synth namespace"""
 
 from ._synthesis import Synthesis, SynthesisException  # noqa: F401

digsim/synth/__main__.py

@@ -1,7 +1,7 @@
 # Copyright (c) Fredrik Andersson, 2023
 # All rights reserved
 
-""" The main class module of the digsim.synth namespace """
+"""The main class module of the digsim.synth namespace"""
 
 import argparse
 import sys

digsim/synth/_synthesis.py

@@ -9,6 +9,7 @@ import sys
 
 import pexpect
 import pexpect.popen_spawn
+
 from digsim.circuit.components.atoms import DigsimException
 
 
@@ -33,11 +34,18 @@ class Synthesis:
                     errorline = line
                     break
             raise SynthesisException(errorline)
-        return before_lines
+
+        # Remove escape sequence in output
+        out_lines = []
+        for line in before_lines:
+            if line.startswith("\x1b"):
+                continue
+            out_lines.append(line)
+        return out_lines
 
     @classmethod
     def _pexpect_spawn_yosys(cls):
-        yosys_exe = shutil.which("yowasp-yosys")
+        yosys_exe = shutil.which("yosys") or shutil.which("yowasp-yosys")
 
         if yosys_exe is None:
             raise SynthesisException("Yosys executable not found")

digsim/utils/__init__.py

@@ -1,6 +1,6 @@
 # Copyright (c) Fredrik Andersson, 2023
 # All rights reserved
 
-""" All classes within digsim.utils namespace """
+"""All classes within digsim.utils namespace"""
 
 from ._yosys_netlist import YosysNetlist  # noqa: F401

{digsim_logic_simulator-0.3.0.dist-info → digsim_logic_simulator-0.5.0.dist-info}/METADATA

@@ -1,6 +1,6 @@
 Metadata-Version: 2.1
 Name: digsim-logic-simulator
-Version: 0.3.0
+Version: 0.5.0
 Summary: Interactive Digital Logic Simulator
 Author-email: Fredrik Andersson <freand@gmail.com>
 Maintainer-email: Fredrik Andersson <freand@gmail.com>
@@ -41,20 +41,20 @@ Project-URL: homepage, https://github.com/freand76/digsim
 Keywords: educational,simulation,digital
 Classifier: Development Status :: 5 - Production/Stable
 Classifier: Programming Language :: Python :: 3
-Classifier: Programming Language :: Python :: 3.8
 Classifier: Programming Language :: Python :: 3.9
 Classifier: Programming Language :: Python :: 3.10
 Classifier: Programming Language :: Python :: 3.11
 Classifier: Programming Language :: Python :: 3.12
 Classifier: Programming Language :: Python :: 3 :: Only
-Requires-Python: >=3.8
+Requires-Python: >=3.9
 Description-Content-Type: text/markdown
 License-File: LICENSE.md
-Requires-Dist: pyvcd >=0.3.0
-Requires-Dist: pyside6 >=6.6.0
-Requires-Dist: pexpect ==4.8.0
+Requires-Dist: pyvcd >=0.4.0
+Requires-Dist: pyside6 >=6.7.3
+Requires-Dist: pexpect ==4.9.0
+Requires-Dist: pydantic ==2.9.2
 Requires-Dist: qtawesome
-Requires-Dist: yowasp-yosys ==0.36.0.8.post620
+Requires-Dist: yowasp-yosys ==0.45.0.0.post775
 
 # DigSim - Interactive Digital Logic Simulator
 
@@ -135,6 +135,11 @@ Then the following package must be installed:
 > gtkwave sr.vcd
 ```
 
+### Examples of writing pytest/python test benches for synthesized verilog code
+```
+> pytest examples/pytest_tb
+```
+
 ## Yosys synthesis helper tool
 
 ```

digsim_logic_simulator-0.5.0.dist-info/RECORD

@@ -0,0 +1,105 @@
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{digsim_logic_simulator-0.3.0.dist-info → digsim_logic_simulator-0.5.0.dist-info}/WHEEL

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 Root-Is-Purelib: true
 Tag: py3-none-any
 

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