digsim-logic-simulator 0.3.0__py3-none-any.whl → 0.5.0__py3-none-any.whl

digsim/app/settings/_gui_settings.py

@@ -1,10 +1,8 @@
-# Copyright (c) Fredrik Andersson, 2023
+# Copyright (c) Fredrik Andersson, 2023-2024
 # All rights reserved
 
 """The GUI settings dialog"""
 
-# pylint: disable=too-few-public-methods
-
 from PySide6.QtCore import Qt
 from PySide6.QtWidgets import QCheckBox, QComboBox, QDialog, QDialogButtonBox, QGridLayout, QLabel
 

digsim/app/settings/_shortcut_dialog.py

@@ -1,10 +1,8 @@
-# Copyright (c) Fredrik Andersson, 2023
+# Copyright (c) Fredrik Andersson, 2023-2024
 # All rights reserved
 
 """The shurtcut dialog"""
 
-# pylint: disable=too-few-public-methods
-
 from PySide6.QtCore import Qt
 from PySide6.QtWidgets import QComboBox, QDialog, QDialogButtonBox, QLabel, QVBoxLayout
 

digsim/circuit/__init__.py

@@ -1,7 +1,7 @@
 # Copyright (c) Fredrik Andersson, 2023
 # All rights reserved
 
-""" All classes within digsim.circuit namespace """
+"""All classes within digsim.circuit namespace"""
 
 from ._circuit import Circuit  # noqa: F401
 from .components import PortConnectionError  # noqa: F401

digsim/circuit/_circuit.py

@@ -1,18 +1,16 @@
-# Copyright (c) Fredrik Andersson, 2023
+# Copyright (c) Fredrik Andersson, 2023-2024
 # All rights reserved
 
 """
 Module that handles the circuit simulation of components
 """
 
-# pylint: disable=too-many-public-methods
-# pylint: disable=too-many-arguments
-
-import json
 import os
 
+from digsim.storage_model import CircuitDataClass, CircuitFileDataClass
+
 from ._waves_writer import WavesWriter
-from .components.atoms import Component, DigsimException
+from .components.atoms import DigsimException
 
 
 class CircuitError(DigsimException):
@@ -73,6 +71,11 @@ class Circuit:
         else:
             self._vcd = None
 
+    @property
+    def name(self):
+        """Get the circuit name"""
+        return self._name
+
     @property
     def time_ns(self):
         """Get the current simulation time (ns)"""
@@ -246,65 +249,24 @@ class Circuit:
             return comp
         raise CircuitError(f"Component '{component_name}' not found")
 
-    def _connect_from_dict(self, source, dest):
-        source_component_name = source.split(".")[0]
-        source_port_name = source.split(".")[1]
-        dest_component_name = dest.split(".")[0]
-        dest_port_name = dest.split(".")[1]
-
-        source_component = self.get_component(source_component_name)
-        dest_componment = self.get_component(dest_component_name)
-        source_component.port(source_port_name).wire = dest_componment.port(dest_port_name)
-
-    def to_dict(self, folder=None):
+    def to_dataclass(self, folder=None):
         """Generate dict from circuit, used when storing circuit"""
         if self._name is None:
             raise CircuitError("Circuit must have a name")
-
         self._folder = folder
-        components_list = []
-        for comp in self.get_toplevel_components():
-            components_list.append(comp.to_dict())
+        return CircuitDataClass.from_circuit(self)
 
-        connection_list = []
-        for comp in self.get_toplevel_components():
-            for port in comp.ports:
-                port_conn_list = port.to_dict_list()
-                connection_list.extend(port_conn_list)
-
-        circuit_dict = {
-            "circuit": {
-                "name": self._name,
-                "components": components_list,
-                "wires": connection_list,
-            }
-        }
-
-        return circuit_dict
-
-    def from_dict(
-        self, circuit_dict, folder=None, component_exceptions=True, connect_exceptions=True
+    def from_dataclass(
+        self, circuit_dc, folder=None, component_exceptions=True, connect_exceptions=True
     ):
         """Clear circuit and add components from dict"""
         self._folder = folder
         self.clear()
-        if "circuit" not in circuit_dict:
-            raise CircuitError("No 'circuit' in JSON")
-        json_circuit = circuit_dict["circuit"]
-        if "name" not in json_circuit:
-            raise CircuitError("No 'circuit/name' in JSON")
-        self._name = json_circuit["name"]
-        if "components" not in json_circuit:
-            raise CircuitError("No 'circuit/components' in JSON")
-        json_components = json_circuit["components"]
-        if "wires" not in json_circuit:
-            raise CircuitError("No 'circuit/connections' in JSON")
-        json_connections = json_circuit["wires"]
 
         exception_str_list = []
-        for json_component in json_components:
+        for component in circuit_dc.components:
             try:
-                Component.from_dict(self, json_component)
+                component.create(self)
             except DigsimException as exc:
                 if component_exceptions:
                     raise exc
@@ -313,9 +275,9 @@ class Circuit:
                 if component_exceptions:
                     raise exc
                 exception_str_list.append(f"{str(exc.__class__.__name__)}:{str(exc)}")
-        for json_connection in json_connections:
+        for wire in circuit_dc.wires:
             try:
-                self._connect_from_dict(json_connection["src"], json_connection["dst"])
+                wire.connect(self)
             except DigsimException as exc:
                 if connect_exceptions:
                     raise exc
@@ -325,15 +287,10 @@ class Circuit:
 
     def to_json_file(self, filename):
         """Store circuit in json file"""
-        circuit_dict = self.to_dict()
-        json_object = json.dumps(circuit_dict, indent=4)
-
-        with open(filename, mode="w", encoding="utf-8") as json_file:
-            json_file.write(json_object)
+        circuitfile_dc = CircuitFileDataClass(circuit=self.to_dataclass())
+        circuitfile_dc.save(filename)
 
     def from_json_file(self, filename, folder=None):
         """Load circuit from json file"""
-        self._folder = folder
-        with open(filename, mode="r", encoding="utf-8") as json_file:
-            circuit_dict = json.load(json_file)
-            self.from_dict(circuit_dict, folder)
+        file_dc = CircuitFileDataClass.load(filename)
+        self.from_dataclass(file_dc.circuit, folder)

digsim/circuit/_waves_writer.py

@@ -1,13 +1,10 @@
-# Copyright (c) Fredrik Andersson, 2023
+# Copyright (c) Fredrik Andersson, 2023-2024
 # All rights reserved
 
 """
 Module that handles the creation of vcd files
 """
 
-# pylint: disable=consider-using-with
-# pylint: disable=import-error
-
 from vcd import VCDWriter
 
 

digsim/circuit/components/__init__.py

@@ -1,7 +1,7 @@
 # Copyright (c) Fredrik Andersson, 2023
 # All rights reserved
 
-""" All classes within digsim.circuit.components namespace """
+"""All classes within digsim.circuit.components namespace"""
 
 from ._bus_bits import Bus2Wires, Wires2Bus  # noqa: F401
 from ._button import PushButton  # noqa: F401

digsim/circuit/components/_bus_bits.py

@@ -29,7 +29,7 @@ class Bus2Wires(Component):
     def get_parameters(cls):
         return {
             "width": {
-                "type": int,
+                "type": "int",
                 "min": 2,
                 "max": 32,
                 "default": 2,
@@ -59,7 +59,7 @@ class Wires2Bus(Component):
     def get_parameters(cls):
         return {
             "width": {
-                "type": int,
+                "type": "int",
                 "min": 2,
                 "max": 32,
                 "default": 2,

digsim/circuit/components/_button.py

@@ -1,7 +1,7 @@
 # Copyright (c) Fredrik Andersson, 2023
 # All rights reserved
 
-""" A PushButton component """
+"""A PushButton component"""
 
 import logging
 

digsim/circuit/components/_buzzer.py

@@ -1,7 +1,7 @@
 # Copyright (c) Fredrik Andersson, 2023
 # All rights reserved
 
-""" Module with the Buzzer component """
+"""Module with the Buzzer component"""
 
 from .atoms import CallbackComponent, PortIn
 
@@ -36,7 +36,7 @@ class Buzzer(CallbackComponent):
     def get_parameters(cls):
         return {
             "tone": {
-                "type": list,
+                "type": "list",
                 "items": ["A", "B", "C", "D", "E", "F", "G"],
                 "default": "A",
                 "description": "Buzzer tone",

digsim/circuit/components/_clock.py

@@ -1,7 +1,7 @@
 # Copyright (c) Fredrik Andersson, 2023
 # All rights reserved
 
-""" Clock component module """
+"""Clock component module"""
 
 from .atoms import CallbackComponent, PortOutDelta, PortOutImmediate
 
@@ -44,7 +44,7 @@ class Clock(CallbackComponent):
     def get_parameters(cls):
         return {
             "frequency": {
-                "type": int,
+                "type": "int",
                 "min": 1,
                 "max": 50,
                 "default": 1,

digsim/circuit/components/_dip_switch.py

@@ -1,7 +1,7 @@
 # Copyright (c) Fredrik Andersson, 2023
 # All rights reserved
 
-""" A Dip-switch component """
+"""A Dip-switch component"""
 
 from .atoms import CallbackComponent, PortOutImmediate
 
@@ -64,7 +64,7 @@ class DipSwitch(CallbackComponent):
     def get_parameters(cls):
         return {
             "bits": {
-                "type": int,
+                "type": "int",
                 "min": 2,
                 "max": 8,
                 "default": 8,

digsim/circuit/components/_gates.py

@@ -1,9 +1,7 @@
-# Copyright (c) Fredrik Andersson, 2023
+# Copyright (c) Fredrik Andersson, 2023-2024
 # All rights reserved
 
-""" Module with the basic logic gates """
-
-# pylint: disable=too-many-arguments
+"""Module with the basic logic gates"""
 
 import math
 
@@ -46,7 +44,7 @@ class ConfigPortsComponent(Component):
     def get_parameters(cls):
         return {
             "ports": {
-                "type": int,
+                "type": "int",
                 "min": 2,
                 "max": 8,
                 "default": 2,
@@ -163,17 +161,17 @@ class DFF(Component):
     def get_parameters(cls):
         return {
             "async_reset": {
-                "type": bool,
+                "type": "bool",
                 "default": False,
                 "description": "Use asynchronous reset",
             },
             "clock_enable": {
-                "type": bool,
+                "type": "bool",
                 "default": False,
                 "description": "Use clock enable",
             },
             "width": {
-                "type": int,
+                "type": "int",
                 "min": 1,
                 "max": 32,
                 "default": 1,
@@ -217,7 +215,7 @@ class MUX(Component):
                 "description": "Number of input ports",
             },
             "width": {
-                "type": int,
+                "type": "int",
                 "min": 1,
                 "max": 32,
                 "default": 1,

digsim/circuit/components/_hexdigit.py

@@ -1,7 +1,7 @@
 # Copyright (c) Fredrik Andersson, 2023
 # All rights reserved
 
-""" HexDigit component module """
+"""HexDigit component module"""
 
 from .atoms import CallbackComponent, PortIn
 
@@ -68,14 +68,14 @@ class HexDigit(CallbackComponent):
     def get_parameters(cls):
         return {
             "digits": {
-                "type": int,
+                "type": "int",
                 "min": 1,
                 "max": 8,
                 "default": 1,
                 "description": "Number of digits",
             },
             "dot": {
-                "type": bool,
+                "type": "bool",
                 "default": False,
                 "description": "Use decimal dot",
             },

digsim/circuit/components/_ic.py

@@ -4,6 +4,7 @@
 """
 Module for creating a yosys component in the ic folder
 """
+
 from pathlib import Path
 
 from ._yosys_component import YosysComponent

digsim/circuit/components/_label_wire.py

@@ -1,7 +1,7 @@
 # Copyright (c) Fredrik Andersson, 2023
 # All rights reserved
 
-""" Label Wire components module """
+"""Label Wire components module"""
 
 from .atoms import Component, DigsimException, PortWire
 
@@ -106,14 +106,14 @@ class LabelWireIn(Component):
 
         return {
             "label": {
-                "type": str,
+                "type": "str",
                 "single_line": True,
                 "default": "WireLabel",
                 "description": "Label name",
                 "invalid_list": label_list,
             },
             "width": {
-                "type": int,
+                "type": "int",
                 "min": 1,
                 "max": 32,
                 "default": 1,
@@ -160,7 +160,7 @@ class LabelWireOut(Component):
 
         return {
             "label": {
-                "type": list,
+                "type": "list",
                 "items": label_list,
                 "description": "Select label",
             }

digsim/circuit/components/_led.py

@@ -1,7 +1,7 @@
 # Copyright (c) Fredrik Andersson, 2023
 # All rights reserved
 
-""" Module with the LED component """
+"""Module with the LED component"""
 
 from .atoms import CallbackComponent, PortIn
 

digsim/circuit/components/_logic_analyzer.py

@@ -1,7 +1,7 @@
 # Copyright (c) Fredrik Andersson, 2023
 # All rights reserved
 
-""" Module with Logic Analyzer component """
+"""Module with Logic Analyzer component"""
 
 from .atoms import CallbackComponent, PortOutDelta, PortWire
 
@@ -50,7 +50,7 @@ class LogicAnalyzer(CallbackComponent):
     def get_parameters(cls):
         return {
             "sample_rate": {
-                "type": int,
+                "type": "int",
                 "min": 10,
                 "max": 100,
                 "default": 20,

digsim/circuit/components/_note.py

@@ -17,7 +17,7 @@ class Note(Component):
     def get_parameters(cls):
         return {
             "text": {
-                "type": str,
+                "type": "str",
                 "default": "Write something here...",
                 "description": "Note text",
                 "reconfigurable": True,

digsim/circuit/components/_on_off_switch.py

@@ -1,7 +1,7 @@
 # Copyright (c) Fredrik Andersson, 2023
 # All rights reserved
 
-""" An On/Off Switch  component """
+"""An On/Off Switch  component"""
 
 import logging
 

digsim/circuit/components/_seven_segment.py

@@ -1,7 +1,8 @@
 # Copyright (c) Fredrik Andersson, 2023
 # All rights reserved
 
-""" Module with 7-segment LED component """
+"""Module with 7-segment LED component"""
+
 from .atoms import CallbackComponent, PortIn
 
 

digsim/circuit/components/_static_level.py

@@ -1,7 +1,7 @@
 # Copyright (c) Fredrik Andersson, 2023
 # All rights reserved
 
-""" Module with the Static Logic components """
+"""Module with the Static Logic components"""
 
 from .atoms import Component, PortOutDelta
 

digsim/circuit/components/_static_value.py

@@ -1,7 +1,7 @@
 # Copyright (c) Fredrik Andersson, 2023
 # All rights reserved
 
-""" Module with the Static Leve component """
+"""Module with the Static Leve component"""
 
 from .atoms import Component, PortOutImmediate
 
@@ -35,7 +35,7 @@ class StaticValue(Component):
                 "reconfigurable": True,
             },
             "width": {
-                "type": int,
+                "type": "int",
                 "min": 1,
                 "max": 16,
                 "default": 1,

digsim/circuit/components/_yosys_atoms.py

@@ -1,4 +1,4 @@
-# Copyright (c) Fredrik Andersson, 2023
+# Copyright (c) Fredrik Andersson, 2023-2024
 # All rights reserved
 
 """
@@ -8,11 +8,6 @@ All components are implemented from the specification in:
 https://github.com/YosysHQ/yosys/blob/master/techlibs/common/simcells.v
 """
 
-# pylint: disable=too-many-arguments
-# pylint: disable=consider-using-in
-# pylint: disable=too-many-lines
-# pylint: disable=too-many-branches
-
 from .atoms import Component, DigsimException, PortIn, PortOutDelta, PortWire
 
 

digsim/circuit/components/_yosys_component.py

@@ -1,4 +1,4 @@
-# Copyright (c) Fredrik Andersson, 2023
+# Copyright (c) Fredrik Andersson, 2023-2024
 # All rights reserved
 
 """
@@ -6,9 +6,6 @@ Module with classes to create a yosys component
 from a yosys json netlist.
 """
 
-# pylint: disable=protected-access
-# pylint: disable=too-many-instance-attributes
-
 import json
 
 import digsim.circuit.components._yosys_atoms

digsim/circuit/components/atoms/__init__.py

@@ -1,7 +1,7 @@
 # Copyright (c) Fredrik Andersson, 2023
 # All rights reserved
 
-""" All classes within digsim.circuit.components.atoms namespace """
+"""All classes within digsim.circuit.components.atoms namespace"""
 
 from ._component import (  # noqa: F401
     CallbackComponent,

digsim/circuit/components/atoms/_component.py

@@ -1,14 +1,10 @@
-# Copyright (c) Fredrik Andersson, 2023
+# Copyright (c) Fredrik Andersson, 2023-2024
 # All rights reserved
 
-""" This module contains the base classes for all component types """
-
-
-# pylint: disable=too-many-public-methods
+"""This module contains the base classes for all component types"""
 
 import abc
 import copy
-import importlib
 
 from ._digsim_exception import DigsimException
 
@@ -169,44 +165,6 @@ class Component(abc.ABC):
             comp_str += f"\n - O:{port.name()}={port.value}"
         return comp_str
 
-    def to_dict(self):
-        """Return the component information as a dict, used when storing a circuit"""
-        component_dict = {
-            "name": self.name(),
-            "display_name": self.display_name(),
-        }
-
-        module_split = type(self).__module__.split(".")
-        type_str = ""
-        for module in module_split:
-            if not module.startswith("_"):
-                type_str += f"{module}."
-        type_str += type(self).__name__
-        component_dict["type"] = type_str
-        component_dict["settings"] = self.settings_to_dict()
-        return component_dict
-
-    @classmethod
-    def from_dict(cls, circuit, json_component):
-        """Factory: Create a component from a dict"""
-        component_name = json_component["name"]
-        component_type = json_component["type"]
-        component_settings = json_component.get("settings", {})
-        if "path" in component_settings:
-            component_settings["path"] = circuit.load_path(component_settings["path"])
-
-        display_name = json_component.get("display_name")
-        py_module_name = ".".join(component_type.split(".")[0:-1])
-        py_class_name = component_type.split(".")[-1]
-
-        module = importlib.import_module(py_module_name)
-        class_ = getattr(module, py_class_name)
-        component = class_(circuit=circuit, **component_settings)
-        component.set_name(component_name)
-        if display_name is not None:
-            component.set_display_name(display_name)
-        return component
-
     @property
     def has_action(self):
         """Return True if this component is interactive"""

digsim/circuit/components/atoms/_port.py

@@ -1,9 +1,7 @@
-# Copyright (c) Fredrik Andersson, 2023
+# Copyright (c) Fredrik Andersson, 2023-2024
 # All rights reserved
 
-""" This module contains the classes for all component ports """
-
-# pylint: disable=too-many-public-methods
+"""This module contains the classes for all component ports"""
 
 import abc
 
@@ -33,6 +31,11 @@ class Port(abc.ABC):
         self._edge_detect_value = "X"
         self.update_wires("X")
 
+    @property
+    def wired_ports(self):
+        """Get wires from thisport"""
+        return self._wired_ports
+
     @property
     def value(self):
         """Get the value of the port, can be "X" """
@@ -176,20 +179,6 @@ class Port(abc.ABC):
     def __str__(self):
         return f"{self._parent.name()}:{self._name}={self.value}"
 
-    def to_dict_list(self):
-        """Output port connections as a dict, used when storing a circuit"""
-        port_conn_list = []
-        for port in self._wired_ports:
-            # Only add port on top-level components
-            if port.parent().is_toplevel():
-                port_conn_list.append(
-                    {
-                        "src": f"{self.parent().name()}.{self.name()}",
-                        "dst": f"{port.parent().name()}.{port.name()}",
-                    }
-                )
-        return port_conn_list
-
 
 class PortWire(Port):
     """

digsim/storage_model/__init__.py

@@ -0,0 +1,7 @@
+# Copyright (c) Fredrik Andersson, 2024
+# All rights reserved
+
+"""All classes within digsim.storage_model namespace"""
+
+from ._app import AppFileDataClass, GuiPositionDataClass, ModelDataClass
+from ._circuit import CircuitDataClass, CircuitFileDataClass, ComponentDataClass, WireDataClass