da4ml 0.5.1.post1__cp311-cp311-manylinux_2_24_x86_64.manylinux_2_28_x86_64.whl

da4ml/codegen/rtl/verilog/comb.py

@@ -0,0 +1,239 @@
+from hashlib import sha256
+from math import ceil, log2
+from uuid import UUID
+
+import numpy as np
+
+from ....cmvm.types import CombLogic, Op, QInterval, _minimal_kif
+
+
+def make_neg(lines: list[str], idx: int, qint: QInterval, v0_name: str, neg_repo: dict[int, tuple[int, str]]):
+    if idx == 21568:
+        pass
+    if idx in neg_repo:
+        return neg_repo[idx]
+    _min, _max, step = qint
+    bw0 = sum(_minimal_kif(qint))
+    bw_neg = sum(_minimal_kif(QInterval(-_max, -_min, step)))
+    was_signed = int(_min < 0)
+    lines.append(
+        f'wire [{bw_neg - 1}:0] v{idx}_neg; negative #({bw0}, {bw_neg}, {was_signed}) op_neg_{idx} ({v0_name}, v{idx}_neg);'
+    )
+    bw0 = bw_neg
+    v0_name = f'v{idx}_neg'
+    neg_repo[idx] = (bw0, v0_name)
+    return bw0, v0_name
+
+
+def gen_mem_file(sol: CombLogic, op: Op) -> str:
+    assert op.opcode == 8
+    assert sol.lookup_tables is not None
+    table = sol.lookup_tables[op.data]
+    width = sum(table.spec.out_kif)
+    ndigits = ceil(width / 4)
+    data = table.padded_table(sol.ops[op.id0].qint)
+    mem_lines = [f'{hex(value)[2:].upper().zfill(ndigits)}' for value in data & ((1 << width) - 1)]
+    return '\n'.join(mem_lines)
+
+
+def get_table_name(sol: CombLogic, op: Op) -> str:
+    memfile = gen_mem_file(sol, op)
+    hash_obj = sha256(memfile.encode('utf-8'))
+    _int = int(hash_obj.hexdigest()[:32], 16)
+    uuid = UUID(int=_int, version=4)
+    return f'table_{str(uuid)}.mem'
+
+
+def ssa_gen(sol: CombLogic, neg_repo: dict[int, tuple[int, str]], print_latency: bool = False) -> list[str]:
+    ops = sol.ops
+    kifs = list(map(_minimal_kif, (op.qint for op in ops)))
+    widths: list[int] = list(map(sum, kifs))
+    inp_kifs = [_minimal_kif(qint) for qint in sol.inp_qint]
+    inp_widths = list(map(sum, inp_kifs))
+    _inp_widths = np.cumsum([0] + inp_widths)
+    inp_idxs = np.stack([_inp_widths[1:] - 1, _inp_widths[:-1]], axis=1)
+
+    lines: list[str] = []
+    ref_count = sol.ref_count
+
+    for i, op in enumerate(ops):
+        if ref_count[i] == 0:
+            continue
+
+        bw = widths[i]
+        v = f'v{i}[{bw - 1}:0]'
+        _def = f'wire [{bw - 1}:0] v{i};'
+        if bw == 0:
+            continue
+
+        match op.opcode:
+            case -1:  # Input marker
+                i0, i1 = inp_idxs[op.id0]
+                line = f'{_def} assign {v} = model_inp[{i0}:{i1}];'
+
+            case 0 | 1:  # Common a+/-b<<shift oprs
+                p0, p1 = kifs[op.id0], kifs[op.id1]  # precision -> keep_neg, integers (no sign), fractional
+
+                bw0, bw1 = widths[op.id0], widths[op.id1]  # width
+                s0, f0, s1, f1 = int(p0[0]), p0[2], int(p1[0]), p1[2]
+                shift = op.data + f0 - f1
+                v0, v1 = f'v{op.id0}[{bw0 - 1}:0]', f'v{op.id1}[{bw1 - 1}:0]'
+
+                line = f'{_def} shift_adder #({bw0}, {bw1}, {s0}, {s1}, {bw}, {shift}, {op.opcode}) op_{i} ({v0}, {v1}, {v});'
+
+            case 2 | -2:  # ReLU
+                lsb_bias = kifs[op.id0][2] - kifs[i][2]
+                i0, i1 = bw + lsb_bias - 1, lsb_bias
+
+                v0_name = f'v{op.id0}'
+                bw0 = widths[op.id0]
+
+                if op.opcode == -2:
+                    bw0, v0_name = make_neg(lines, op.id0, ops[op.id0].qint, v0_name, neg_repo)
+                if ops[op.id0].qint.min < 0:
+                    line = f'{_def} assign {v} = {v0_name}[{i0}:{i1}] & {{{bw}{{~{v0_name}[{bw0 - 1}]}}}};'
+                else:
+                    line = f'{_def} assign {v} = {v0_name}[{i0}:{i1}];'
+
+            case 3 | -3:  # Explicit quantization
+                lsb_bias = kifs[op.id0][2] - kifs[i][2]
+                i0, i1 = bw + lsb_bias - 1, lsb_bias
+                v0_name = f'v{op.id0}'
+                bw0 = widths[op.id0]
+
+                if op.opcode == -3:
+                    bw0, v0_name = make_neg(lines, op.id0, ops[op.id0].qint, v0_name, neg_repo)
+
+                if i0 >= bw0:
+                    if op.opcode == 3:
+                        assert ops[op.id0].qint.min < 0, f'{i}, {op.id0}'
+                    else:
+                        assert ops[op.id0].qint.max > 0, f'{i}, {op.id0}'
+
+                    if i1 >= bw0:
+                        v0_name = f'{{{i0 - i1 + 1}{{{v0_name}[{bw0 - 1}]}}}}'
+                    else:
+                        v0_name = f'{{{{{i0 - bw0 + 1}{{{v0_name}[{bw0 - 1}]}}}}, {v0_name}[{bw0 - 1}:{i1}]}}'
+                    line = f'{_def} assign {v} = {v0_name};'
+                else:
+                    line = f'{_def} assign {v} = {v0_name}[{i0}:{i1}];'
+
+            case 4:  # constant addition
+                num = op.data
+                sign, mag = int(num < 0), abs(num)
+                bw1 = ceil(log2(mag + 1))
+                bw0 = widths[op.id0]
+                s0 = int(kifs[op.id0][0])
+                v0 = f'v{op.id0}[{bw0 - 1}:0]'
+                v1 = f"{bw1}'{bin(mag)[1:]}"
+                shift = kifs[op.id0][2] - kifs[i][2]
+
+                line = f'{_def} shift_adder #({bw0}, {bw1}, {s0}, 0, {bw}, {shift}, {sign}) op_{i} ({v0}, {v1}, {v});'
+
+            case 5:  # constant
+                num = op.data
+                if num < 0:
+                    num = 2**bw + num
+                line = f"{_def} assign {v} = '{bin(num)[1:]};"
+
+            case 6 | -6:  # MSB Muxing
+                k, a, b = op.data & 0xFFFFFFFF, op.id0, op.id1
+                p0, p1 = kifs[a], kifs[b]
+                inv = '1' if op.opcode == -6 else '0'
+                bwk, bw0, bw1 = widths[k], widths[a], widths[b]
+                s0, f0, s1, f1 = int(p0[0]), p0[2], int(p1[0]), p1[2]
+                _shift = (op.data >> 32) & 0xFFFFFFFF
+                _shift = _shift if _shift < 0x80000000 else _shift - 0x100000000
+                shift = f0 - f1 + _shift
+                vk, v0, v1 = f'v{k}[{bwk - 1}]', f'v{a}[{bw0 - 1}:0]', f'v{b}[{bw1 - 1}:0]'
+                if bw0 == 0:
+                    v0, bw0 = "1'b0", 1
+                if bw1 == 0:
+                    v1, bw1 = "1'b0", 1
+
+                line = f'{_def} mux #({bw0}, {bw1}, {s0}, {s1}, {bw}, {shift}, {inv}) op_{i} ({vk}, {v0}, {v1}, {v});'
+
+            case 7:  # Multiplication
+                bw0, bw1 = widths[op.id0], widths[op.id1]  # width
+                s0, s1 = int(kifs[op.id0][0]), int(kifs[op.id1][0])
+                v0, v1 = f'v{op.id0}[{bw0 - 1}:0]', f'v{op.id1}[{bw1 - 1}:0]'
+
+                line = f'{_def} multiplier #({bw0}, {bw1}, {s0}, {s1}, {bw}) op_{i} ({v0}, {v1}, {v});'
+
+            case 8:  # Lookup Table
+                name = get_table_name(sol, op)
+                bw0 = widths[op.id0]
+
+                line = f'{_def} lookup_table #({bw0}, {bw}, "{name}") op_{i} (v{op.id0}, {v});'
+
+            case _:
+                raise ValueError(f'Unknown opcode {op.opcode} for operation {i} ({op})')
+
+        if print_latency:
+            line += f' // {op.latency}'
+        lines.append(line)
+    return lines
+
+
+def output_gen(sol: CombLogic, neg_repo: dict[int, tuple[int, str]]) -> list[str]:
+    lines = []
+    widths = list(map(sum, map(_minimal_kif, sol.out_qint)))
+    _widths = np.cumsum([0] + widths)
+    out_idxs = np.stack([_widths[1:] - 1, _widths[:-1]], axis=1)
+    for i, idx in enumerate(sol.out_idxs):
+        if idx < 0:
+            continue
+        i0, i1 = out_idxs[i]
+        if i0 == i1 - 1:
+            continue
+        bw = widths[i]
+        if sol.out_negs[i]:
+            _, name = make_neg(lines, idx, sol.ops[idx].qint, f'v{idx}', neg_repo)
+            lines.append(f'assign model_out[{i0}:{i1}] = {name}[{bw - 1}:0];')
+
+        else:
+            lines.append(f'assign model_out[{i0}:{i1}] = v{idx}[{bw - 1}:0];')
+    return lines
+
+
+def comb_logic_gen(sol: CombLogic, fn_name: str, print_latency: bool = False, timescale: str | None = None):
+    inp_bits = sum(map(sum, map(_minimal_kif, sol.inp_qint)))
+    out_bits = sum(map(sum, map(_minimal_kif, sol.out_qint)))
+
+    fn_signature = [
+        f'module {fn_name} (',
+        f'    input [{inp_bits - 1}:0] model_inp,',
+        f'    output [{out_bits - 1}:0] model_out',
+        ');',
+    ]
+
+    neg_repo: dict[int, tuple[int, str]] = {}
+    ssa_lines = ssa_gen(sol, neg_repo=neg_repo, print_latency=print_latency)
+    output_lines = output_gen(sol, neg_repo)
+
+    indent = '    '
+    base_indent = '\n'
+    body_indent = base_indent + indent
+    code = f"""{base_indent[1:]}{base_indent.join(fn_signature)}
+
+    // verilator lint_off UNUSEDSIGNAL
+    // Explicit quantization operation will drop bits if exists
+
+    {body_indent.join(ssa_lines)}
+
+    // verilator lint_on UNUSEDSIGNAL
+
+    {body_indent.join(output_lines)}
+
+    endmodule
+"""
+    if timescale is not None:
+        code = f'{timescale}\n\n{code}'
+    return code
+
+
+def table_mem_gen(sol: CombLogic) -> dict[str, str]:
+    if not sol.lookup_tables:
+        return {}
+    mem_files = {get_table_name(sol, op): gen_mem_file(sol, op) for op in sol.ops if op.opcode == 8}
+    return mem_files

da4ml/codegen/rtl/verilog/io_wrapper.py

@@ -0,0 +1,113 @@
+from itertools import accumulate
+
+from ....cmvm.types import CombLogic, Pipeline, QInterval, _minimal_kif
+
+
+def hetero_io_map(qints: list[QInterval], merge: bool = False):
+    N = len(qints)
+    ks, _is, fs = zip(*map(_minimal_kif, qints))
+    Is = [_i + _k for _i, _k in zip(_is, ks)]
+    max_I, max_f = max(_is) + max(ks), max(fs)
+    max_bw = max_I + max_f
+    width_regular, width_packed = max_bw * N, sum(Is) + sum(fs)
+
+    regular: list[tuple[int, int]] = []
+    pads: list[tuple[int, int, int]] = []
+
+    bws = [I + f for I, f in zip(Is, fs)]
+    _bw = list(accumulate([0] + bws))
+    hetero = [(i - 1, j) for i, j in zip(_bw[1:], _bw[:-1])]
+
+    for i in range(N):
+        base = max_bw * i
+        bias_low = max_f - fs[i]
+        bias_high = max_I - Is[i]
+        low = base + bias_low
+        high = (base + max_bw - 1) - bias_high
+        regular.append((high, low))
+
+        if bias_low != 0:
+            pads.append((base + bias_low - 1, base, -1))
+        if bias_high != 0:
+            copy_from = hetero[i][0] if ks[i] else -1
+            pads.append((base + max_bw - 1, base + max_bw - bias_high, copy_from))
+
+    mask = list(high < low for high, low in hetero)
+    regular = [r for r, m in zip(regular, mask) if not m]
+    hetero = [h for h, m in zip(hetero, mask) if not m]
+
+    if not merge:
+        return regular, hetero, pads, (width_regular, width_packed)
+
+    # Merging consecutive intervals when possible
+    NN = len(regular) - 2
+    for i in range(NN, -1, -1):
+        this_high = regular[i][0]
+        next_low = regular[i + 1][1]
+        if next_low - this_high != 1:
+            continue
+        regular[i] = (regular[i + 1][0], regular[i][1])
+        regular.pop(i + 1)
+        hetero[i] = (hetero[i + 1][0], hetero[i][1])
+        hetero.pop(i + 1)
+
+    for i in range(len(pads) - 2, -1, -1):
+        if pads[i + 1][1] - pads[i][0] == 1 and pads[i][2] == pads[i + 1][2]:
+            pads[i] = (pads[i + 1][0], pads[i][1], pads[i][2])
+            pads.pop(i + 1)
+
+    return regular, hetero, pads, (width_regular, width_packed)
+
+
+def generate_io_wrapper(sol: CombLogic | Pipeline, module_name: str, pipelined: bool = False):
+    reg_in, het_in, _, shape_in = hetero_io_map(sol.inp_qint, merge=True)
+    reg_out, het_out, pad_out, shape_out = hetero_io_map(sol.out_qint, merge=True)
+
+    w_reg_in, w_het_in = shape_in
+    w_reg_out, w_het_out = shape_out
+
+    inp_assignment = [f'assign packed_inp[{ih}:{jh}] = model_inp[{ir}:{jr}];' for (ih, jh), (ir, jr) in zip(het_in, reg_in)]
+    _out_assignment: list[tuple[int, str]] = []
+
+    for i, ((ih, jh), (ir, jr)) in enumerate(zip(het_out, reg_out)):
+        if ih == jh - 1:
+            continue
+        _out_assignment.append((ih, f'assign model_out[{ir}:{jr}] = packed_out[{ih}:{jh}];'))
+
+    for i, (i, j, copy_from) in enumerate(pad_out):
+        n_bit = i - j + 1
+        pad = f"{n_bit}'b0" if copy_from == -1 else f'{{{n_bit}{{packed_out[{copy_from}]}}}}'
+        _out_assignment.append((i, f'assign model_out[{i}:{j}] = {pad};'))
+    _out_assignment.sort(key=lambda x: x[0])
+    out_assignment = [v for _, v in _out_assignment]
+
+    inp_assignment_str = '\n    '.join(inp_assignment)
+    out_assignment_str = '\n    '.join(out_assignment)
+
+    clk_and_rst_inp, clk_and_rst_bind = '', ''
+    if pipelined:
+        clk_and_rst_inp = '\n   input clk,'
+        clk_and_rst_bind = '\n        .clk(clk),'
+
+    return f"""`timescale 1 ns / 1 ps
+
+module {module_name}_wrapper ({clk_and_rst_inp}
+    // verilator lint_off UNUSEDSIGNAL
+    input [{w_reg_in - 1}:0] model_inp,
+    // verilator lint_on UNUSEDSIGNAL
+    output [{w_reg_out - 1}:0] model_out
+);
+    wire [{w_het_in - 1}:0] packed_inp;
+    wire [{w_het_out - 1}:0] packed_out;
+
+    {inp_assignment_str}
+
+    {module_name} op ({clk_and_rst_bind}
+        .model_inp(packed_inp),
+        .model_out(packed_out)
+    );
+
+    {out_assignment_str}
+
+endmodule
+"""

da4ml/codegen/rtl/verilog/pipeline.py

@@ -0,0 +1,67 @@
+from ....cmvm.types import Pipeline, _minimal_kif
+from .comb import comb_logic_gen
+
+
+def pipeline_logic_gen(
+    csol: Pipeline,
+    name: str,
+    print_latency=False,
+    timescale: str | None = '`timescale 1 ns / 1 ps',
+    register_layers: int = 1,
+):
+    N = len(csol.solutions)
+    inp_bits = [sum(map(sum, map(_minimal_kif, sol.inp_qint))) for sol in csol.solutions]
+    out_bits = inp_bits[1:] + [sum(map(sum, map(_minimal_kif, csol.out_qint)))]
+
+    registers = [f'reg [{width - 1}:0] stage{i}_inp;' for i, width in enumerate(inp_bits)]
+    for i in range(0, register_layers - 1):
+        registers += [f'reg [{width - 1}:0] stage{j}_inp_copy{i};' for j, width in enumerate(inp_bits)]
+    wires = [f'wire [{width - 1}:0] stage{i}_out;' for i, width in enumerate(out_bits)]
+
+    comb_logic = [f'{name}_stage{i} stage{i} (.model_inp(stage{i}_inp), .model_out(stage{i}_out));' for i in range(N)]
+
+    if register_layers == 1:
+        serial_logic = ['stage0_inp <= model_inp;']
+        serial_logic += [f'stage{i}_inp <= stage{i - 1}_out;' for i in range(1, N)]
+    else:
+        serial_logic = ['stage0_inp_copy0 <= model_inp;']
+        for j in range(1, register_layers - 1):
+            serial_logic.append(f'stage0_inp_copy{j} <= stage0_inp_copy{j - 1};')
+        serial_logic.append(f'stage0_inp <= stage0_inp_copy{register_layers - 2};')
+        for i in range(1, N):
+            serial_logic.append(f'stage{i}_inp_copy0 <= stage{i - 1}_out;')
+            for j in range(1, register_layers - 1):
+                serial_logic.append(f'stage{i}_inp_copy{j} <= stage{i}_inp_copy{j - 1};')
+            serial_logic.append(f'stage{i}_inp <= stage{i}_inp_copy{register_layers - 2};')
+
+    serial_logic += [f'model_out <= stage{N - 1}_out;']
+
+    sep0 = '\n    '
+    sep1 = '\n        '
+
+    module = f"""module {name} (
+    input clk,
+    input [{inp_bits[0] - 1}:0] model_inp,
+    output reg [{out_bits[-1] - 1}:0] model_out
+);
+
+    {sep0.join(registers)}
+    {sep0.join(wires)}
+
+    {sep0.join(comb_logic)}
+
+    always @(posedge clk) begin
+        {sep1.join(serial_logic)}
+    end
+endmodule
+"""
+
+    if timescale:
+        module = f'{timescale}\n\n{module}'
+
+    ret: dict[str, str] = {}
+    for i, s in enumerate(csol.solutions):
+        stage_name = f'{name}_stage{i}'
+        ret[stage_name] = comb_logic_gen(s, stage_name, print_latency=print_latency, timescale=timescale)
+    ret[name] = module
+    return ret

da4ml/codegen/rtl/verilog/source/lookup_table.v

@@ -0,0 +1,27 @@
+`timescale 1ns / 1ps
+
+
+module lookup_table #(
+    parameter BW_IN = 8,
+    parameter BW_OUT = 8,
+    parameter MEM_FILE = "whatever.mem"
+) (
+    input [BW_IN-1:0] in,
+    output [BW_OUT-1:0] out
+);
+
+  (* rom_style = (BW_IN <= 999) ? "distributed" : "block" *)
+  reg [BW_OUT-1:0] lut_rom [0:(1<<BW_IN)-1];
+  reg [BW_OUT-1:0] readout;
+
+  initial begin
+    $readmemh(MEM_FILE, lut_rom);
+  end
+
+  assign out[BW_OUT-1:0] = readout[BW_OUT-1:0];
+
+  always @(*) begin
+    readout = lut_rom[in];
+  end
+
+endmodule

da4ml/codegen/rtl/verilog/source/multiplier.v

@@ -0,0 +1,37 @@
+`timescale 1ns / 1ps
+
+
+module multiplier #(
+    parameter BW_INPUT0 = 32,
+    parameter BW_INPUT1 = 32,
+    parameter SIGNED0 = 0,
+    parameter SIGNED1 = 0,
+    parameter BW_OUT = 32
+) (
+    input [BW_INPUT0-1:0] in0,
+    input [BW_INPUT1-1:0] in1,
+    output [BW_OUT-1:0] out
+);
+
+  localparam BW_BUF = BW_INPUT0 + BW_INPUT1;
+
+  // verilator lint_off UNUSEDSIGNAL
+  wire [BW_BUF - 1:0] buffer;
+  // verilator lint_on UNUSEDSIGNAL
+
+  generate
+    if (SIGNED0 == 1 && SIGNED1 == 1) begin : signed_signed
+      assign buffer[BW_BUF-1:0] = $signed(in0) * $signed(in1);
+    end else if (SIGNED0 == 1 && SIGNED1 == 0) begin : signed_unsigned
+      assign buffer[BW_BUF-1:0] = $signed(in0) * $signed({{1'b0,in1}});
+      // assign buffer[BW_BUF-1] = in0[BW_INPUT0-1];
+    end else if (SIGNED0 == 0 && SIGNED1 == 1) begin : unsigned_signed
+      assign buffer[BW_BUF-1:0] = $signed({{1'b0,in0}}) * $signed(in1);
+      // assign buffer[BW_BUF-1] = in1[BW_INPUT1-1];
+    end else begin : unsigned_unsigned
+      assign buffer[BW_BUF-1:0] = in0 * in1;
+    end
+  endgenerate
+
+  assign out[BW_OUT-1:0] = buffer[BW_OUT-1:0];
+endmodule

da4ml/codegen/rtl/verilog/source/mux.v

@@ -0,0 +1,58 @@
+`timescale 1ns / 1ps
+
+
+module mux #(
+    parameter BW_INPUT0 = 32,
+    parameter BW_INPUT1 = 32,
+    parameter SIGNED0 = 0,
+    parameter SIGNED1 = 0,
+    parameter BW_OUT = 32,
+    parameter SHIFT1 = 0,
+    parameter INVERT1 = 0
+) (
+    input key,
+    input [BW_INPUT0-1:0] in0,
+    input [BW_INPUT1-1:0] in1,
+    output [BW_OUT-1:0] out
+);
+
+  localparam IN0_NEED_BITS = (SHIFT1 < 0) ? BW_INPUT0 - SHIFT1 : BW_INPUT0;
+  localparam IN1_NEED_BITS = (SHIFT1 > 0) ? BW_INPUT1 + SHIFT1 : BW_INPUT1;
+  localparam EXTRA_PAD = (SIGNED0 != SIGNED1) ? INVERT1 + 1 : INVERT1 + 0;
+  localparam BW_BUF = (IN0_NEED_BITS > IN1_NEED_BITS) ? IN0_NEED_BITS + EXTRA_PAD : IN1_NEED_BITS + EXTRA_PAD;
+  localparam IN0_PAD_LEFT = (SHIFT1 < 0) ? BW_BUF - BW_INPUT0 + SHIFT1 : BW_BUF - BW_INPUT0;
+  localparam IN0_PAD_RIGHT = (SHIFT1 < 0) ? -SHIFT1 : 0;
+  localparam IN1_PAD_LEFT = (SHIFT1 > 0) ? BW_BUF - BW_INPUT1 - SHIFT1 : BW_BUF - BW_INPUT1;
+  localparam IN1_PAD_RIGHT = (SHIFT1 > 0) ? SHIFT1 : 0;
+
+
+  // verilator lint_off UNUSEDSIGNAL
+  wire [BW_BUF-1:0] in0_ext;
+  wire [BW_BUF-1:0] in1_ext;
+  // verilator lint_on UNUSEDSIGNAL
+
+  generate
+    if (SIGNED0 == 1) begin : in0_is_signed
+      assign in0_ext = {{IN0_PAD_LEFT{in0[BW_INPUT0-1]}}, in0, {IN0_PAD_RIGHT{1'b0}}};
+    end else begin : in0_is_unsigned
+      assign in0_ext = {{IN0_PAD_LEFT{1'b0}}, in0, {IN0_PAD_RIGHT{1'b0}}};
+    end
+  endgenerate
+
+  generate
+    if (SIGNED1 == 1) begin : in1_is_signed
+      assign in1_ext = {{IN1_PAD_LEFT{in1[BW_INPUT1-1]}}, in1, {IN1_PAD_RIGHT{1'b0}}};
+    end else begin : in1_is_unsigned
+      assign in1_ext = {{IN1_PAD_LEFT{1'b0}}, in1, {IN1_PAD_RIGHT{1'b0}}};
+    end
+  endgenerate
+
+  generate
+    if (INVERT1 == 1) begin : is_invert
+      assign out = (key) ? in0_ext[BW_OUT-1:0] : -in1_ext[BW_OUT-1:0];
+    end else begin : is_not_invert
+      assign out = (key) ? in0_ext[BW_OUT-1:0] : in1_ext[BW_OUT-1:0];
+    end
+  endgenerate
+
+endmodule

da4ml/codegen/rtl/verilog/source/negative.v

@@ -0,0 +1,31 @@
+`timescale 1ns / 1ps
+
+
+module negative #(
+    parameter BW_IN = 32,
+    parameter BW_OUT = 32,
+    parameter IN_SIGNED = 0
+) (
+    // verilator lint_off UNUSEDSIGNAL
+    input  [ BW_IN-1:0] in,
+    // verilator lint_off UNUSEDSIGNAL
+    output [BW_OUT-1:0] out
+);
+  /* verilator lint_off WIDTHTRUNC */
+  generate
+    if (BW_IN < BW_OUT) begin : in_is_smaller
+      wire [BW_OUT-1:0] in_ext;
+      if (IN_SIGNED == 1) begin : is_signed
+        assign in_ext = {{BW_OUT - BW_IN{in[BW_IN-1]}}, in};
+      end else begin : is_unsigned
+        assign in_ext = {{BW_OUT - BW_IN{1'b0}}, in};
+      end
+      assign out = -in_ext;
+    end else begin : in_is_bigger
+      wire [BW_IN-1:0] out_ext;
+      assign out_ext = -in;
+      assign out = out_ext[BW_OUT-1:0];
+    end
+  endgenerate
+  /* verilator lint_on WIDTHTRUNC */
+endmodule

da4ml/codegen/rtl/verilog/source/shift_adder.v

@@ -0,0 +1,59 @@
+`timescale 1ns / 1ps
+
+
+module shift_adder #(
+    parameter BW_INPUT0 = 32,
+    parameter BW_INPUT1 = 32,
+    parameter SIGNED0 = 0,
+    parameter SIGNED1 = 0,
+    parameter BW_OUT = 32,
+    parameter SHIFT1 = 0,
+    parameter IS_SUB = 0
+) (
+    input [BW_INPUT0-1:0] in0,
+    input [BW_INPUT1-1:0] in1,
+    output [BW_OUT-1:0] out
+);
+
+  localparam IN0_NEED_BITS = (SHIFT1 < 0) ? BW_INPUT0 - SHIFT1 : BW_INPUT0;
+  localparam IN1_NEED_BITS = (SHIFT1 > 0) ? BW_INPUT1 + SHIFT1 : BW_INPUT1;
+  localparam EXTRA_PAD = (SIGNED0 != SIGNED1) ? IS_SUB + 1 : IS_SUB + 0;
+  localparam BW_ADD = (IN0_NEED_BITS > IN1_NEED_BITS) ? IN0_NEED_BITS + EXTRA_PAD + 1 : IN1_NEED_BITS + EXTRA_PAD + 1;
+  localparam IN0_PAD_LEFT = (SHIFT1 < 0) ? BW_ADD - BW_INPUT0 + SHIFT1 : BW_ADD - BW_INPUT0;
+  localparam IN0_PAD_RIGHT = (SHIFT1 < 0) ? -SHIFT1 : 0;
+  localparam IN1_PAD_LEFT = (SHIFT1 > 0) ? BW_ADD - BW_INPUT1 - SHIFT1 : BW_ADD - BW_INPUT1;
+  localparam IN1_PAD_RIGHT = (SHIFT1 > 0) ? SHIFT1 : 0;
+
+  wire [BW_ADD-1:0] in0_ext;
+  wire [BW_ADD-1:0] in1_ext;
+
+  // verilator lint_off UNUSEDSIGNAL
+  wire [BW_ADD-1:0] accum;
+  // verilator lint_on UNUSEDSIGNAL
+
+  generate
+    if (SIGNED0 == 1) begin : in0_is_signed
+      assign in0_ext = {{IN0_PAD_LEFT{in0[BW_INPUT0-1]}}, in0, {IN0_PAD_RIGHT{1'b0}}};
+    end else begin : in0_is_unsigned
+      assign in0_ext = {{IN0_PAD_LEFT{1'b0}}, in0, {IN0_PAD_RIGHT{1'b0}}};
+    end
+  endgenerate
+
+  generate
+    if (SIGNED1 == 1) begin : in1_is_signed
+      assign in1_ext = {{IN1_PAD_LEFT{in1[BW_INPUT1-1]}}, in1, {IN1_PAD_RIGHT{1'b0}}};
+    end else begin : in1_is_unsigned
+      assign in1_ext = {{IN1_PAD_LEFT{1'b0}}, in1, {IN1_PAD_RIGHT{1'b0}}};
+    end
+  endgenerate
+
+  generate
+    if (IS_SUB == 1) begin : is_sub
+      assign accum = in0_ext - in1_ext;
+    end else begin : is_add
+      assign accum = in0_ext + in1_ext;
+    end
+  endgenerate
+  assign out = accum[BW_OUT-1:0];
+
+endmodule

da4ml/codegen/rtl/vhdl/__init__.py

@@ -0,0 +1,9 @@
+from .comb import comb_logic_gen
+from .io_wrapper import generate_io_wrapper
+from .pipeline import pipeline_logic_gen
+
+__all__ = [
+    'comb_logic_gen',
+    'generate_io_wrapper',
+    'pipeline_logic_gen',
+]