da4ml 0.5.1.post1__cp311-cp311-manylinux_2_24_x86_64.manylinux_2_28_x86_64.whl

da4ml/codegen/rtl/common_source/build_quartus_prj.tcl

@@ -0,0 +1,104 @@
+set project_name "$::env(PROJECT_NAME)"
+set device "$::env(DEVICE)"
+set source_type "$::env(SOURCE_TYPE)"
+
+set top_module "${project_name}"
+set output_dir "./output_${project_name}"
+
+file mkdir $output_dir
+file mkdir "${output_dir}/reports"
+
+project_new "${project_name}" -overwrite -revision "${project_name}"
+
+set_global_assignment -name FAMILY [lindex [split "${device}" "-"] 0]
+set_global_assignment -name DEVICE "${device}"
+
+if { "${source_type}" != "vhdl" && "${source_type}" != "verilog" } {
+    puts "Error: SOURCE_TYPE must be either 'vhdl' or 'verilog'."
+    exit 1
+}
+
+# Add source files based on type
+if { "${source_type}" == "vhdl" } {
+    set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
+
+    foreach file [glob -nocomplain "src/static/*.vhd"] {
+        set_global_assignment -name VHDL_FILE "${file}"
+    }
+
+    set_global_assignment -name VHDL_FILE "src/${project_name}.vhd"
+    foreach file [glob -nocomplain "src/${project_name}_stage*.vhd"] {
+        set_global_assignment -name VHDL_FILE "${file}"
+    }
+} else {
+    foreach file [glob -nocomplain "src/static/*.v"] {
+        set_global_assignment -name VERILOG_FILE "${file}"
+    }
+
+    set_global_assignment -name VERILOG_FILE "src/${project_name}.v"
+    foreach file [glob -nocomplain "src/${project_name}_stage*.v"] {
+        set_global_assignment -name VERILOG_FILE "${file}"
+    }
+}
+
+set mems [glob -nocomplain "src/memfiles/*.mem"]
+
+# VHDL only uses relative path to working dir apparently...
+if { "${source_type}" == "vhdl" } {
+    foreach f $mems {
+        file copy -force $f [file tail $f]
+    }
+    set mems [glob -nocomplain "*.mem"]
+}
+
+foreach f $mems {
+    set_global_assignment -name MIF_FILE "${f}"
+}
+
+# Add SDC constraint file if it exists
+if { [file exists "src/${project_name}.sdc"] } {
+    set_global_assignment -name SDC_FILE "${project_name}.sdc"
+}
+
+# Set top-level entity
+set_global_assignment -name TOP_LEVEL_ENTITY "${top_module}"
+
+# OOC
+load_package flow
+
+proc make_all_pins_virtual {} {
+    execute_module -tool map
+
+    set name_ids [get_names -filter * -node_type pin]
+
+    foreach_in_collection name_id $name_ids {
+        set pin_name [get_name_info -info full_path $name_id]
+        post_message "Making VIRTUAL_PIN assignment to $pin_name"
+        set_instance_assignment -to $pin_name -name VIRTUAL_PIN ON
+    }
+    export_assignments
+}
+
+make_all_pins_virtual
+
+# Config
+set_global_assignment -name OPTIMIZATION_MODE "HIGH PERFORMANCE EFFORT"
+set_global_assignment -name OPTIMIZATION_TECHNIQUE SPEED
+set_global_assignment -name AUTO_RESOURCE_SHARING ON
+set_global_assignment -name ALLOW_ANY_RAM_SIZE_FOR_RECOGNITION ON
+set_global_assignment -name ALLOW_ANY_ROM_SIZE_FOR_RECOGNITION ON
+set_global_assignment -name ALLOW_REGISTER_RETIMING ON
+
+set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS ON
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
+
+set_global_assignment -name FITTER_EFFORT "STANDARD FIT"
+
+set_global_assignment -name SYNTH_TIMING_DRIVEN_SYNTHESIS ON
+set_global_assignment -name SYNTHESIS_EFFORT AUTO
+set_global_assignment -name ADV_NETLIST_OPT_SYNTH_WYSIWYG_REMAP ON
+
+# Run!!!
+execute_flow -compile
+
+project_close

da4ml/codegen/rtl/common_source/build_vivado_prj.tcl

@@ -0,0 +1,111 @@
+set project_name "$::env(PROJECT_NAME)"
+set device "$::env(DEVICE)"
+set source_type "$::env(SOURCE_TYPE)"
+
+set top_module "${project_name}"
+set output_dir "./output_${project_name}"
+
+create_project $project_name "${output_dir}/$project_name" -force -part $device
+
+set_property DEFAULT_LIB work [current_project]
+
+if { $source_type != "vhdl" && $source_type != "verilog" } {
+    puts "Error: SOURCE_TYPE must be either 'vhdl' or 'verilog'."
+    exit 1
+}
+
+if { $source_type == "vhdl" } {
+    set_property TARGET_LANGUAGE VHDL [current_project]
+
+    set statis_files [glob -nocomplain "src/static/*.vhd"]
+    set top_file "src/${project_name}.vhd"
+    set stage_files [glob -nocomplain "src/${project_name}_stage*.vhd"]
+
+    read_vhdl -vhdl2008 $top_file $statis_files $stage_files
+
+} else {
+    set_property TARGET_LANGUAGE Verilog [current_project]
+
+    set statis_files [glob -nocomplain "src/static/*.v"]
+    set top_file "src/${project_name}.v"
+    set stage_files [glob -nocomplain "src/${project_name}_stage*.v"]
+
+    read_verilog $top_file $statis_files $stage_files
+
+}
+
+
+set mems [glob -nocomplain "src/memfiles/*.mem"]
+
+# VHDL only uses relative path to working dir apparently...
+if { $source_type == "vhdl" } {
+    foreach f $mems {
+        file copy -force $f [file tail $f]
+    }
+    set mems [glob -nocomplain "*.mem"]
+}
+
+add_files -fileset [current_fileset] $mems
+
+foreach f $mems {
+    set_property used_in_synthesis true [get_files $f]
+}
+
+# Add XDC constraint if it exists
+if { [file exists "src/${project_name}.xdc"] } {
+    read_xdc "src/${project_name}.xdc" -mode out_of_context
+}
+
+set_property top $top_module [current_fileset]
+
+file mkdir $output_dir
+file mkdir "${output_dir}/reports"
+
+# synth
+synth_design -top $top_module -mode out_of_context -global_retiming on \
+    -flatten_hierarchy full -resource_sharing auto -directive AreaOptimized_High
+
+write_checkpoint -force "${output_dir}/${project_name}_post_synth.dcp"
+
+report_timing_summary -file "${output_dir}/reports/${project_name}_post_synth_timing.rpt"
+report_power -file "${output_dir}/reports/${project_name}_post_synth_power.rpt"
+report_utilization -file "${output_dir}/reports/${project_name}_post_synth_util.rpt"
+
+# opt_design -directive ExploreSequentialArea
+opt_design -directive ExploreWithRemap
+
+report_design_analysis -congestion -file "${output_dir}/reports/${project_name}_post_opt_congestion.rpt"
+
+# place
+place_design -directive SSI_HighUtilSLRs -fanout_opt
+report_design_analysis -congestion -file "${output_dir}/reports/${project_name}_post_place_congestion_initial.rpt"
+
+phys_opt_design -directive AggressiveExplore
+write_checkpoint -force "${output_dir}/${project_name}_post_place.dcp"
+file delete -force "${output_dir}/${project_name}_post_synth.dcp"
+
+report_design_analysis -congestion -file "${output_dir}/reports/${project_name}_post_place_congestion_final.rpt"
+
+report_timing_summary -file "${output_dir}/reports/${project_name}_post_place_timing.rpt"
+report_utilization -hierarchical -file "${output_dir}/reports/${project_name}_post_place_util.rpt"
+
+# route
+route_design -directive NoTimingRelaxation
+write_checkpoint -force "${output_dir}/${project_name}_post_route.dcp"
+file delete -force "${output_dir}/${project_name}_post_place.dcp"
+
+
+report_timing_summary -file "${output_dir}/reports/${project_name}_post_route_timing.rpt"
+report_timing -sort_by group -max_paths 100 -path_type summary -file "${output_dir}/reports/${project_name}_post_route_timing_paths.rpt"
+report_clock_utilization -file "${output_dir}/reports/${project_name}_post_route_clock_util.rpt"
+report_utilization -file "${output_dir}/reports/${project_name}_post_route_util.rpt"
+report_power -file "${output_dir}/reports/${project_name}_post_route_power.rpt"
+report_drc -file "${output_dir}/reports/${project_name}_post_route_drc.rpt"
+
+report_utilization -format xml -hierarchical -file "${output_dir}/reports/${project_name}_post_route_util.xml"
+report_power -xpe "${output_dir}/reports/${project_name}_post_route_power.xml"
+
+# Generate Verilog netlist for simulation
+# write_verilog -force "${output_dir}/${project_name}_impl_netlist.v" -mode timesim -sdf_anno true
+
+puts "Implementation complete. Results saved in ${output_dir}"

da4ml/codegen/rtl/common_source/ioutil.hh

@@ -0,0 +1,124 @@
+#include "verilated.h"
+#include <cassert>
+#include <cstdint>
+#include <vector>
+template <size_t bw, size_t N_in> std::vector<int32_t> bitpack(const int32_t *values) {
+    static_assert(bw > 0 && bw <= 32, "Bit width must be between 1 and 32");
+
+    constexpr size_t total_bits = N_in * bw;
+    constexpr size_t result_size = (total_bits + 31) / 32;
+    std::vector<int32_t> result(result_size, 0);
+
+    constexpr uint32_t mask = (bw == 32) ? 0xFFFFFFFF : ((1U << bw) - 1);
+
+    size_t bit_pos = 0;
+    for (size_t i = 0; i < N_in; i++) {
+        int32_t val = values[i];
+        uint32_t bits = val & mask;
+
+        size_t result_idx = bit_pos / 32;
+        size_t offset = bit_pos % 32;
+
+        // base case
+        result[result_idx] |= (bits << offset);
+
+        // cross boundary case
+        if (offset + bw > 32 && result_idx + 1 < result.size()) {
+            result[result_idx + 1] |= (bits >> (32 - offset));
+        }
+
+        bit_pos += bw;
+    }
+
+    return result;
+}
+
+template <size_t bw, size_t N_out>
+std::vector<int32_t> bitunpack(const std::vector<int32_t> &packed) {
+    static_assert(bw > 0 && bw <= 32, "Bit width must be between 1 and 32");
+
+    constexpr size_t total_bits = N_out * bw;
+    constexpr size_t packed_size = (total_bits + 31) / 32;
+    assert(packed.size() == packed_size);
+
+    std::vector<int32_t> result(N_out, 0);
+
+    for (size_t i = 0; i < N_out; i++) {
+        size_t bit_pos = i * bw;
+        size_t packed_idx = bit_pos / 32;
+        size_t offset = bit_pos % 32;
+
+        // base case
+        size_t bw_v0 = std::min(bw, 32 - offset);
+        uint32_t mask = bw_v0 == 32 ? 0xFFFFFFFF : ((1U << bw_v0) - 1);
+        int32_t value = (packed[packed_idx] >> offset) & mask;
+
+        // cross boundary
+        if (offset + bw > 32) {
+            assert(packed_idx + 1 < packed.size());
+            size_t bw_v1 = offset + bw - 32;
+            uint32_t mask_v1 = ((1U << bw_v1) - 1);
+            uint32_t additional_bits = packed[packed_idx + 1] & mask_v1;
+            value |= (additional_bits << bw_v0);
+        }
+
+        result[i] = value;
+    }
+
+    return result;
+}
+
+template <size_t bits_in, typename inp_buf_t>
+std::enable_if_t<std::is_integral_v<inp_buf_t>, void>
+_write_input(inp_buf_t &inp_buf, const std::vector<int32_t> &input) {
+    assert(input.size() == (bits_in + 31) / 32);
+    inp_buf = input[0] & 0xFFFFFFFF;
+    if (bits_in > 32) {
+        inp_buf |= static_cast<int64_t>(input[1]) << 32;
+    }
+}
+
+template <size_t bits_in, size_t N_in>
+void _write_input(VlWide<N_in> &inp_buf, const std::vector<int32_t> &input) {
+    assert(input.size() == (bits_in + 31) / 32);
+    for (size_t i = 0; i < input.size(); ++i) {
+        inp_buf[i] = input[i];
+    }
+}
+
+template <size_t bits_out, typename out_buf_t>
+std::enable_if_t<std::is_integral_v<out_buf_t>, std::vector<int32_t>>
+_read_output(out_buf_t &out_buf) {
+    std::vector<int32_t> output((bits_out + 31) / 32);
+    output[0] = out_buf & 0xFFFFFFFF;
+    if (bits_out > 32) {
+        output[1] = (out_buf >> 32) & 0xFFFFFFFF;
+    }
+    return output;
+}
+
+template <size_t bits_out, size_t N_out>
+std::vector<int32_t> _read_output(VlWide<N_out> out_buf) {
+    std::vector<int32_t> output((bits_out + 31) / 32);
+    for (size_t i = 0; i < output.size(); ++i) {
+        output[i] = out_buf[i] & 0xFFFFFFFF;
+    }
+    return output;
+}
+
+template <size_t N, size_t max_bw, typename inp_buf_t>
+void write_input(inp_buf_t &inp_buf, const int32_t *c_inp) {
+    constexpr size_t bits_in = N * max_bw;
+    std::vector<int32_t> input = bitpack<max_bw, N>(c_inp);
+    _write_input<bits_in>(inp_buf, input);
+}
+
+template <size_t N, size_t max_bw, typename out_buf_t>
+void read_output(out_buf_t out_buf, int32_t *c_out) {
+    constexpr size_t bits_out = N * max_bw;
+    std::vector<int32_t> packed = _read_output<bits_out>(out_buf);
+    std::vector<int32_t> unpacked = bitunpack<max_bw, N>(packed);
+    for (size_t i = 0; i < N; ++i) {
+        c_out[i] = unpacked[i];
+    }
+}

da4ml/codegen/rtl/common_source/template.sdc

@@ -0,0 +1,27 @@
+set clock_period $::env(CLOCK_PERIOD)
+
+# Clock uncertainty as percentage of clock period
+set uncertainty_setup_r $::env(UNCERTAINITY_SETUP)
+set uncertainty_hold_r $::env(UNCERTAINITY_HOLD)
+set delay_max_r $::env(DELAY_MAX)
+set delay_min_r $::env(DELAY_MIN)
+
+# Calculate actual uncertainty values
+set uncertainty_setup [expr {$clock_period * $uncertainty_setup_r}]
+set uncertainty_hold [expr {$clock_period * $uncertainty_hold_r}]
+set delay_max [expr {$clock_period * $delay_max_r}]
+set delay_min [expr {$clock_period * $delay_min_r}]
+
+# Create clock with variable period
+create_clock -period $clock_period -name sys_clk [get_ports {clk}]
+
+# Input/Output constraints
+set_input_delay -clock sys_clk -max $delay_max [get_ports {model_inp[*]}]
+set_input_delay -clock sys_clk -min $delay_min [get_ports {model_inp[*]}]
+
+set_output_delay -clock sys_clk -max $delay_max [get_ports {model_out[*]}]
+set_output_delay -clock sys_clk -min $delay_min [get_ports {model_out[*]}]
+
+# Apply calculated uncertainty values
+set_clock_uncertainty -setup -to [get_clocks sys_clk] $uncertainty_setup
+set_clock_uncertainty -hold -to [get_clocks sys_clk] $uncertainty_hold

da4ml/codegen/rtl/common_source/template.xdc

@@ -0,0 +1,30 @@
+set clock_period $::env(CLOCK_PERIOD)
+
+# Clock uncertainty as percentage of clock period
+set uncertainty_setup_r $::env(UNCERTAINITY_SETUP)
+set uncertainty_hold_r $::env(UNCERTAINITY_HOLD)
+set delay_max_r $::env(DELAY_MAX)
+set delay_min_r $::env(DELAY_MIN)
+
+# Calculate actual uncertainty values
+set uncertainty_setup [expr {$clock_period * $uncertainty_setup_r}]
+set uncertainty_hold [expr {$clock_period * $uncertainty_hold_r}]
+set delay_max [expr {$clock_period * $delay_max_r}]
+set delay_min [expr {$clock_period * $delay_min_r}]
+
+# Create clock with variable period
+create_clock -period $clock_period -name sys_clk [get_ports {clk}]
+
+# Input/Output constraints
+set_input_delay -clock sys_clk -max $delay_max [get_ports {model_inp[*]}]
+set_input_delay -clock sys_clk -min $delay_min [get_ports {model_inp[*]}]
+
+set_output_delay -clock sys_clk -max $delay_max [get_ports {model_out[*]}]
+set_output_delay -clock sys_clk -min $delay_min [get_ports {model_out[*]}]
+
+# Apply calculated uncertainty values
+set_clock_uncertainty -setup $uncertainty_setup [get_clocks sys_clk]
+set_clock_uncertainty -hold $uncertainty_hold [get_clocks sys_clk]
+
+# Mark lut_rom to be implemented as distributed ROM (*rom_style = "distributed" *)
+set_property rom_style "distributed" [get_cells lut_rom]