da4ml 0.4.0__py3-none-any.whl → 0.5.0b0__py3-none-any.whl

da4ml/codegen/rtl/vhdl/comb.py

@@ -2,7 +2,8 @@ from math import ceil, log2
 
 import numpy as np
 
-from ....cmvm.types import Op, QInterval, Solution, _minimal_kif
+from ....cmvm.types import CombLogic, Op, QInterval, _minimal_kif
+from ..verilog.comb import get_table_name
 
 
 def make_neg(
@@ -16,7 +17,7 @@ def make_neg(
     _min, _max, step = ops[op.id0].qint
     bw_neg = max(sum(_minimal_kif(QInterval(-_max, -_min, step))), bw0)
     was_signed = int(_min < 0)
-    signals.append(f'signal v{op.id0}_neg : std_logic_vector({bw_neg-1} downto {0});')
+    signals.append(f'signal v{op.id0}_neg : std_logic_vector({bw_neg - 1} downto {0});')
     assigns.append(
         f'op_neg_{op.id0} : entity work.negative generic map (BW_IN => {bw0}, BW_OUT => {bw_neg}, IN_SIGNED => {was_signed}) port map (neg_in => {v0_name}, neg_out => v{op.id0}_neg);'
     )
@@ -25,7 +26,7 @@ def make_neg(
     return bw0, v0_name
 
 
-def ssa_gen(sol: Solution, neg_defined: set[int], print_latency: bool = False):
+def ssa_gen(sol: CombLogic, neg_defined: set[int], print_latency: bool = False):
     ops = sol.ops
     kifs = list(map(_minimal_kif, (op.qint for op in ops)))
     widths = list(map(sum, kifs))
@@ -46,10 +47,11 @@ def ssa_gen(sol: Solution, neg_defined: set[int], print_latency: bool = False):
         if bw == 0:
             continue
 
+        signals.append(f'signal v{i}:std_logic_vector({bw - 1} downto {0});')
+
         match op.opcode:
             case -1:  # Input marker
                 i0, i1 = inp_idxs[op.id0]
-                signals.append(f'signal v{i}:std_logic_vector({bw-1} downto {0});')
                 line = f'v{i} <= model_inp({i0} downto {i1});'
 
             case 0 | 1:  # Common a+/-b<<shift oprs
@@ -57,7 +59,6 @@ def ssa_gen(sol: Solution, neg_defined: set[int], print_latency: bool = False):
                 bw0, bw1 = widths[op.id0], widths[op.id1]
                 s0, f0, s1, f1 = int(p0[0]), p0[2], int(p1[0]), p1[2]
                 shift = op.data + f0 - f1
-                signals.append(f'signal v{i}:std_logic_vector({bw-1} downto {0});')
                 line = f'op_{i}:entity work.shift_adder generic map(BW_INPUT0=>{bw0},BW_INPUT1=>{bw1},SIGNED0=>{s0},SIGNED1=>{s1},BW_OUT=>{bw},SHIFT1=>{shift},IS_SUB=>{op.opcode}) port map(in0=>v{op.id0},in1=>v{op.id1},result=>v{i});'
 
             case 2 | -2:  # ReLU
@@ -68,12 +69,11 @@ def ssa_gen(sol: Solution, neg_defined: set[int], print_latency: bool = False):
                 if op.opcode == -2 and op.id0 not in neg_defined:
                     neg_defined.add(op.id0)
                     bw0, v0_name = make_neg(signals, assigns, op, ops, bw0, v0_name)
-                signals.append(f'signal v{i}:std_logic_vector({bw-1} downto {0});')
                 if ops[op.id0].qint.min < 0:
                     if bw > 1:
-                        line = f'v{i} <= {v0_name}({i0} downto {i1}) and ({bw - 1} downto 0 => not {v0_name}({bw0-1}));'
+                        line = f'v{i} <= {v0_name}({i0} downto {i1}) and ({bw - 1} downto 0 => not {v0_name}({bw0 - 1}));'
                     else:
-                        line = f'v{i}(0) <= {v0_name}(0) and (not {v0_name}({bw0-1}));'
+                        line = f'v{i}(0) <= {v0_name}(0) and (not {v0_name}({bw0 - 1}));'
                 else:
                     line = f'v{i} <= {v0_name}({i0} downto {i1});'
 
@@ -85,7 +85,6 @@ def ssa_gen(sol: Solution, neg_defined: set[int], print_latency: bool = False):
                 if op.opcode == -3 and op.id0 not in neg_defined:
                     neg_defined.add(op.id0)
                     bw0, v0_name = make_neg(signals, assigns, op, ops, bw0, v0_name)
-                signals.append(f'signal v{i}:std_logic_vector({bw-1} downto {0});')
                 line = f'v{i} <= {v0_name}({i0} downto {i1});'
 
             case 4:  # constant addition
@@ -95,14 +94,12 @@ def ssa_gen(sol: Solution, neg_defined: set[int], print_latency: bool = False):
                 bw0 = widths[op.id0]
                 s0 = int(kifs[op.id0][0])
                 shift = kifs[op.id0][2] - kifs[i][2]
-                signals.append(f'signal v{i}:std_logic_vector({bw-1} downto {0});')
                 bin_val = format(mag, f'0{bw1}b')
                 line = f'op_{i}:entity work.shift_adder generic map(BW_INPUT0=>{bw0},BW_INPUT1=>{bw1},SIGNED0=>{s0},SIGNED1=>0,BW_OUT=>{bw},SHIFT1=>{shift},IS_SUB=>{sign}) port map(in0=>v{op.id0},in1=>"{bin_val}",result=>v{i});'
             case 5:  # constant
                 num = op.data
                 if num < 0:
                     num = 2**bw + num
-                signals.append(f'signal v{i}:std_logic_vector({bw-1} downto {0});')
                 bin_val = format(num, f'0{bw}b')
                 line = f'v{i} <= "{bin_val}";'
 
@@ -115,14 +112,23 @@ def ssa_gen(sol: Solution, neg_defined: set[int], print_latency: bool = False):
                 _shift = (op.data >> 32) & 0xFFFFFFFF
                 _shift = _shift if _shift < 0x80000000 else _shift - 0x100000000
                 shift = f0 - f1 + _shift
-                signals.append(f'signal v{i}:std_logic_vector({bw-1} downto {0});')
-                line = f'op_{i}:entity work.mux generic map(BW_INPUT0=>{bw0},BW_INPUT1=>{bw1},SIGNED0=>{s0},SIGNED1=>{s1},BW_OUT=>{bw},SHIFT1=>{shift},INVERT1=>{inv}) port map(key=>v{k}({bwk-1}),in0=>v{a},in1=>v{b},result=>v{i});'
+                v0, v1 = f'v{a}', f'v{b}'
+                if bw0 == 0:
+                    v0, bw0 = 'B"0"', 1
+                if bw1 == 0:
+                    v1, bw1 = 'B"0"', 1
+                line = f'op_{i}:entity work.mux generic map(BW_INPUT0=>{bw0},BW_INPUT1=>{bw1},SIGNED0=>{s0},SIGNED1=>{s1},BW_OUT=>{bw},SHIFT1=>{shift},INVERT1=>{inv}) port map(key=>v{k}({bwk - 1}),in0=>{v0},in1=>{v1},result=>v{i});'
+
             case 7:  # Multiplication
                 bw0, bw1 = widths[op.id0], widths[op.id1]
                 s0, s1 = int(kifs[op.id0][0]), int(kifs[op.id1][0])
-                signals.append(f'signal v{i}:std_logic_vector({bw-1} downto {0});')
                 line = f'op_{i}:entity work.multiplier generic map(BW_INPUT0=>{bw0},BW_INPUT1=>{bw1},SIGNED0=>{s0},SIGNED1=>{s1},BW_OUT=>{bw}) port map(in0=>v{op.id0},in1=>v{op.id1},result=>v{i});'
 
+            case 8:  # Lookup Table
+                name = get_table_name(sol, op)
+                bw0 = widths[op.id0]
+                line = f'op_{i}:entity work.lookup_table generic map(BW_IN=>{bw0},BW_OUT=>{bw},MEM_FILE=>"{name}") port map(inp=>v{op.id0},outp=>v{i});'
+
             case _:
                 raise ValueError(f'Unknown opcode {op.opcode} for operation {i} ({op})')
 
@@ -132,7 +138,7 @@ def ssa_gen(sol: Solution, neg_defined: set[int], print_latency: bool = False):
     return signals, assigns
 
 
-def output_gen(sol: Solution, neg_defined: set[int]):
+def output_gen(sol: CombLogic, neg_defined: set[int]):
     assigns = []
     signals = []
     widths = list(map(sum, map(_minimal_kif, sol.out_qint)))
@@ -150,17 +156,17 @@ def output_gen(sol: Solution, neg_defined: set[int]):
                 neg_defined.add(idx)
                 bw0 = sum(_minimal_kif(sol.ops[idx].qint))
                 was_signed = int(_minimal_kif(sol.ops[idx].qint)[0])
-                signals.append(f'signal v{idx}_neg:std_logic_vector({bw-1} downto {0});')
+                signals.append(f'signal v{idx}_neg:std_logic_vector({bw - 1} downto {0});')
                 assigns.append(
                     f'op_neg_{idx}:entity work.negative generic map(BW_IN=>{bw0},BW_OUT=>{bw},IN_SIGNED=>{was_signed}) port map(neg_in=>v{idx},neg_out=>v{idx}_neg);'
                 )
-            assigns.append(f'model_out({i0} downto {i1}) <= v{idx}_neg({bw-1} downto {0});')
+            assigns.append(f'model_out({i0} downto {i1}) <= v{idx}_neg({bw - 1} downto {0});')
         else:
-            assigns.append(f'model_out({i0} downto {i1}) <= v{idx}({bw-1} downto {0});')
+            assigns.append(f'model_out({i0} downto {i1}) <= v{idx}({bw - 1} downto {0});')
     return signals, assigns
 
 
-def comb_logic_gen(sol: Solution, fn_name: str, print_latency: bool = False, timescale: str | None = None):
+def comb_logic_gen(sol: CombLogic, fn_name: str, print_latency: bool = False, timescale: str | None = None):
     inp_bits = sum(map(sum, map(_minimal_kif, sol.inp_qint)))
     out_bits = sum(map(sum, map(_minimal_kif, sol.out_qint)))
 
@@ -174,8 +180,8 @@ use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
 entity {fn_name} is port(
-    model_inp:in std_logic_vector({inp_bits-1} downto {0});
-    model_out:out std_logic_vector({out_bits-1} downto {0})
+    model_inp:in std_logic_vector({inp_bits - 1} downto {0});
+    model_out:out std_logic_vector({out_bits - 1} downto {0})
 );
 end entity {fn_name};
 

da4ml/codegen/rtl/vhdl/io_wrapper.py

@@ -1,6 +1,6 @@
 from itertools import accumulate
 
-from ....cmvm.types import CascadedSolution, QInterval, Solution, _minimal_kif
+from ....cmvm.types import CombLogic, Pipeline, QInterval, _minimal_kif
 
 
 def _loc(i: int, j: int):
@@ -63,26 +63,26 @@ def hetero_io_map(qints: list[QInterval], merge: bool = False):
     return regular, hetero, pads, (width_regular, width_packed)
 
 
-def generate_io_wrapper(sol: Solution | CascadedSolution, module_name: str, pipelined: bool = False):
+def generate_io_wrapper(sol: CombLogic | Pipeline, module_name: str, pipelined: bool = False):
     reg_in, het_in, _, shape_in = hetero_io_map(sol.inp_qint, merge=True)
     reg_out, het_out, pad_out, shape_out = hetero_io_map(sol.out_qint, merge=True)
 
     w_reg_in, w_het_in = shape_in
     w_reg_out, w_het_out = shape_out
 
-    inp_assignment = [f'packed_inp{_loc(ih,jh)} <= model_inp{_loc(ir,jr)};' for (ih, jh), (ir, jr) in zip(het_in, reg_in)]
+    inp_assignment = [f'packed_inp{_loc(ih, jh)} <= model_inp{_loc(ir, jr)};' for (ih, jh), (ir, jr) in zip(het_in, reg_in)]
     _out_assignment: list[tuple[int, str]] = []
 
     for i, ((ih, jh), (ir, jr)) in enumerate(zip(het_out, reg_out)):
         if ih == jh - 1:
             continue
-        _out_assignment.append((ih, f'model_out{_loc(ir,jr)} <= packed_out{_loc(ih,jh)};'))
+        _out_assignment.append((ih, f'model_out{_loc(ir, jr)} <= packed_out{_loc(ih, jh)};'))
 
     for i, (i, j, copy_from) in enumerate(pad_out):
         n_bit = i - j + 1
         value = "'0'" if copy_from == -1 else f'packed_out({copy_from})'
         pad = f'(others => {value})' if n_bit > 1 else value
-        _out_assignment.append((i, f'model_out{_loc(i,j)} <= {pad};'))
+        _out_assignment.append((i, f'model_out{_loc(i, j)} <= {pad};'))
     _out_assignment.sort(key=lambda x: x[0])
     out_assignment = [v for _, v in _out_assignment]
 
@@ -97,14 +97,14 @@ def generate_io_wrapper(sol: Solution | CascadedSolution, module_name: str, pipe
     return f"""library ieee;
 use ieee.std_logic_1164.all;
 entity {module_name}_wrapper is port({clk_and_rst_inp}
-    model_inp:in std_logic_vector({w_reg_in-1} downto {0});
-    model_out:out std_logic_vector({w_reg_out-1} downto {0})
+    model_inp:in std_logic_vector({w_reg_in - 1} downto {0});
+    model_out:out std_logic_vector({w_reg_out - 1} downto {0})
 );
 end entity {module_name}_wrapper;
 
 architecture rtl of {module_name}_wrapper is
-    signal packed_inp:std_logic_vector({w_het_in-1} downto {0});
-    signal packed_out:std_logic_vector({w_het_out-1} downto {0});
+    signal packed_inp:std_logic_vector({w_het_in - 1} downto {0});
+    signal packed_out:std_logic_vector({w_het_out - 1} downto {0});
 
 begin
     {inp_assignment_str}
@@ -120,12 +120,12 @@ end architecture rtl;
 """
 
 
-def binder_gen(csol: CascadedSolution | Solution, module_name: str, II: int = 1, latency_multiplier: int = 1):
+def binder_gen(csol: Pipeline | CombLogic, module_name: str, II: int = 1, latency_multiplier: int = 1):
     k_in, i_in, f_in = zip(*map(_minimal_kif, csol.inp_qint))
     k_out, i_out, f_out = zip(*map(_minimal_kif, csol.out_qint))
     max_inp_bw = max(k_in) + max(i_in) + max(f_in)
     max_out_bw = max(k_out) + max(i_out) + max(f_out)
-    if isinstance(csol, Solution):
+    if isinstance(csol, CombLogic):
         II = latency = 0
     else:
         latency = len(csol.solutions) * latency_multiplier

da4ml/codegen/rtl/vhdl/pipeline.py

@@ -1,9 +1,9 @@
-from ....cmvm.types import CascadedSolution, _minimal_kif
+from ....cmvm.types import Pipeline, _minimal_kif
 from .comb import comb_logic_gen
 
 
 def pipeline_logic_gen(
-    csol: CascadedSolution,
+    csol: Pipeline,
     name: str,
     print_latency=False,
     timescale: str | None = None,
@@ -13,10 +13,10 @@ def pipeline_logic_gen(
     inp_bits = [sum(map(sum, map(_minimal_kif, sol.inp_qint))) for sol in csol.solutions]
     out_bits = inp_bits[1:] + [sum(map(sum, map(_minimal_kif, csol.out_qint)))]
 
-    registers = [f'signal stage{i}_inp:std_logic_vector({width-1} downto 0);' for i, width in enumerate(inp_bits)]
+    registers = [f'signal stage{i}_inp:std_logic_vector({width - 1} downto 0);' for i, width in enumerate(inp_bits)]
     for i in range(0, register_layers - 1):
-        registers += [f'signal stage{j}_inp_copy{i}:std_logic_vector({width-1} downto 0);' for j, width in enumerate(inp_bits)]
-    wires = [f'signal stage{i}_out:std_logic_vector({width-1} downto 0);' for i, width in enumerate(out_bits)]
+        registers += [f'signal stage{j}_inp_copy{i}:std_logic_vector({width - 1} downto 0);' for j, width in enumerate(inp_bits)]
+    wires = [f'signal stage{i}_out:std_logic_vector({width - 1} downto 0);' for i, width in enumerate(out_bits)]
 
     comb_logic = [
         f'stage{i}:entity work.{name}_stage{i} port map(model_inp=>stage{i}_inp,model_out=>stage{i}_out);' for i in range(N)
@@ -24,19 +24,19 @@ def pipeline_logic_gen(
 
     if register_layers == 1:
         serial_logic = ['stage0_inp <= model_inp;']
-        serial_logic += [f'stage{i}_inp <= stage{i-1}_out;' for i in range(1, N)]
+        serial_logic += [f'stage{i}_inp <= stage{i - 1}_out;' for i in range(1, N)]
     else:
         serial_logic = ['stage0_inp_copy0 <= model_inp;']
         for j in range(1, register_layers - 1):
-            serial_logic.append(f'stage0_inp_copy{j} <= stage0_inp_copy{j-1};')
+            serial_logic.append(f'stage0_inp_copy{j} <= stage0_inp_copy{j - 1};')
         serial_logic.append(f'stage0_inp <= stage0_inp_copy{register_layers - 2};')
         for i in range(1, N):
-            serial_logic.append(f'stage{i}_inp_copy0 <= stage{i-1}_out;')
+            serial_logic.append(f'stage{i}_inp_copy0 <= stage{i - 1}_out;')
             for j in range(1, register_layers - 1):
-                serial_logic.append(f'stage{i}_inp_copy{j} <= stage{i}_inp_copy{j-1};')
+                serial_logic.append(f'stage{i}_inp_copy{j} <= stage{i}_inp_copy{j - 1};')
             serial_logic.append(f'stage{i}_inp <= stage{i}_inp_copy{register_layers - 2};')
 
-    serial_logic += [f'model_out <= stage{N-1}_out;']
+    serial_logic += [f'model_out <= stage{N - 1}_out;']
 
     blk = '\n    '
 
@@ -44,8 +44,8 @@ def pipeline_logic_gen(
 use ieee.std_logic_1164.all;
 entity {name} is port(
     clk:in std_logic;
-    model_inp:in std_logic_vector({inp_bits[0]-1} downto 0);
-    model_out:out std_logic_vector({out_bits[-1]-1} downto 0));
+    model_inp:in std_logic_vector({inp_bits[0] - 1} downto 0);
+    model_out:out std_logic_vector({out_bits[-1] - 1} downto 0));
 end entity {name};
 
 architecture rtl of {name} is

da4ml/codegen/rtl/vhdl/source/lookup_table.vhd

@@ -0,0 +1,52 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.textio.all;
+use ieee.std_logic_textio.all;
+
+entity lookup_table is
+	generic (
+		BW_IN    : positive := 8;
+		BW_OUT   : positive := 8;
+		MEM_FILE : string   := "whatever.mem"
+	);
+	port (
+		inp  : in  std_logic_vector(BW_IN - 1 downto 0);
+		outp : out std_logic_vector(BW_OUT - 1 downto 0)
+	);
+end entity lookup_table;
+
+architecture rtl of lookup_table is
+	subtype rom_index_t is natural range 0 to (2 ** BW_IN) - 1;
+	type rom_array_t is array (rom_index_t) of std_logic_vector(BW_OUT - 1 downto 0);
+
+	-- Load the ROM contents from an external hex file.
+	impure function init_rom return rom_array_t is
+		file rom_file : text;
+		variable rom_data : rom_array_t := (others => (others => '0'));
+		variable line_in  : line;
+		variable idx      : integer := 0;
+		variable data_val : std_logic_vector(BW_OUT - 1 downto 0);
+		variable temp_val : std_logic_vector(((BW_OUT + 3) / 4) * 4 - 1 downto 0);
+	begin
+		file_open(rom_file, MEM_FILE, read_mode);
+
+	while not endfile(rom_file) loop
+		exit when idx > rom_index_t'high;
+		readline(rom_file, line_in);
+		hread(line_in, temp_val);
+		rom_data(idx) := temp_val(BW_OUT - 1 downto 0);
+		idx := idx + 1;
+	end loop;
+
+	file_close(rom_file);
+	return rom_data;
+	end function init_rom;
+
+	signal ROM_CONTENTS : rom_array_t := init_rom;
+
+	attribute rom_style : string;
+	attribute rom_style of ROM_CONTENTS : signal is "distributed";
+begin
+	outp <= ROM_CONTENTS(to_integer(unsigned(inp)));
+end architecture rtl;

da4ml/converter/__init__.py

@@ -1,3 +1,59 @@
-from .hgq2 import trace_model
+from collections.abc import Callable
+from typing import Any, Literal, overload
+
+from ..cmvm.api import solver_options_t
+from ..trace import FixedVariableArray, HWConfig
 
 __all__ = ['trace_model']
+
+
+@overload
+def trace_model(  # type: ignore
+    model: Callable,
+    hwconf: HWConfig | tuple[int, int, int] = HWConfig(1, -1, -1),
+    solver_options: solver_options_t | None = None,
+    verbose: bool = False,
+    inputs: tuple[FixedVariableArray, ...] | FixedVariableArray | None = None,
+    dump: Literal[False] = False,
+) -> tuple[FixedVariableArray, FixedVariableArray]: ...
+
+
+@overload
+def trace_model(  # type: ignore
+    model: Callable,
+    hwconf: HWConfig | tuple[int, int, int] = HWConfig(1, -1, -1),
+    solver_options: solver_options_t | None = None,
+    verbose: bool = False,
+    inputs: tuple[FixedVariableArray, ...] | FixedVariableArray | None = None,
+    dump: Literal[True] = False,  # type: ignore
+) -> dict[str, FixedVariableArray]: ...
+
+
+def trace_model(  # type: ignore
+    model: Callable,
+    hwconf: HWConfig | tuple[int, int, int] = HWConfig(1, -1, -1),
+    solver_options: dict[str, Any] | None = None,
+    verbose: bool = False,
+    inputs: tuple[FixedVariableArray, ...] | None = None,
+    dump=False,
+):
+    hwconf = HWConfig(*hwconf) if isinstance(hwconf, tuple) else hwconf
+
+    module = type(model).__module__
+    if module.startswith('keras.'):
+        import keras
+
+        from .hgq2 import trace_model as keras_trace_model
+
+        assert isinstance(model, keras.Model)
+
+        return keras_trace_model(
+            model,
+            hwconf,
+            solver_options=solver_options,
+            verbose=verbose,
+            inputs=inputs,
+            dump=dump,
+        )
+    else:
+        raise ValueError(f'Unsupported model type: {type(model)}')

da4ml/converter/hgq2/parser.py

@@ -1,11 +1,12 @@
 from collections.abc import Sequence
 from dataclasses import dataclass
-from typing import Any, Literal, overload
+from typing import Any
 
 import keras
 import numpy as np
 from keras import KerasTensor, Operation
 
+from ...cmvm.api import solver_options_t
 from ...trace import FixedVariableArray, FixedVariableArrayInput, HWConfig, comb_trace
 from ...trace.fixed_variable import FixedVariable
 from .replica import _registry
@@ -116,32 +117,10 @@ def _apply_nn(
         return {k.name: v for k, v in tensor_map.items()}
 
 
-@overload
 def trace_model(  # type: ignore
     model: keras.Model,
-    hwconf: HWConfig = HWConfig(1, -1, -1),
-    solver_options: dict[str, Any] | None = None,
-    verbose: bool = False,
-    inputs: tuple[FixedVariableArray, ...] | FixedVariableArray | None = None,
-    dump: Literal[False] = False,
-) -> tuple[FixedVariableArray, FixedVariableArray]: ...
-
-
-@overload
-def trace_model(  # type: ignore
-    model: keras.Model,
-    hwconf: HWConfig = HWConfig(1, -1, -1),
-    solver_options: dict[str, Any] | None = None,
-    verbose: bool = False,
-    inputs: tuple[FixedVariableArray, ...] | FixedVariableArray | None = None,
-    dump: Literal[True] = False,  # type: ignore
-) -> dict[str, FixedVariableArray]: ...
-
-
-def trace_model(  # type: ignore
-    model: keras.Model,
-    hwconf: HWConfig = HWConfig(1, -1, -1),
-    solver_options: dict[str, Any] | None = None,
+    hwconf: HWConfig | tuple[int, int, int] = HWConfig(1, -1, -1),
+    solver_options: solver_options_t | None = None,
     verbose: bool = False,
     inputs: tuple[FixedVariableArray, ...] | None = None,
     dump=False,