da4ml 0.4.0__py3-none-any.whl → 0.5.0b0__py3-none-any.whl

da4ml/codegen/rtl/rtl_model.py

@@ -1,30 +1,45 @@
 import ctypes
+import json
 import os
 import re
 import shutil
 import subprocess
 import sys
+from collections.abc import Sequence
 from pathlib import Path
 from uuid import uuid4
 
 import numpy as np
 from numpy.typing import NDArray
 
-from ...cmvm.types import CascadedSolution, Solution, _minimal_kif
+from ...cmvm.types import CombLogic, Pipeline, _minimal_kif
 from ...trace.pipeline import to_pipeline
 from .. import rtl
 
 
-def get_io_kifs(sol: Solution | CascadedSolution):
+def get_io_kifs(sol: CombLogic | Pipeline):
     inp_kifs = tuple(zip(*map(_minimal_kif, sol.inp_qint)))
     out_kifs = tuple(zip(*map(_minimal_kif, sol.out_qint)))
     return np.array(inp_kifs, np.int8), np.array(out_kifs, np.int8)
 
 
+class at_path:
+    def __init__(self, path: str | Path):
+        self._path = Path(path)
+        self._orig_cwd = None
+
+    def __enter__(self):
+        self._orig_cwd = Path.cwd()
+        os.chdir(self._path)
+
+    def __exit__(self, exc_type, exc_value, traceback):
+        os.chdir(self._orig_cwd)  # type: ignore
+
+
 class RTLModel:
     def __init__(
         self,
-        solution: Solution | CascadedSolution,
+        solution: CombLogic | Pipeline,
         prj_name: str,
         path: str | Path,
         flavor: str = 'verilog',
@@ -51,9 +66,9 @@ class RTLModel:
 
         assert self._flavor in ('vhdl', 'verilog'), f'Unsupported flavor {flavor}, only vhdl and verilog are supported.'
 
-        self._pipe = solution if isinstance(solution, CascadedSolution) else None
+        self._pipe = solution if isinstance(solution, Pipeline) else None
         if latency_cutoff > 0 and self._pipe is None:
-            assert isinstance(solution, Solution)
+            assert isinstance(solution, CombLogic)
             self._pipe = to_pipeline(solution, latency_cutoff, verbose=False)
 
         if self._pipe is not None:
@@ -72,32 +87,46 @@ class RTLModel:
         else:  # verilog
             from .verilog import binder_gen, comb_logic_gen, generate_io_wrapper, pipeline_logic_gen
 
-        self._path.mkdir(parents=True, exist_ok=True)
+        from .verilog.comb import table_mem_gen
+
+        (self._path / 'src/static').mkdir(parents=True, exist_ok=True)
+        (self._path / 'sim').mkdir(exist_ok=True)
+        (self._path / 'model').mkdir(exist_ok=True)
+        (self._path / 'src/memfiles').mkdir(exist_ok=True)
         if self._pipe is not None:  # Pipeline
             # Main logic
             codes = pipeline_logic_gen(self._pipe, self._prj_name, self._print_latency, register_layers=self._register_layers)
+
+            # Table memory files
+            memfiles: dict[str, str] = {}
+            for comb in self._pipe.solutions:
+                memfiles.update(table_mem_gen(comb))
+
             for k, v in codes.items():
-                with open(self._path / f'{k}.{suffix}', 'w') as f:
+                with open(self._path / f'src/{k}.{suffix}', 'w') as f:
                     f.write(v)
 
-            # Build script
-            with open(self.__src_root / 'common_source/build_prj.tcl') as f:
-                tcl = f.read()
-            tcl = tcl.replace('${DEVICE}', self._part_name)
-            tcl = tcl.replace('${PROJECT_NAME}', self._prj_name)
-            with open(self._path / 'build_prj.tcl', 'w') as f:
-                f.write(tcl)
-
-            # XDC
-            with open(self.__src_root / 'common_source/template.xdc') as f:
-                xdc = f.read()
-            xdc = xdc.replace('${CLOCK_PERIOD}', str(self._clock_period))
-            xdc = xdc.replace('${UNCERTAINITY_SETUP}', str(self._clock_uncertainty))
-            xdc = xdc.replace('${UNCERTAINITY_HOLD}', str(self._clock_uncertainty))
-            xdc = xdc.replace('${DELAY_MAX}', str(self._io_delay_minmax[0]))
-            xdc = xdc.replace('${DELAY_MIN}', str(self._io_delay_minmax[1]))
-            with open(self._path / f'{self._prj_name}.xdc', 'w') as f:
-                f.write(xdc)
+            # Build scripts
+            for path in (self.__src_root).glob('common_source/build_*_prj.tcl'):
+                with open(path) as f:
+                    tcl = f.read()
+                tcl = tcl.replace('$::env(DEVICE)', self._part_name)
+                tcl = tcl.replace('$::env(PROJECT_NAME)', self._prj_name)
+                tcl = tcl.replace('$::env(SOURCE_TYPE)', flavor)
+                with open(self._path / path.name, 'w') as f:
+                    f.write(tcl)
+
+            # Timing constraint
+            for fmt in ('xdc', 'sdc'):
+                with open(self.__src_root / f'common_source/template.{fmt}') as f:
+                    constraint = f.read()
+                constraint = constraint.replace('$::env(CLOCK_PERIOD)', str(self._clock_period))
+                constraint = constraint.replace('$::env(UNCERTAINITY_SETUP)', str(self._clock_uncertainty))
+                constraint = constraint.replace('$::env(UNCERTAINITY_HOLD)', str(self._clock_uncertainty))
+                constraint = constraint.replace('$::env(DELAY_MAX)', str(self._io_delay_minmax[1]))
+                constraint = constraint.replace('$::env(DELAY_MIN)', str(self._io_delay_minmax[0]))
+                with open(self._path / f'src/{self._prj_name}.{fmt}', 'w') as f:
+                    f.write(constraint)
 
             # C++ binder w/ HDL wrapper for uniform bw
             binder = binder_gen(self._pipe, f'{self._prj_name}_wrapper', 1, self._register_layers)
@@ -105,34 +134,46 @@ class RTLModel:
             # Verilog IO wrapper (non-uniform bw to uniform one, clk passthrough)
             io_wrapper = generate_io_wrapper(self._pipe, self._prj_name, True)
 
-            self._pipe.save(self._path / 'pipeline.json')
+            self._pipe.save(self._path / 'model/pipeline.json')
         else:  # Comb
-            assert isinstance(self._solution, Solution)
+            assert isinstance(self._solution, CombLogic)
+
+            # Table memory files
+            memfiles = table_mem_gen(self._solution)
 
             # Main logic
             code = comb_logic_gen(self._solution, self._prj_name, self._print_latency, '`timescale 1ns/1ps')
-            with open(self._path / f'{self._prj_name}.{suffix}', 'w') as f:
+            with open(self._path / f'src/{self._prj_name}.{suffix}', 'w') as f:
                 f.write(code)
 
             # Verilog IO wrapper (non-uniform bw to uniform one, no clk)
             io_wrapper = generate_io_wrapper(self._solution, self._prj_name, False)
             binder = binder_gen(self._solution, f'{self._prj_name}_wrapper')
 
-        with open(self._path / f'{self._prj_name}_wrapper.{suffix}', 'w') as f:
+        # Write table memory files
+        for name, mem in memfiles.items():
+            with open(self._path / 'src/memfiles' / name, 'w') as f:
+                f.write(mem)
+
+        with open(self._path / f'src/{self._prj_name}_wrapper.{suffix}', 'w') as f:
             f.write(io_wrapper)
-        with open(self._path / f'{self._prj_name}_wrapper_binder.cc', 'w') as f:
+        with open(self._path / f'sim/{self._prj_name}_wrapper_binder.cc', 'w') as f:
             f.write(binder)
 
         # Common resource copy
-        for fname in self.__src_root.glob(f'{flavor}/source/*.{suffix}'):
-            shutil.copy(fname, self._path)
-
-        shutil.copy(self.__src_root / 'common_source/build_binder.mk', self._path)
-        shutil.copy(self.__src_root / 'common_source/ioutil.hh', self._path)
-        shutil.copy(self.__src_root / 'common_source/binder_util.hh', self._path)
-        self._solution.save(self._path / 'model.json')
-        with open(self._path / 'misc.json', 'w') as f:
-            f.write(f'{{"cost": {self._solution.cost}}}')
+        for path in self.__src_root.glob(f'{flavor}/source/*.{suffix}'):
+            shutil.copy(path, self._path / 'src/static')
+
+        shutil.copy(self.__src_root / 'common_source/build_binder.mk', self._path / 'sim')
+        shutil.copy(self.__src_root / 'common_source/ioutil.hh', self._path / 'sim')
+        shutil.copy(self.__src_root / 'common_source/binder_util.hh', self._path / 'sim')
+        self._solution.save(self._path / 'model/comb.json')
+        with open(self._path / 'metadata.json', 'w') as f:
+            misc = {'cost': self._solution.cost}
+            if self._pipe is not None:
+                misc['latency'] = len(self._pipe[0])
+                misc['reg_bits'] = self._pipe.reg_bits
+            f.write(json.dumps(misc))
 
     def _compile(self, verbose=False, openmp=True, nproc=None, o3: bool = False, clean=True):
         """Same as compile, but will not write to the library
@@ -149,7 +190,7 @@ class RTLModel:
         o3 : bool | None, optional
             Turn on -O3 flag, by default False
         clean : bool, optional
-            Remove obsolete shared object files, by default True
+            Remove obsolete shared object files and `obj_dir`, by default True
 
         Raises
         ------
@@ -169,18 +210,21 @@ class RTLModel:
         if o3:
             args.append('fast')
 
-        if clean is not False:
+        if clean:
             m = re.compile(r'^lib.*[0-9a-f]{8}-[0-9a-f]{4}-[0-9a-f]{4}-[0-9a-f]{4}-[0-9a-f]{12}\.so$')
-            for p in self._path.iterdir():
+            for p in (self._path / 'sim').iterdir():
                 if not p.is_dir() and m.match(p.name):
                     p.unlink()
-        if clean:
             subprocess.run(
-                ['make', '-f', 'build_binder.mk', 'clean'], env=env, cwd=self._path, check=True, capture_output=not verbose
+                ['make', '-f', 'build_binder.mk', 'clean'],
+                env=env,
+                cwd=self._path / 'sim',
+                check=True,
+                capture_output=not verbose,
             )
 
         try:
-            r = subprocess.run(args, env=env, check=True, cwd=self._path, capture_output=not verbose)
+            r = subprocess.run(args, env=env, check=True, cwd=self._path / 'sim', capture_output=not verbose)
         except subprocess.CalledProcessError as e:
             print(e.stderr.decode(), file=sys.stderr)
             print(e.stdout.decode(), file=sys.stdout)
@@ -190,18 +234,21 @@ class RTLModel:
             print(r.stdout.decode(), file=sys.stderr)
             raise RuntimeError('Compilation failed!!')
 
+        if clean:
+            subprocess.run(['rm', '-rf', 'obj_dir'], cwd=self._path / 'sim', check=True, capture_output=not verbose)
+
         self._load_lib(self._uuid)
 
     def _load_lib(self, uuid: str | None = None):
         uuid = uuid if uuid is not None else self._uuid
         if uuid is None:
             # load .so if there is only one, otherwise raise an error
-            libs = list(self._path.glob(f'lib{self._prj_name}_wrapper_*.so'))
+            libs = list(self._path.glob(f'sim/lib{self._prj_name}_wrapper_*.so'))
             if len(libs) == 0:
                 raise RuntimeError(f'Cannot load library, found {len(libs)} libraries in {self._path}')
             uuid = libs[0].name.split('_')[-1].split('.', 1)[0]
         self._uuid = uuid
-        lib_path = self._path / f'lib{self._prj_name}_wrapper_{uuid}.so'
+        lib_path = self._path / f'sim/lib{self._prj_name}_wrapper_{uuid}.so'
         if not lib_path.exists():
             raise RuntimeError(f'Library {lib_path} does not exist')
         self._lib = ctypes.CDLL(str(lib_path))
@@ -221,7 +268,7 @@ class RTLModel:
         o3 : bool | None, optional
             Turn on -O3 flag, by default False
         clean : bool, optional
-            Remove obsolete shared object files, by default True
+            Remove obsolete shared object files and `obj_dir`, by default True
 
         Raises
         ------
@@ -231,12 +278,12 @@ class RTLModel:
         self.write()
         self._compile(verbose=verbose, openmp=openmp, nproc=nproc, o3=o3, clean=clean)
 
-    def predict(self, data: NDArray[np.floating]) -> NDArray[np.float32]:
+    def predict(self, data: NDArray[np.floating] | Sequence[NDArray[np.floating]]) -> NDArray[np.float32]:
         """Run the model on the input data.
 
         Parameters
         ----------
-        data : NDArray[np.floating]
+        data : NDArray[np.floating]|Sequence[NDArray[np.floating]]
             Input data to the model. The shape is ignored, and the number of samples is
             determined by the size of the data.
 
@@ -246,6 +293,9 @@ class RTLModel:
             Output of the model in shape (n_samples, output_size).
         """
 
+        if isinstance(data, Sequence):
+            data = np.concatenate([a.reshape(a.shape[0], -1) for a in data], axis=-1)
+
         assert self._lib is not None, 'Library not loaded, call .compile() first.'
         inp_size, out_size = self._solution.shape
 
@@ -266,7 +316,9 @@ class RTLModel:
 
         inp_buf = inp_data.ctypes.data_as(ctypes.POINTER(ctypes.c_int32))
         out_buf = out_data.ctypes.data_as(ctypes.POINTER(ctypes.c_int32))
-        self._lib.inference(inp_buf, out_buf, n_sample)
+
+        with at_path(self._path / 'src/memfiles'):
+            self._lib.inference(inp_buf, out_buf, n_sample)
 
         # Unscale the output int32 to recover fp values
         k, i, f = np.max(k_out), np.max(i_out), np.max(f_out)
@@ -307,7 +359,7 @@ Estimated cost: {cost} LUTs"""
 class VerilogModel(RTLModel):
     def __init__(
         self,
-        solution: Solution | CascadedSolution,
+        solution: CombLogic | Pipeline,
         prj_name: str,
         path: str | Path,
         latency_cutoff: float = -1,
@@ -336,7 +388,7 @@ class VerilogModel(RTLModel):
 class VHDLModel(RTLModel):
     def __init__(
         self,
-        solution: Solution | CascadedSolution,
+        solution: CombLogic | Pipeline,
         prj_name: str,
         path: str | Path,
         latency_cutoff: float = -1,

da4ml/codegen/rtl/verilog/__init__.py

@@ -1,9 +1,10 @@
-from .comb import comb_logic_gen
+from .comb import comb_logic_gen, table_mem_gen
 from .io_wrapper import binder_gen, generate_io_wrapper
 from .pipeline import pipeline_logic_gen
 
 __all__ = [
     'comb_logic_gen',
+    'table_mem_gen',
     'generate_io_wrapper',
     'pipeline_logic_gen',
     'binder_gen',

da4ml/codegen/rtl/verilog/comb.py

@@ -2,7 +2,7 @@ from math import ceil, log2
 
 import numpy as np
 
-from ....cmvm.types import Op, QInterval, Solution, _minimal_kif
+from ....cmvm.types import CombLogic, Op, QInterval, _minimal_kif
 
 
 def make_neg(
@@ -23,16 +23,35 @@ def make_neg(
     return bw0, v0_name
 
 
-def ssa_gen(sol: Solution, neg_defined: set[int], print_latency: bool = False):
+def gen_mem_file(sol: CombLogic, op: Op) -> str:
+    assert op.opcode == 8
+    assert sol.lookup_tables is not None
+    table = sol.lookup_tables[op.data]
+    width = sum(table.spec.out_kif)
+    ndigits = ceil(width / 4)
+    data = table.padded_table(sol.ops[op.id0].qint)
+    mem_lines = [f'{hex(value)[2:].upper().zfill(ndigits)}' for value in data & ((1 << width) - 1)]
+    return '\n'.join(mem_lines)
+
+
+def get_table_name(sol: CombLogic, op: Op) -> str:
+    assert sol.lookup_tables is not None
+    assert op.opcode == 8
+    qint_in = sol.ops[op.id0].qint
+    uuid = sol.lookup_tables[op.data].get_uuid(qint_in)
+    return f'lut_{uuid}.mem'
+
+
+def ssa_gen(sol: CombLogic, neg_defined: set[int], print_latency: bool = False) -> list[str]:
     ops = sol.ops
     kifs = list(map(_minimal_kif, (op.qint for op in ops)))
-    widths = list(map(sum, kifs))
+    widths: list[int] = list(map(sum, kifs))
     inp_kifs = [_minimal_kif(qint) for qint in sol.inp_qint]
     inp_widths = list(map(sum, inp_kifs))
     _inp_widths = np.cumsum([0] + inp_widths)
     inp_idxs = np.stack([_inp_widths[1:] - 1, _inp_widths[:-1]], axis=1)
 
-    lines = []
+    lines: list[str] = []
     ref_count = sol.ref_count
 
     for i, op in enumerate(ops):
@@ -84,6 +103,7 @@ def ssa_gen(sol: Solution, neg_defined: set[int], print_latency: bool = False):
                 if op.opcode == -3 and op.id0 not in neg_defined:
                     neg_defined.add(op.id0)
                     bw0, v0_name = make_neg(lines, op, ops, bw0, v0_name)
+
                 line = f'{_def} assign {v} = {v0_name}[{i0}:{i1}];'
 
             case 4:  # constant addition
@@ -93,9 +113,11 @@ def ssa_gen(sol: Solution, neg_defined: set[int], print_latency: bool = False):
                 bw0 = widths[op.id0]
                 s0 = int(kifs[op.id0][0])
                 v0 = f'v{op.id0}[{bw0 - 1}:0]'
-                v1 = f"'{bin(mag)[1:]}"
+                v1 = f"{bw1}'{bin(mag)[1:]}"
                 shift = kifs[op.id0][2] - kifs[i][2]
+
                 line = f'{_def} shift_adder #({bw0}, {bw1}, {s0}, 0, {bw}, {shift}, {sign}) op_{i} ({v0}, {v1}, {v});'
+
             case 5:  # constant
                 num = op.data
                 if num < 0:
@@ -112,8 +134,13 @@ def ssa_gen(sol: Solution, neg_defined: set[int], print_latency: bool = False):
                 _shift = _shift if _shift < 0x80000000 else _shift - 0x100000000
                 shift = f0 - f1 + _shift
                 vk, v0, v1 = f'v{k}[{bwk - 1}]', f'v{a}[{bw0 - 1}:0]', f'v{b}[{bw1 - 1}:0]'
+                if bw0 == 0:
+                    v0, bw0 = "1'b0", 1
+                if bw1 == 0:
+                    v1, bw1 = "1'b0", 1
 
                 line = f'{_def} mux #({bw0}, {bw1}, {s0}, {s1}, {bw}, {shift}, {inv}) op_{i} ({vk}, {v0}, {v1}, {v});'
+
             case 7:  # Multiplication
                 bw0, bw1 = widths[op.id0], widths[op.id1]  # width
                 s0, s1 = int(kifs[op.id0][0]), int(kifs[op.id1][0])
@@ -121,6 +148,12 @@ def ssa_gen(sol: Solution, neg_defined: set[int], print_latency: bool = False):
 
                 line = f'{_def} multiplier #({bw0}, {bw1}, {s0}, {s1}, {bw}) op_{i} ({v0}, {v1}, {v});'
 
+            case 8:  # Lookup Table
+                name = get_table_name(sol, op)
+                bw0 = widths[op.id0]
+
+                line = f'{_def} lookup_table #({bw0}, {bw}, "{name}") op_{i} (v{op.id0}, {v});'
+
             case _:
                 raise ValueError(f'Unknown opcode {op.opcode} for operation {i} ({op})')
 
@@ -130,7 +163,7 @@ def ssa_gen(sol: Solution, neg_defined: set[int], print_latency: bool = False):
     return lines
 
 
-def output_gen(sol: Solution, neg_defined: set[int]):
+def output_gen(sol: CombLogic, neg_defined: set[int]):
     lines = []
     widths = list(map(sum, map(_minimal_kif, sol.out_qint)))
     _widths = np.cumsum([0] + widths)
@@ -157,7 +190,7 @@ def output_gen(sol: Solution, neg_defined: set[int]):
     return lines
 
 
-def comb_logic_gen(sol: Solution, fn_name: str, print_latency: bool = False, timescale: str | None = None):
+def comb_logic_gen(sol: CombLogic, fn_name: str, print_latency: bool = False, timescale: str | None = None):
     inp_bits = sum(map(sum, map(_minimal_kif, sol.inp_qint)))
     out_bits = sum(map(sum, map(_minimal_kif, sol.out_qint)))
 
@@ -191,3 +224,10 @@ def comb_logic_gen(sol: Solution, fn_name: str, print_latency: bool = False, tim
     if timescale is not None:
         code = f'{timescale}\n\n{code}'
     return code
+
+
+def table_mem_gen(sol: CombLogic) -> dict[str, str]:
+    if not sol.lookup_tables:
+        return {}
+    mem_files = {get_table_name(sol, op): gen_mem_file(sol, op) for op in sol.ops if op.opcode == 8}
+    return mem_files

da4ml/codegen/rtl/verilog/io_wrapper.py

@@ -1,6 +1,6 @@
 from itertools import accumulate
 
-from ....cmvm.types import CascadedSolution, QInterval, Solution, _minimal_kif
+from ....cmvm.types import CombLogic, Pipeline, QInterval, _minimal_kif
 
 
 def hetero_io_map(qints: list[QInterval], merge: bool = False):
@@ -59,7 +59,7 @@ def hetero_io_map(qints: list[QInterval], merge: bool = False):
     return regular, hetero, pads, (width_regular, width_packed)
 
 
-def generate_io_wrapper(sol: Solution | CascadedSolution, module_name: str, pipelined: bool = False):
+def generate_io_wrapper(sol: CombLogic | Pipeline, module_name: str, pipelined: bool = False):
     reg_in, het_in, _, shape_in = hetero_io_map(sol.inp_qint, merge=True)
     reg_out, het_out, pad_out, shape_out = hetero_io_map(sol.out_qint, merge=True)
 
@@ -113,12 +113,12 @@ endmodule
 """
 
 
-def binder_gen(csol: CascadedSolution | Solution, module_name: str, II: int = 1, latency_multiplier: int = 1):
+def binder_gen(csol: Pipeline | CombLogic, module_name: str, II: int = 1, latency_multiplier: int = 1):
     k_in, i_in, f_in = zip(*map(_minimal_kif, csol.inp_qint))
     k_out, i_out, f_out = zip(*map(_minimal_kif, csol.out_qint))
     max_inp_bw = max(k_in) + max(i_in) + max(f_in)
     max_out_bw = max(k_out) + max(i_out) + max(f_out)
-    if isinstance(csol, Solution):
+    if isinstance(csol, CombLogic):
         II = latency = 0
     else:
         latency = len(csol.solutions) * latency_multiplier

da4ml/codegen/rtl/verilog/pipeline.py

@@ -1,9 +1,9 @@
-from ....cmvm.types import CascadedSolution, _minimal_kif
+from ....cmvm.types import Pipeline, _minimal_kif
 from .comb import comb_logic_gen
 
 
 def pipeline_logic_gen(
-    csol: CascadedSolution,
+    csol: Pipeline,
     name: str,
     print_latency=False,
     timescale: str | None = '`timescale 1 ns / 1 ps',
@@ -13,36 +13,36 @@ def pipeline_logic_gen(
     inp_bits = [sum(map(sum, map(_minimal_kif, sol.inp_qint))) for sol in csol.solutions]
     out_bits = inp_bits[1:] + [sum(map(sum, map(_minimal_kif, csol.out_qint)))]
 
-    registers = [f'reg [{width-1}:0] stage{i}_inp;' for i, width in enumerate(inp_bits)]
+    registers = [f'reg [{width - 1}:0] stage{i}_inp;' for i, width in enumerate(inp_bits)]
     for i in range(0, register_layers - 1):
-        registers += [f'reg [{width-1}:0] stage{j}_inp_copy{i};' for j, width in enumerate(inp_bits)]
-    wires = [f'wire [{width-1}:0] stage{i}_out;' for i, width in enumerate(out_bits)]
+        registers += [f'reg [{width - 1}:0] stage{j}_inp_copy{i};' for j, width in enumerate(inp_bits)]
+    wires = [f'wire [{width - 1}:0] stage{i}_out;' for i, width in enumerate(out_bits)]
 
     comb_logic = [f'{name}_stage{i} stage{i} (.model_inp(stage{i}_inp), .model_out(stage{i}_out));' for i in range(N)]
 
     if register_layers == 1:
         serial_logic = ['stage0_inp <= model_inp;']
-        serial_logic += [f'stage{i}_inp <= stage{i-1}_out;' for i in range(1, N)]
+        serial_logic += [f'stage{i}_inp <= stage{i - 1}_out;' for i in range(1, N)]
     else:
         serial_logic = ['stage0_inp_copy0 <= model_inp;']
         for j in range(1, register_layers - 1):
-            serial_logic.append(f'stage0_inp_copy{j} <= stage0_inp_copy{j-1};')
+            serial_logic.append(f'stage0_inp_copy{j} <= stage0_inp_copy{j - 1};')
         serial_logic.append(f'stage0_inp <= stage0_inp_copy{register_layers - 2};')
         for i in range(1, N):
-            serial_logic.append(f'stage{i}_inp_copy0 <= stage{i-1}_out;')
+            serial_logic.append(f'stage{i}_inp_copy0 <= stage{i - 1}_out;')
             for j in range(1, register_layers - 1):
-                serial_logic.append(f'stage{i}_inp_copy{j} <= stage{i}_inp_copy{j-1};')
+                serial_logic.append(f'stage{i}_inp_copy{j} <= stage{i}_inp_copy{j - 1};')
             serial_logic.append(f'stage{i}_inp <= stage{i}_inp_copy{register_layers - 2};')
 
-    serial_logic += [f'model_out <= stage{N-1}_out;']
+    serial_logic += [f'model_out <= stage{N - 1}_out;']
 
     sep0 = '\n    '
     sep1 = '\n        '
 
     module = f"""module {name} (
     input clk,
-    input [{inp_bits[0]-1}:0] model_inp,
-    output reg [{out_bits[-1]-1}:0] model_out
+    input [{inp_bits[0] - 1}:0] model_inp,
+    output reg [{out_bits[-1] - 1}:0] model_out
 );
 
     {sep0.join(registers)}

da4ml/codegen/rtl/verilog/source/lookup_table.v

@@ -0,0 +1,27 @@
+`timescale 1ns / 1ps
+
+
+module lookup_table #(
+    parameter BW_IN = 8,
+    parameter BW_OUT = 8,
+    parameter MEM_FILE = "whatever.mem"
+) (
+    input [BW_IN-1:0] in,
+    output [BW_OUT-1:0] out
+);
+
+  (*rom_style = "distributed" *)
+  reg [BW_OUT-1:0] lut_rom [0:(1<<BW_IN)-1];
+  reg [BW_OUT-1:0] readout;
+
+  initial begin
+    $readmemh(MEM_FILE, lut_rom);
+  end
+
+  assign out[BW_OUT-1:0] = readout[BW_OUT-1:0];
+
+  always @(*) begin
+    readout = lut_rom[in];
+  end
+
+endmodule