da4ml 0.3.2__py3-none-any.whl → 0.4.0__py3-none-any.whl

da4ml/codegen/rtl/vhdl/source/multiplier.vhd

@@ -0,0 +1,40 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity multiplier is
+    generic (
+        BW_INPUT0 : integer := 32;
+        BW_INPUT1 : integer := 32;
+        SIGNED0   : integer := 0;
+        SIGNED1   : integer := 0;
+        BW_OUT    : integer := 32
+    );
+    port (
+        in0 : in  std_logic_vector(BW_INPUT0-1 downto 0);
+        in1 : in  std_logic_vector(BW_INPUT1-1 downto 0);
+        result : out std_logic_vector(BW_OUT-1 downto 0)
+    );
+end entity multiplier;
+
+architecture rtl of multiplier is
+    constant BW_BUF : integer := BW_INPUT0 + BW_INPUT1;
+    signal mult_buffer : std_logic_vector(BW_BUF-1 downto 0);
+begin
+
+    gen_mult : process(in0, in1)
+    begin
+        if SIGNED0 = 1 and SIGNED1 = 1 then
+            mult_buffer <= std_logic_vector(resize(signed(in0) * signed(in1), BW_BUF));
+        elsif SIGNED0 = 1 and SIGNED1 = 0 then
+            mult_buffer <= std_logic_vector(resize(signed(in0) * signed('0' & in1), BW_BUF));
+        elsif SIGNED0 = 0 and SIGNED1 = 1 then
+            mult_buffer <= std_logic_vector(resize(signed('0' & in0) * signed(in1), BW_BUF));
+        else
+            mult_buffer <= std_logic_vector(resize(unsigned(in0) * unsigned(in1), BW_BUF));
+        end if;
+    end process;
+
+    result <= mult_buffer(BW_OUT-1 downto 0);
+
+end architecture rtl;

da4ml/codegen/rtl/vhdl/source/mux.vhd

@@ -0,0 +1,102 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity mux is
+    generic (
+        BW_INPUT0 : integer := 32;
+        BW_INPUT1 : integer := 32;
+        SIGNED0   : integer := 0;
+        SIGNED1   : integer := 0;
+        BW_OUT    : integer := 32;
+        SHIFT1    : integer := 0;
+        INVERT1   : integer := 0
+    );
+    port (
+        key : in  std_logic;
+        in0 : in  std_logic_vector(BW_INPUT0-1 downto 0);
+        in1 : in  std_logic_vector(BW_INPUT1-1 downto 0);
+        result : out std_logic_vector(BW_OUT-1 downto 0)
+    );
+end entity mux;
+
+architecture rtl of mux is
+    function max(L, R: integer) return integer is
+    begin
+        if L > R then
+            return L;
+        else
+            return R;
+        end if;
+    end function;
+
+    function if_then_else(cond: boolean; val_true: integer; val_false: integer) return integer is
+    begin
+        if cond then
+            return val_true;
+        else
+            return val_false;
+        end if;
+    end function;
+
+    constant IN0_NEED_BITS : integer := if_then_else(SHIFT1 < 0, BW_INPUT0 - SHIFT1, BW_INPUT0);
+    constant IN1_NEED_BITS : integer := if_then_else(SHIFT1 > 0, BW_INPUT1 + SHIFT1, BW_INPUT1);
+    constant EXTRA_PAD : integer := if_then_else(SIGNED0 /= SIGNED1, INVERT1 + 1, INVERT1);
+    constant BW_BUF : integer := max(IN0_NEED_BITS, IN1_NEED_BITS) + EXTRA_PAD;
+
+    signal in0_ext : std_logic_vector(BW_BUF-1 downto 0);
+    signal in1_ext : std_logic_vector(BW_BUF-1 downto 0);
+    signal out_buf : std_logic_vector(BW_BUF-1 downto 0);
+
+begin
+
+    -- Extension and shifting for input 0
+    gen_in0_shift_neg: if SHIFT1 < 0 generate
+        gen_in0_signed: if SIGNED0 = 1 generate
+            in0_ext <= std_logic_vector(resize(signed(in0), BW_BUF)) sll (-SHIFT1);
+        end generate;
+        gen_in0_unsigned: if SIGNED0 = 0 generate
+            in0_ext <= std_logic_vector(resize(unsigned(in0), BW_BUF)) sll (-SHIFT1);
+        end generate;
+    end generate;
+
+    gen_in0_shift_pos: if SHIFT1 >= 0 generate
+        gen_in0_signed: if SIGNED0 = 1 generate
+            in0_ext <= std_logic_vector(resize(signed(in0), BW_BUF));
+        end generate;
+        gen_in0_unsigned: if SIGNED0 = 0 generate
+            in0_ext <= std_logic_vector(resize(unsigned(in0), BW_BUF));
+        end generate;
+    end generate;
+
+    -- Extension and shifting for input 1
+    gen_in1_shift_pos: if SHIFT1 > 0 generate
+        gen_in1_signed: if SIGNED1 = 1 generate
+            in1_ext <= std_logic_vector(resize(signed(in1), BW_BUF)) sll SHIFT1;
+        end generate;
+        gen_in1_unsigned: if SIGNED1 = 0 generate
+            in1_ext <= std_logic_vector(resize(unsigned(in1), BW_BUF)) sll SHIFT1;
+        end generate;
+    end generate;
+
+    gen_in1_shift_neg: if SHIFT1 <= 0 generate
+        gen_in1_signed: if SIGNED1 = 1 generate
+            in1_ext <= std_logic_vector(resize(signed(in1), BW_BUF));
+        end generate;
+        gen_in1_unsigned: if SIGNED1 = 0 generate
+            in1_ext <= std_logic_vector(resize(unsigned(in1), BW_BUF));
+        end generate;
+    end generate;
+
+    -- Mux logic
+    gen_invert: if INVERT1 = 1 generate
+        out_buf <= in0_ext when key = '1' else std_logic_vector(-signed(in1_ext));
+    end generate;
+
+    gen_no_invert: if INVERT1 = 0 generate
+        out_buf <= in0_ext when key = '1' else in1_ext;
+    end generate;
+
+    result <= out_buf(BW_OUT-1 downto 0);
+
+end architecture rtl;

da4ml/codegen/rtl/vhdl/source/negative.vhd

@@ -0,0 +1,35 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity negative is
+    generic (
+        BW_IN     : integer := 32;
+        BW_OUT    : integer := 32;
+        IN_SIGNED : integer := 0
+    );
+    port (
+        neg_in  : in  std_logic_vector(BW_IN-1 downto 0);
+        neg_out : out std_logic_vector(BW_OUT-1 downto 0)
+    );
+end entity negative;
+
+architecture rtl of negative is
+    signal in_ext : std_logic_vector(BW_OUT-1 downto 0);
+begin
+
+    gen_lt : if BW_IN < BW_OUT generate
+        gen_signed : if IN_SIGNED = 1 generate
+            in_ext <= std_logic_vector(resize(signed(neg_in), BW_OUT));
+        end generate;
+        gen_unsigned : if IN_SIGNED = 0 generate
+            in_ext <= std_logic_vector(resize(unsigned(neg_in), BW_OUT));
+        end generate;
+        neg_out <= std_logic_vector(-signed(in_ext));
+    end generate;
+
+    gen_ge : if BW_IN >= BW_OUT generate
+        neg_out <= std_logic_vector(-signed(neg_in(BW_OUT-1 downto 0)));
+    end generate;
+
+end architecture rtl;

da4ml/codegen/rtl/vhdl/source/shift_adder.vhd

@@ -0,0 +1,101 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity shift_adder is
+    generic (
+        BW_INPUT0 : integer := 32;
+        BW_INPUT1 : integer := 32;
+        SIGNED0   : integer := 0;
+        SIGNED1   : integer := 0;
+        BW_OUT    : integer := 32;
+        SHIFT1    : integer := 0;
+        IS_SUB    : integer := 0
+    );
+    port (
+        in0 : in  std_logic_vector(BW_INPUT0-1 downto 0);
+        in1 : in  std_logic_vector(BW_INPUT1-1 downto 0);
+        result : out std_logic_vector(BW_OUT-1 downto 0)
+    );
+end entity shift_adder;
+
+architecture rtl of shift_adder is
+    function max(L, R: integer) return integer is
+    begin
+        if L > R then
+            return L;
+        else
+            return R;
+        end if;
+    end function;
+
+    function if_then_else(cond: boolean; val_true: integer; val_false: integer) return integer is
+    begin
+        if cond then
+            return val_true;
+        else
+            return val_false;
+        end if;
+    end function;
+
+    constant IN0_NEED_BITS : integer := if_then_else(SHIFT1 < 0, BW_INPUT0 - SHIFT1, BW_INPUT0);
+    constant IN1_NEED_BITS : integer := if_then_else(SHIFT1 > 0, BW_INPUT1 + SHIFT1, BW_INPUT1);
+    constant EXTRA_PAD     : integer := if_then_else(SIGNED0 /= SIGNED1, IS_SUB + 1, IS_SUB);
+    constant BW_ADD        : integer := max(IN0_NEED_BITS, IN1_NEED_BITS) + EXTRA_PAD + 1;
+
+    signal in0_ext : std_logic_vector(BW_ADD-1 downto 0);
+    signal in1_ext : std_logic_vector(BW_ADD-1 downto 0);
+    signal accum   : std_logic_vector(BW_ADD-1 downto 0);
+
+begin
+
+    -- Extension and shifting for input 0
+    gen_in0_shift_neg: if SHIFT1 < 0 generate
+        gen_in0_signed: if SIGNED0 = 1 generate
+            in0_ext <= std_logic_vector(resize(signed(in0), BW_ADD)) sll (-SHIFT1);
+        end generate;
+        gen_in0_unsigned: if SIGNED0 = 0 generate
+            in0_ext <= std_logic_vector(resize(unsigned(in0), BW_ADD)) sll (-SHIFT1);
+        end generate;
+    end generate;
+
+    gen_in0_shift_pos: if SHIFT1 >= 0 generate
+        gen_in0_signed: if SIGNED0 = 1 generate
+            in0_ext <= std_logic_vector(resize(signed(in0), BW_ADD));
+        end generate;
+        gen_in0_unsigned: if SIGNED0 = 0 generate
+            in0_ext <= std_logic_vector(resize(unsigned(in0), BW_ADD));
+        end generate;
+    end generate;
+
+    -- Extension and shifting for input 1
+    gen_in1_shift_pos: if SHIFT1 > 0 generate
+        gen_in1_signed: if SIGNED1 = 1 generate
+            in1_ext <= std_logic_vector(resize(signed(in1), BW_ADD)) sll SHIFT1;
+        end generate;
+        gen_in1_unsigned: if SIGNED1 = 0 generate
+            in1_ext <= std_logic_vector(resize(unsigned(in1), BW_ADD)) sll SHIFT1;
+        end generate;
+    end generate;
+
+    gen_in1_shift_neg: if SHIFT1 <= 0 generate
+        gen_in1_signed: if SIGNED1 = 1 generate
+            in1_ext <= std_logic_vector(resize(signed(in1), BW_ADD));
+        end generate;
+        gen_in1_unsigned: if SIGNED1 = 0 generate
+            in1_ext <= std_logic_vector(resize(unsigned(in1), BW_ADD));
+        end generate;
+    end generate;
+
+    -- Addition/subtraction logic
+    gen_sub: if IS_SUB = 1 generate
+        accum <= std_logic_vector(signed(in0_ext) - signed(in1_ext));
+    end generate;
+
+    gen_add: if IS_SUB = 0 generate
+        accum <= std_logic_vector(signed(in0_ext) + signed(in1_ext));
+    end generate;
+
+    result <= accum(BW_OUT-1 downto 0);
+
+end architecture rtl;

da4ml/codegen/rtl/vhdl/source/template.xdc

@@ -0,0 +1,32 @@
+set clock_period ${CLOCK_PERIOD}
+
+# Clock uncertainty as percentage of clock period
+set uncertainty_setup_r ${UNCERTAINITY_SETUP}
+set uncertainty_hold_r ${UNCERTAINITY_HOLD}
+set delay_max_r ${DELAY_MAX}
+set delay_min_r ${DELAY_MIN}
+
+# Calculate actual uncertainty values
+set uncertainty_setup [expr {$clock_period * $uncertainty_setup_r}]
+set uncertainty_hold [expr {$clock_period * $uncertainty_hold_r}]
+set delay_max [expr {$clock_period * $delay_max_r}]
+set delay_min [expr {$clock_period * $delay_min_r}]
+
+# Create clock with variable period
+create_clock -period $clock_period -name sys_clk [get_ports {clk}]
+
+# Input/Output constraints
+set_input_delay -clock sys_clk -max $delay_max [get_ports {inp[*]}]
+set_input_delay -clock sys_clk -min $delay_min [get_ports {inp[*]}]
+
+set_output_delay -clock sys_clk -max $delay_max [get_ports {out[*]}]
+set_output_delay -clock sys_clk -min $delay_min [get_ports {out[*]}]
+
+# Apply calculated uncertainty values
+set_clock_uncertainty -setup $uncertainty_setup [get_clocks sys_clk]
+set_clock_uncertainty -hold $uncertainty_hold [get_clocks sys_clk]
+
+set_property HD.CLK_SRC BUFG_X0Y0 [get_ports clk]
+
+set_property retiming_forward 1 [get_cells {stage[*]_inp}]
+set_property retiming_backward 1 [get_cells {stage[*]_inp}]

da4ml/converter/hgq2/parser.py

@@ -6,8 +6,8 @@ import keras
 import numpy as np
 from keras import KerasTensor, Operation
 
-from ...trace import FixedVariableArray, HWConfig, comb_trace
-from ...trace.fixed_variable_array import FixedVariableArrayInput
+from ...trace import FixedVariableArray, FixedVariableArrayInput, HWConfig, comb_trace
+from ...trace.fixed_variable import FixedVariable
 from .replica import _registry
 
 
@@ -55,6 +55,8 @@ def replace_tensors(tensor_map: dict[KerasTensor, FixedVariableArray], obj: Any)
 def _flatten_arr(args: Any) -> FixedVariableArray:
     if isinstance(args, FixedVariableArray):
         return np.ravel(args)  # type: ignore
+    if isinstance(args, FixedVariable):
+        return FixedVariableArray(np.array([args]))
     if not isinstance(args, Sequence):
         return None  # type: ignore
     args = [_flatten_arr(a) for a in args]

da4ml/trace/fixed_variable.py

@@ -265,6 +265,10 @@ class FixedVariable:
     def __sub__(self, other: 'FixedVariable|int|float|Decimal'):
         return self + (-other)
 
+    def __truediv__(self, other: 'int|float|Decimal'):
+        assert not isinstance(other, FixedVariable), 'Division by variable is not supported'
+        return self * (1 / other)
+
     def __mul__(self, other: 'FixedVariable|int|float|Decimal') -> 'FixedVariable':
         if other == 0:
             return FixedVariable(0, 0, 1, hwconf=self.hwconf, opr='const')

da4ml/trace/fixed_variable_array.py

@@ -164,6 +164,10 @@ class FixedVariableArray:
         latency: NDArray[np.floating] | float = 0.0,
         solver_options: dict[str, Any] | None = None,
     ):
+        mask = k + i + f <= 0
+        k = np.where(mask, 0, k)
+        i = np.where(mask, 0, i)
+        f = np.where(mask, 0, f)
         step = 2.0**-f
         _high = 2.0**i
         high, low = _high - step, -_high * k

da4ml/trace/ops/reduce_utils.py

@@ -99,7 +99,7 @@ def reduce(operator: Callable[[T, T], T], x: TA, axis: int | Sequence[int] | Non
     r = _arr.reshape(target_shape)  # type: ignore
 
     if isinstance(x, FixedVariableArray):
-        ret = FixedVariableArray(r, solver_config)
-        if ret.size == 1 and not keepdims:
-            return ret.ravel()[0]  # type: ignore
+        r = FixedVariableArray(r, solver_config)
+        if r.size == 1 and not keepdims:
+            return r.ravel()[0]  # type: ignore
     return r if r.size > 1 or keepdims else r.ravel()[0]  # type: ignore

{da4ml-0.3.2.dist-info → da4ml-0.4.0.dist-info}/METADATA

@@ -1,7 +1,7 @@
 Metadata-Version: 2.4
 Name: da4ml
-Version: 0.3.2
-Summary: Digital Arithmetic for Machine Learning
+Version: 0.4.0
+Summary: Distributed Arithmetic for Machine Learning
 Author-email: Chang Sun <chsun@cern.ch>
 License: GNU Lesser General Public License v3 (LGPLv3)
 Project-URL: repository, https://github.com/calad0i/da4ml

da4ml-0.4.0.dist-info/RECORD

@@ -0,0 +1,76 @@
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+da4ml/_version.py,sha256=2_0GUP7yBCXRus-qiJKxQD62z172WSs1sQ6DVpPsbmM,704
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+da4ml/cmvm/api.py,sha256=JpecMt6g8zutGh_uWT61_0iX8TuXct7-jq7N7HMIsgA,9626
+da4ml/cmvm/types.py,sha256=O8BuBZ2SyucxoXt_KbulAuHNgim7Ls3M6Ovw8prLgXM,21340
+da4ml/cmvm/core/__init__.py,sha256=bp2CXI4EOVOQSho1qwfusNs0RliZRt2dV0hZ33W_Kjo,7703
+da4ml/cmvm/core/indexers.py,sha256=QjXgvExS-B2abHTJPDG4NufMdMEflo1i6cUhFOgJpH4,2945
+da4ml/cmvm/core/state_opr.py,sha256=wLqO8qVuM2-qCE5LDeYJDNkUruIPHy63obsv4-x-aR8,8661
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+da4ml/codegen/__init__.py,sha256=ldMaaixWMxEpLS6skyAgpGCcIMVHdeRCNy57-JxGn3Y,161
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+da4ml/codegen/hls/source/vitis_bitshift.hh,sha256=u8wjT_cRn7bXcbC5pH3-rS76ekRbwv-VWAAdaP52-dw,765
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da4ml/codegen/cpp/__init__.py

@@ -1,4 +0,0 @@
-from .cpp_codegen import cpp_logic_and_bridge_gen
-from .hls_model import HLSModel
-
-__all__ = ['cpp_logic_and_bridge_gen', 'HLSModel']

da4ml/codegen/cpp/source/binder_util.hh

@@ -1,56 +0,0 @@
-#pragma once
-#include <cstddef>
-
-#ifdef _OPENMP
-#include <algorithm>
-#include <omp.h>
-constexpr bool _openmp = true;
-#else
-constexpr bool _openmp = false;
-#endif
-
-template <typename CONFIG_T, typename T> void _inference(T *c_inp, T *c_out, size_t n_samples)
-{
-    typename CONFIG_T::inp_t in_fixed_buf[CONFIG_T::N_inp];
-    typename CONFIG_T::out_t out_fixed_buf[CONFIG_T::N_out];
-
-    for(size_t i = 0; i < n_samples; ++i)
-        {
-            size_t offset_in = i * CONFIG_T::N_inp;
-            size_t offset_out = i * CONFIG_T::N_out;
-            for(size_t j = 0; j < CONFIG_T::N_inp; ++j)
-                {
-                    in_fixed_buf[j] = c_inp[offset_in + j];
-                }
-
-            CONFIG_T::f(in_fixed_buf, out_fixed_buf);
-
-            for(size_t j = 0; j < CONFIG_T::N_out; ++j)
-                {
-                    c_out[offset_out + j] = out_fixed_buf[j];
-                }
-        }
-}
-
-template <typename CONFIG_T, typename T> void batch_inference(T *c_inp, T *c_out, size_t n_samples)
-{
-#ifdef _OPENMP
-    size_t n_max_threads = omp_get_max_threads();
-    size_t n_samples_per_thread = std::max<size_t>(n_samples / n_max_threads, 32);
-    size_t n_thread = n_samples / n_samples_per_thread;
-    n_thread += (n_samples % n_samples_per_thread) ? 1 : 0;
-
-#pragma omp parallel for num_threads(n_thread) schedule(static)
-    for(size_t i = 0; i < n_thread; ++i)
-        {
-            size_t start = i * n_samples_per_thread;
-            size_t end = std::min<size_t>(start + n_samples_per_thread, n_samples);
-            size_t n_samples_this_thread = end - start;
-            size_t offset_in = start * CONFIG_T::N_inp;
-            size_t offset_out = start * CONFIG_T::N_out;
-            _inference<CONFIG_T, T>(&c_inp[offset_in], &c_out[offset_out], n_samples_this_thread);
-        }
-#else
-    _inference<CONFIG_T, T>(c_inp, c_out, n_samples);
-#endif
-}

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