da4ml 0.3.2__py3-none-any.whl → 0.4.0__py3-none-any.whl

da4ml/codegen/{verilog → rtl/verilog}/comb.py

@@ -2,7 +2,25 @@ from math import ceil, log2
 
 import numpy as np
 
-from ...cmvm.types import QInterval, Solution, _minimal_kif
+from ....cmvm.types import Op, QInterval, Solution, _minimal_kif
+
+
+def make_neg(
+    lines: list[str],
+    op: Op,
+    ops: list[Op],
+    bw0: int,
+    v0_name: str,
+):
+    _min, _max, step = ops[op.id0].qint
+    bw_neg = max(sum(_minimal_kif(QInterval(-_max, -_min, step))), bw0)
+    was_signed = int(_min < 0)
+    lines.append(
+        f'wire [{bw_neg - 1}:0] v{op.id0}_neg; negative #({bw0}, {bw_neg}, {was_signed}) op_neg_{op.id0} ({v0_name}, v{op.id0}_neg);'
+    )
+    bw0 = bw_neg
+    v0_name = f'v{op.id0}_neg'
+    return bw0, v0_name
 
 
 def ssa_gen(sol: Solution, neg_defined: set[int], print_latency: bool = False):
@@ -30,7 +48,7 @@ def ssa_gen(sol: Solution, neg_defined: set[int], print_latency: bool = False):
         match op.opcode:
             case -1:  # Input marker
                 i0, i1 = inp_idxs[op.id0]
-                line = f'{_def} assign {v} = inp[{i0}:{i1}];'
+                line = f'{_def} assign {v} = model_inp[{i0}:{i1}];'
 
             case 0 | 1:  # Common a+/-b<<shift oprs
                 p0, p1 = kifs[op.id0], kifs[op.id1]  # precision -> keep_neg, integers (no sign), fractional
@@ -49,45 +67,25 @@ def ssa_gen(sol: Solution, neg_defined: set[int], print_latency: bool = False):
                 v0_name = f'v{op.id0}'
                 bw0 = widths[op.id0]
 
-                if op.opcode == -2:
-                    _min, _max, step = ops[op.id0].qint
-                    bw_neg = max(sum(_minimal_kif(QInterval(-_max, -_min, step))), bw0)
-                    if op.id0 not in neg_defined:
-                        neg_defined.add(op.id0)
-                        was_signed = int(kifs[op.id0][0])
-                        lines.append(
-                            f'wire [{bw_neg - 1}:0] v{op.id0}_neg; negative #({bw0}, {bw_neg}, {was_signed}) op_neg_{op.id0} ({v0_name}, v{op.id0}_neg);'
-                        )
-                        bw0 = bw_neg
-                    v0_name = f'v{op.id0}_neg'
+                if op.opcode == -2 and op.id0 not in neg_defined:
+                    neg_defined.add(op.id0)
+                    bw0, v0_name = make_neg(lines, op, ops, bw0, v0_name)
                 if ops[op.id0].qint.min < 0:
                     line = f'{_def} assign {v} = {v0_name}[{i0}:{i1}] & {{{bw}{{~{v0_name}[{bw0 - 1}]}}}};'
                 else:
                     line = f'{_def} assign {v} = {v0_name}[{i0}:{i1}];'
+
             case 3 | -3:  # Explicit quantization
                 lsb_bias = kifs[op.id0][2] - kifs[i][2]
                 i0, i1 = bw + lsb_bias - 1, lsb_bias
                 v0_name = f'v{op.id0}'
                 bw0 = widths[op.id0]
 
-                if op.opcode == -3:
-                    _min, _max, step = ops[op.id0].qint
-                    lines.append('/* verilator lint_off WIDTHTRUNC */')
-                    bw_neg = max(sum(_minimal_kif(QInterval(-_max, -_min, step))), bw0)
-                    if op.id0 not in neg_defined:
-                        neg_defined.add(op.id0)
-                        # lines.append('/* verilator lint_off WIDTHTRUNC */')
-                        # lines.append(
-                        #     f'wire [{bw_neg - 1}:0] v{op.id0}_neg; assign v{op.id0}_neg[{bw_neg - 1}:0] = -{v0_name}[{bw0 - 1}:0];'
-                        # )
-                        # lines.append('/* verilator lint_on WIDTHTRUNC */')
-                        was_signed = int(kifs[op.id0][0])
-                        lines.append(
-                            f'wire [{bw_neg - 1}:0] v{op.id0}_neg; negative #({bw0}, {bw_neg}, {was_signed}) op_neg_{op.id0} ({v0_name}, v{op.id0}_neg);'
-                        )
-                    v0_name = f'v{op.id0}_neg'
-
+                if op.opcode == -3 and op.id0 not in neg_defined:
+                    neg_defined.add(op.id0)
+                    bw0, v0_name = make_neg(lines, op, ops, bw0, v0_name)
                 line = f'{_def} assign {v} = {v0_name}[{i0}:{i1}];'
+
             case 4:  # constant addition
                 num = op.data
                 sign, mag = int(num < 0), abs(num)
@@ -152,10 +150,10 @@ def output_gen(sol: Solution, neg_defined: set[int]):
                 lines.append(
                     f'wire [{bw - 1}:0] v{idx}_neg; negative #({bw0}, {bw}, {was_signed}) op_neg_{idx} (v{idx}, v{idx}_neg);'
                 )
-            lines.append(f'assign out[{i0}:{i1}] = v{idx}_neg[{bw - 1}:0];')
+            lines.append(f'assign model_out[{i0}:{i1}] = v{idx}_neg[{bw - 1}:0];')
 
         else:
-            lines.append(f'assign out[{i0}:{i1}] = v{idx}[{bw - 1}:0];')
+            lines.append(f'assign model_out[{i0}:{i1}] = v{idx}[{bw - 1}:0];')
     return lines
 
 
@@ -165,8 +163,8 @@ def comb_logic_gen(sol: Solution, fn_name: str, print_latency: bool = False, tim
 
     fn_signature = [
         f'module {fn_name} (',
-        f'    input [{inp_bits - 1}:0] inp,',
-        f'    output [{out_bits - 1}:0] out',
+        f'    input [{inp_bits - 1}:0] model_inp,',
+        f'    output [{out_bits - 1}:0] model_out',
         ');',
     ]
 

da4ml/codegen/{verilog → rtl/verilog}/io_wrapper.py

@@ -1,6 +1,6 @@
 from itertools import accumulate
 
-from ...cmvm.types import CascadedSolution, QInterval, Solution, _minimal_kif
+from ....cmvm.types import CascadedSolution, QInterval, Solution, _minimal_kif
 
 
 def hetero_io_map(qints: list[QInterval], merge: bool = False):
@@ -66,18 +66,18 @@ def generate_io_wrapper(sol: Solution | CascadedSolution, module_name: str, pipe
     w_reg_in, w_het_in = shape_in
     w_reg_out, w_het_out = shape_out
 
-    inp_assignment = [f'assign packed_inp[{ih}:{jh}] = inp[{ir}:{jr}];' for (ih, jh), (ir, jr) in zip(het_in, reg_in)]
+    inp_assignment = [f'assign packed_inp[{ih}:{jh}] = model_inp[{ir}:{jr}];' for (ih, jh), (ir, jr) in zip(het_in, reg_in)]
     _out_assignment: list[tuple[int, str]] = []
 
     for i, ((ih, jh), (ir, jr)) in enumerate(zip(het_out, reg_out)):
         if ih == jh - 1:
             continue
-        _out_assignment.append((ih, f'assign out[{ir}:{jr}] = packed_out[{ih}:{jh}];'))
+        _out_assignment.append((ih, f'assign model_out[{ir}:{jr}] = packed_out[{ih}:{jh}];'))
 
     for i, (i, j, copy_from) in enumerate(pad_out):
         n_bit = i - j + 1
         pad = f"{n_bit}'b0" if copy_from == -1 else f'{{{n_bit}{{packed_out[{copy_from}]}}}}'
-        _out_assignment.append((i, f'assign out[{i}:{j}] = {pad};'))
+        _out_assignment.append((i, f'assign model_out[{i}:{j}] = {pad};'))
     _out_assignment.sort(key=lambda x: x[0])
     out_assignment = [v for _, v in _out_assignment]
 
@@ -93,9 +93,9 @@ def generate_io_wrapper(sol: Solution | CascadedSolution, module_name: str, pipe
 
 module {module_name}_wrapper ({clk_and_rst_inp}
     // verilator lint_off UNUSEDSIGNAL
-    input [{w_reg_in - 1}:0] inp,
+    input [{w_reg_in - 1}:0] model_inp,
     // verilator lint_on UNUSEDSIGNAL
-    output [{w_reg_out - 1}:0] out
+    output [{w_reg_out - 1}:0] model_out
 );
     wire [{w_het_in - 1}:0] packed_inp;
     wire [{w_het_out - 1}:0] packed_out;
@@ -103,8 +103,8 @@ module {module_name}_wrapper ({clk_and_rst_inp}
     {inp_assignment_str}
 
     {module_name} op ({clk_and_rst_bind}
-        .inp(packed_inp),
-        .out(packed_out)
+        .model_inp(packed_inp),
+        .model_out(packed_out)
     );
 
     {out_assignment_str}

da4ml/codegen/{verilog → rtl/verilog}/pipeline.py

@@ -1,4 +1,4 @@
-from ...cmvm.types import CascadedSolution, _minimal_kif
+from ....cmvm.types import CascadedSolution, _minimal_kif
 from .comb import comb_logic_gen
 
 
@@ -13,18 +13,18 @@ def pipeline_logic_gen(
     inp_bits = [sum(map(sum, map(_minimal_kif, sol.inp_qint))) for sol in csol.solutions]
     out_bits = inp_bits[1:] + [sum(map(sum, map(_minimal_kif, csol.out_qint)))]
 
-    registers = [f'reg [{width}-1:0] stage{i}_inp;' for i, width in enumerate(inp_bits)]
+    registers = [f'reg [{width-1}:0] stage{i}_inp;' for i, width in enumerate(inp_bits)]
     for i in range(0, register_layers - 1):
-        registers += [f'reg [{width}-1:0] stage{j}_inp_copy{i};' for j, width in enumerate(inp_bits)]
-    wires = [f'wire [{width}-1:0] stage{i}_out;' for i, width in enumerate(out_bits)]
+        registers += [f'reg [{width-1}:0] stage{j}_inp_copy{i};' for j, width in enumerate(inp_bits)]
+    wires = [f'wire [{width-1}:0] stage{i}_out;' for i, width in enumerate(out_bits)]
 
-    comb_logic = [f'{name}_stage{i} stage{i} (.inp(stage{i}_inp), .out(stage{i}_out));' for i in range(N)]
+    comb_logic = [f'{name}_stage{i} stage{i} (.model_inp(stage{i}_inp), .model_out(stage{i}_out));' for i in range(N)]
 
     if register_layers == 1:
-        serial_logic = ['stage0_inp <= inp;']
+        serial_logic = ['stage0_inp <= model_inp;']
         serial_logic += [f'stage{i}_inp <= stage{i-1}_out;' for i in range(1, N)]
     else:
-        serial_logic = ['stage0_inp_copy0 <= inp;']
+        serial_logic = ['stage0_inp_copy0 <= model_inp;']
         for j in range(1, register_layers - 1):
             serial_logic.append(f'stage0_inp_copy{j} <= stage0_inp_copy{j-1};')
         serial_logic.append(f'stage0_inp <= stage0_inp_copy{register_layers - 2};')
@@ -34,15 +34,15 @@ def pipeline_logic_gen(
                 serial_logic.append(f'stage{i}_inp_copy{j} <= stage{i}_inp_copy{j-1};')
             serial_logic.append(f'stage{i}_inp <= stage{i}_inp_copy{register_layers - 2};')
 
-    serial_logic += [f'out <= stage{N-1}_out;']
+    serial_logic += [f'model_out <= stage{N-1}_out;']
 
     sep0 = '\n    '
     sep1 = '\n        '
 
     module = f"""module {name} (
     input clk,
-    input [{inp_bits[0]-1}:0] inp,
-    output reg [{out_bits[-1]-1}:0] out
+    input [{inp_bits[0]-1}:0] model_inp,
+    output reg [{out_bits[-1]-1}:0] model_out
 );
 
     {sep0.join(registers)}

da4ml/codegen/{verilog → rtl/verilog}/source/negative.v

@@ -11,6 +11,7 @@ module negative #(
     // verilator lint_off UNUSEDSIGNAL
     output [BW_OUT-1:0] out
 );
+  /* verilator lint_off WIDTHTRUNC */
   generate
     if (BW_IN < BW_OUT) begin : in_is_smaller
       wire [BW_OUT-1:0] in_ext;
@@ -24,5 +25,5 @@ module negative #(
       assign out = -in[BW_OUT-1:0];
     end
   endgenerate
-
+  /* verilator lint_on WIDTHTRUNC */
 endmodule

da4ml/codegen/rtl/vhdl/__init__.py

@@ -0,0 +1,10 @@
+from .comb import comb_logic_gen
+from .io_wrapper import binder_gen, generate_io_wrapper
+from .pipeline import pipeline_logic_gen
+
+__all__ = [
+    'comb_logic_gen',
+    'generate_io_wrapper',
+    'pipeline_logic_gen',
+    'binder_gen',
+]

da4ml/codegen/rtl/vhdl/comb.py

@@ -0,0 +1,192 @@
+from math import ceil, log2
+
+import numpy as np
+
+from ....cmvm.types import Op, QInterval, Solution, _minimal_kif
+
+
+def make_neg(
+    signals: list[str],
+    assigns: list[str],
+    op: Op,
+    ops: list[Op],
+    bw0: int,
+    v0_name: str,
+):
+    _min, _max, step = ops[op.id0].qint
+    bw_neg = max(sum(_minimal_kif(QInterval(-_max, -_min, step))), bw0)
+    was_signed = int(_min < 0)
+    signals.append(f'signal v{op.id0}_neg : std_logic_vector({bw_neg-1} downto {0});')
+    assigns.append(
+        f'op_neg_{op.id0} : entity work.negative generic map (BW_IN => {bw0}, BW_OUT => {bw_neg}, IN_SIGNED => {was_signed}) port map (neg_in => {v0_name}, neg_out => v{op.id0}_neg);'
+    )
+    bw0 = bw_neg
+    v0_name = f'v{op.id0}_neg'
+    return bw0, v0_name
+
+
+def ssa_gen(sol: Solution, neg_defined: set[int], print_latency: bool = False):
+    ops = sol.ops
+    kifs = list(map(_minimal_kif, (op.qint for op in ops)))
+    widths = list(map(sum, kifs))
+    inp_kifs = [_minimal_kif(qint) for qint in sol.inp_qint]
+    inp_widths = list(map(sum, inp_kifs))
+    _inp_widths = np.cumsum([0] + inp_widths)
+    inp_idxs = np.stack([_inp_widths[1:] - 1, _inp_widths[:-1]], axis=1)
+
+    signals = []
+    assigns = []
+    ref_count = sol.ref_count
+
+    for i, op in enumerate(ops):
+        if ref_count[i] == 0:
+            continue
+
+        bw = widths[i]
+        if bw == 0:
+            continue
+
+        match op.opcode:
+            case -1:  # Input marker
+                i0, i1 = inp_idxs[op.id0]
+                signals.append(f'signal v{i}:std_logic_vector({bw-1} downto {0});')
+                line = f'v{i} <= model_inp({i0} downto {i1});'
+
+            case 0 | 1:  # Common a+/-b<<shift oprs
+                p0, p1 = kifs[op.id0], kifs[op.id1]
+                bw0, bw1 = widths[op.id0], widths[op.id1]
+                s0, f0, s1, f1 = int(p0[0]), p0[2], int(p1[0]), p1[2]
+                shift = op.data + f0 - f1
+                signals.append(f'signal v{i}:std_logic_vector({bw-1} downto {0});')
+                line = f'op_{i}:entity work.shift_adder generic map(BW_INPUT0=>{bw0},BW_INPUT1=>{bw1},SIGNED0=>{s0},SIGNED1=>{s1},BW_OUT=>{bw},SHIFT1=>{shift},IS_SUB=>{op.opcode}) port map(in0=>v{op.id0},in1=>v{op.id1},result=>v{i});'
+
+            case 2 | -2:  # ReLU
+                lsb_bias = kifs[op.id0][2] - kifs[i][2]
+                i0, i1 = bw + lsb_bias - 1, lsb_bias
+                v0_name = f'v{op.id0}'
+                bw0 = widths[op.id0]
+                if op.opcode == -2 and op.id0 not in neg_defined:
+                    neg_defined.add(op.id0)
+                    bw0, v0_name = make_neg(signals, assigns, op, ops, bw0, v0_name)
+                signals.append(f'signal v{i}:std_logic_vector({bw-1} downto {0});')
+                if ops[op.id0].qint.min < 0:
+                    if bw > 1:
+                        line = f'v{i} <= {v0_name}({i0} downto {i1}) and ({bw - 1} downto 0 => not {v0_name}({bw0-1}));'
+                    else:
+                        line = f'v{i}(0) <= {v0_name}(0) and (not {v0_name}({bw0-1}));'
+                else:
+                    line = f'v{i} <= {v0_name}({i0} downto {i1});'
+
+            case 3 | -3:  # Explicit quantization
+                lsb_bias = kifs[op.id0][2] - kifs[i][2]
+                i0, i1 = bw + lsb_bias - 1, lsb_bias
+                v0_name = f'v{op.id0}'
+                bw0 = widths[op.id0]
+                if op.opcode == -3 and op.id0 not in neg_defined:
+                    neg_defined.add(op.id0)
+                    bw0, v0_name = make_neg(signals, assigns, op, ops, bw0, v0_name)
+                signals.append(f'signal v{i}:std_logic_vector({bw-1} downto {0});')
+                line = f'v{i} <= {v0_name}({i0} downto {i1});'
+
+            case 4:  # constant addition
+                num = op.data
+                sign, mag = int(num < 0), abs(num)
+                bw1 = ceil(log2(mag + 1)) if mag > 0 else 1
+                bw0 = widths[op.id0]
+                s0 = int(kifs[op.id0][0])
+                shift = kifs[op.id0][2] - kifs[i][2]
+                signals.append(f'signal v{i}:std_logic_vector({bw-1} downto {0});')
+                bin_val = format(mag, f'0{bw1}b')
+                line = f'op_{i}:entity work.shift_adder generic map(BW_INPUT0=>{bw0},BW_INPUT1=>{bw1},SIGNED0=>{s0},SIGNED1=>0,BW_OUT=>{bw},SHIFT1=>{shift},IS_SUB=>{sign}) port map(in0=>v{op.id0},in1=>"{bin_val}",result=>v{i});'
+            case 5:  # constant
+                num = op.data
+                if num < 0:
+                    num = 2**bw + num
+                signals.append(f'signal v{i}:std_logic_vector({bw-1} downto {0});')
+                bin_val = format(num, f'0{bw}b')
+                line = f'v{i} <= "{bin_val}";'
+
+            case 6 | -6:  # MSB Muxing
+                k, a, b = op.data & 0xFFFFFFFF, op.id0, op.id1
+                p0, p1 = kifs[a], kifs[b]
+                inv = '1' if op.opcode == -6 else '0'
+                bwk, bw0, bw1 = widths[k], widths[a], widths[b]
+                s0, f0, s1, f1 = int(p0[0]), p0[2], int(p1[0]), p1[2]
+                _shift = (op.data >> 32) & 0xFFFFFFFF
+                _shift = _shift if _shift < 0x80000000 else _shift - 0x100000000
+                shift = f0 - f1 + _shift
+                signals.append(f'signal v{i}:std_logic_vector({bw-1} downto {0});')
+                line = f'op_{i}:entity work.mux generic map(BW_INPUT0=>{bw0},BW_INPUT1=>{bw1},SIGNED0=>{s0},SIGNED1=>{s1},BW_OUT=>{bw},SHIFT1=>{shift},INVERT1=>{inv}) port map(key=>v{k}({bwk-1}),in0=>v{a},in1=>v{b},result=>v{i});'
+            case 7:  # Multiplication
+                bw0, bw1 = widths[op.id0], widths[op.id1]
+                s0, s1 = int(kifs[op.id0][0]), int(kifs[op.id1][0])
+                signals.append(f'signal v{i}:std_logic_vector({bw-1} downto {0});')
+                line = f'op_{i}:entity work.multiplier generic map(BW_INPUT0=>{bw0},BW_INPUT1=>{bw1},SIGNED0=>{s0},SIGNED1=>{s1},BW_OUT=>{bw}) port map(in0=>v{op.id0},in1=>v{op.id1},result=>v{i});'
+
+            case _:
+                raise ValueError(f'Unknown opcode {op.opcode} for operation {i} ({op})')
+
+        if print_latency:
+            line += f' -- {op.latency}'
+        assigns.append(line)
+    return signals, assigns
+
+
+def output_gen(sol: Solution, neg_defined: set[int]):
+    assigns = []
+    signals = []
+    widths = list(map(sum, map(_minimal_kif, sol.out_qint)))
+    _widths = np.cumsum([0] + widths)
+    out_idxs = np.stack([_widths[1:] - 1, _widths[:-1]], axis=1)
+    for i, idx in enumerate(sol.out_idxs):
+        if idx < 0:
+            continue
+        i0, i1 = out_idxs[i]
+        if i0 == i1 - 1:
+            continue
+        bw = widths[i]
+        if sol.out_negs[i]:
+            if idx not in neg_defined:
+                neg_defined.add(idx)
+                bw0 = sum(_minimal_kif(sol.ops[idx].qint))
+                was_signed = int(_minimal_kif(sol.ops[idx].qint)[0])
+                signals.append(f'signal v{idx}_neg:std_logic_vector({bw-1} downto {0});')
+                assigns.append(
+                    f'op_neg_{idx}:entity work.negative generic map(BW_IN=>{bw0},BW_OUT=>{bw},IN_SIGNED=>{was_signed}) port map(neg_in=>v{idx},neg_out=>v{idx}_neg);'
+                )
+            assigns.append(f'model_out({i0} downto {i1}) <= v{idx}_neg({bw-1} downto {0});')
+        else:
+            assigns.append(f'model_out({i0} downto {i1}) <= v{idx}({bw-1} downto {0});')
+    return signals, assigns
+
+
+def comb_logic_gen(sol: Solution, fn_name: str, print_latency: bool = False, timescale: str | None = None):
+    inp_bits = sum(map(sum, map(_minimal_kif, sol.inp_qint)))
+    out_bits = sum(map(sum, map(_minimal_kif, sol.out_qint)))
+
+    neg_defined = set()
+    ssa_signals, ssa_assigns = ssa_gen(sol, neg_defined=neg_defined, print_latency=print_latency)
+    output_signals, output_assigns = output_gen(sol, neg_defined)
+    blk = '\n    '
+
+    code = f"""library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity {fn_name} is port(
+    model_inp:in std_logic_vector({inp_bits-1} downto {0});
+    model_out:out std_logic_vector({out_bits-1} downto {0})
+);
+end entity {fn_name};
+
+architecture rtl of {fn_name} is
+    {blk.join(ssa_signals + output_signals)}
+
+
+begin
+    {blk.join(ssa_assigns + output_assigns)}
+
+end architecture rtl;
+
+"""
+    return code

da4ml/codegen/rtl/vhdl/io_wrapper.py

@@ -0,0 +1,157 @@
+from itertools import accumulate
+
+from ....cmvm.types import CascadedSolution, QInterval, Solution, _minimal_kif
+
+
+def _loc(i: int, j: int):
+    return f'({i} downto {j})' if i != j else f'({i})'
+
+
+def hetero_io_map(qints: list[QInterval], merge: bool = False):
+    N = len(qints)
+    ks, _is, fs = zip(*map(_minimal_kif, qints))
+    Is = [_i + _k for _i, _k in zip(_is, ks)]
+    max_I, max_f = max(_is) + max(ks), max(fs)
+    max_bw = max_I + max_f
+    width_regular, width_packed = max_bw * N, sum(Is) + sum(fs)
+
+    regular: list[tuple[int, int]] = []
+    pads: list[tuple[int, int, int]] = []
+
+    bws = [I + f for I, f in zip(Is, fs)]
+    _bw = list(accumulate([0] + bws))
+    hetero = [(i - 1, j) for i, j in zip(_bw[1:], _bw[:-1])]
+
+    for i in range(N):
+        base = max_bw * i
+        bias_low = max_f - fs[i]
+        bias_high = max_I - Is[i]
+        low = base + bias_low
+        high = (base + max_bw - 1) - bias_high
+        regular.append((high, low))
+
+        if bias_low != 0:
+            pads.append((base + bias_low - 1, base, -1))
+        if bias_high != 0:
+            copy_from = hetero[i][0] if ks[i] else -1
+            pads.append((base + max_bw - 1, base + max_bw - bias_high, copy_from))
+
+    mask = list(high < low for high, low in hetero)
+    regular = [r for r, m in zip(regular, mask) if not m]
+    hetero = [h for h, m in zip(hetero, mask) if not m]
+
+    if not merge:
+        return regular, hetero, pads, (width_regular, width_packed)
+
+    # Merging consecutive intervals when possible
+    NN = len(regular) - 2
+    for i in range(NN, -1, -1):
+        this_high = regular[i][0]
+        next_low = regular[i + 1][1]
+        if next_low - this_high != 1:
+            continue
+        regular[i] = (regular[i + 1][0], regular[i][1])
+        regular.pop(i + 1)
+        hetero[i] = (hetero[i + 1][0], hetero[i][1])
+        hetero.pop(i + 1)
+
+    for i in range(len(pads) - 2, -1, -1):
+        if pads[i + 1][1] - pads[i][0] == 1 and pads[i][2] == pads[i + 1][2]:
+            pads[i] = (pads[i + 1][0], pads[i][1], pads[i][2])
+            pads.pop(i + 1)
+
+    return regular, hetero, pads, (width_regular, width_packed)
+
+
+def generate_io_wrapper(sol: Solution | CascadedSolution, module_name: str, pipelined: bool = False):
+    reg_in, het_in, _, shape_in = hetero_io_map(sol.inp_qint, merge=True)
+    reg_out, het_out, pad_out, shape_out = hetero_io_map(sol.out_qint, merge=True)
+
+    w_reg_in, w_het_in = shape_in
+    w_reg_out, w_het_out = shape_out
+
+    inp_assignment = [f'packed_inp{_loc(ih,jh)} <= model_inp{_loc(ir,jr)};' for (ih, jh), (ir, jr) in zip(het_in, reg_in)]
+    _out_assignment: list[tuple[int, str]] = []
+
+    for i, ((ih, jh), (ir, jr)) in enumerate(zip(het_out, reg_out)):
+        if ih == jh - 1:
+            continue
+        _out_assignment.append((ih, f'model_out{_loc(ir,jr)} <= packed_out{_loc(ih,jh)};'))
+
+    for i, (i, j, copy_from) in enumerate(pad_out):
+        n_bit = i - j + 1
+        value = "'0'" if copy_from == -1 else f'packed_out({copy_from})'
+        pad = f'(others => {value})' if n_bit > 1 else value
+        _out_assignment.append((i, f'model_out{_loc(i,j)} <= {pad};'))
+    _out_assignment.sort(key=lambda x: x[0])
+    out_assignment = [v for _, v in _out_assignment]
+
+    inp_assignment_str = '\n    '.join(inp_assignment)
+    out_assignment_str = '\n    '.join(out_assignment)
+
+    clk_and_rst_inp, clk_and_rst_bind = '', ''
+    if pipelined:
+        clk_and_rst_inp = '\n    clk:in std_logic;'
+        clk_and_rst_bind = '\n        clk=>clk,'
+
+    return f"""library ieee;
+use ieee.std_logic_1164.all;
+entity {module_name}_wrapper is port({clk_and_rst_inp}
+    model_inp:in std_logic_vector({w_reg_in-1} downto {0});
+    model_out:out std_logic_vector({w_reg_out-1} downto {0})
+);
+end entity {module_name}_wrapper;
+
+architecture rtl of {module_name}_wrapper is
+    signal packed_inp:std_logic_vector({w_het_in-1} downto {0});
+    signal packed_out:std_logic_vector({w_het_out-1} downto {0});
+
+begin
+    {inp_assignment_str}
+
+    op:entity work.{module_name} port map({clk_and_rst_bind}
+        model_inp=>packed_inp,
+        model_out=>packed_out
+    );
+
+    {out_assignment_str}
+
+end architecture rtl;
+"""
+
+
+def binder_gen(csol: CascadedSolution | Solution, module_name: str, II: int = 1, latency_multiplier: int = 1):
+    k_in, i_in, f_in = zip(*map(_minimal_kif, csol.inp_qint))
+    k_out, i_out, f_out = zip(*map(_minimal_kif, csol.out_qint))
+    max_inp_bw = max(k_in) + max(i_in) + max(f_in)
+    max_out_bw = max(k_out) + max(i_out) + max(f_out)
+    if isinstance(csol, Solution):
+        II = latency = 0
+    else:
+        latency = len(csol.solutions) * latency_multiplier
+
+    n_in, n_out = csol.shape
+    return f"""#include <cstddef>
+#include "binder_util.hh"
+#include "V{module_name}.h"
+
+struct {module_name}_config {{
+    static const size_t N_inp = {n_in};
+    static const size_t N_out = {n_out};
+    static const size_t max_inp_bw = {max_inp_bw};
+    static const size_t max_out_bw = {max_out_bw};
+    static const size_t II = {II};
+    static const size_t latency = {latency};
+    typedef V{module_name} dut_t;
+}};
+
+extern "C" {{
+bool openmp_enabled() {{
+    return _openmp;
+}}
+
+void inference(int32_t *c_inp, int32_t *c_out, size_t n_samples) {{
+    batch_inference<{module_name}_config>(c_inp, c_out, n_samples);
+}}
+}}
+"""

da4ml/codegen/rtl/vhdl/pipeline.py

@@ -0,0 +1,71 @@
+from ....cmvm.types import CascadedSolution, _minimal_kif
+from .comb import comb_logic_gen
+
+
+def pipeline_logic_gen(
+    csol: CascadedSolution,
+    name: str,
+    print_latency=False,
+    timescale: str | None = None,
+    register_layers: int = 1,
+):
+    N = len(csol.solutions)
+    inp_bits = [sum(map(sum, map(_minimal_kif, sol.inp_qint))) for sol in csol.solutions]
+    out_bits = inp_bits[1:] + [sum(map(sum, map(_minimal_kif, csol.out_qint)))]
+
+    registers = [f'signal stage{i}_inp:std_logic_vector({width-1} downto 0);' for i, width in enumerate(inp_bits)]
+    for i in range(0, register_layers - 1):
+        registers += [f'signal stage{j}_inp_copy{i}:std_logic_vector({width-1} downto 0);' for j, width in enumerate(inp_bits)]
+    wires = [f'signal stage{i}_out:std_logic_vector({width-1} downto 0);' for i, width in enumerate(out_bits)]
+
+    comb_logic = [
+        f'stage{i}:entity work.{name}_stage{i} port map(model_inp=>stage{i}_inp,model_out=>stage{i}_out);' for i in range(N)
+    ]
+
+    if register_layers == 1:
+        serial_logic = ['stage0_inp <= model_inp;']
+        serial_logic += [f'stage{i}_inp <= stage{i-1}_out;' for i in range(1, N)]
+    else:
+        serial_logic = ['stage0_inp_copy0 <= model_inp;']
+        for j in range(1, register_layers - 1):
+            serial_logic.append(f'stage0_inp_copy{j} <= stage0_inp_copy{j-1};')
+        serial_logic.append(f'stage0_inp <= stage0_inp_copy{register_layers - 2};')
+        for i in range(1, N):
+            serial_logic.append(f'stage{i}_inp_copy0 <= stage{i-1}_out;')
+            for j in range(1, register_layers - 1):
+                serial_logic.append(f'stage{i}_inp_copy{j} <= stage{i}_inp_copy{j-1};')
+            serial_logic.append(f'stage{i}_inp <= stage{i}_inp_copy{register_layers - 2};')
+
+    serial_logic += [f'model_out <= stage{N-1}_out;']
+
+    blk = '\n    '
+
+    module = f"""library ieee;
+use ieee.std_logic_1164.all;
+entity {name} is port(
+    clk:in std_logic;
+    model_inp:in std_logic_vector({inp_bits[0]-1} downto 0);
+    model_out:out std_logic_vector({out_bits[-1]-1} downto 0));
+end entity {name};
+
+architecture rtl of {name} is
+    {blk.join(registers)}
+    {blk.join(wires)}
+
+begin
+    {blk.join(comb_logic)}
+
+    process(clk) begin
+        if rising_edge(clk) then
+            {f'{blk}        '.join(serial_logic)}
+        end if;
+    end process;
+end architecture rtl;
+"""
+
+    ret: dict[str, str] = {}
+    for i, s in enumerate(csol.solutions):
+        stage_name = f'{name}_stage{i}'
+        ret[stage_name] = comb_logic_gen(s, stage_name, print_latency=print_latency, timescale=timescale)
+    ret[name] = module
+    return ret