angr 9.2.118__py3-none-win_amd64.whl → 9.2.120__py3-none-win_amd64.whl

angr/analyses/stack_pointer_tracker.py

@@ -1,7 +1,7 @@
 # pylint:disable=abstract-method,ungrouped-imports
 from __future__ import annotations
 
-from typing import TYPE_CHECKING
+from typing import Any, TYPE_CHECKING
 import re
 import logging
 from collections import defaultdict
@@ -9,11 +9,11 @@ from collections import defaultdict
 import pyvex
 
 from angr.analyses import ForwardAnalysis, visitors
-from ..utils.constants import is_alignment_mask
-from ..analyses import AnalysesHub
-from ..knowledge_plugins import Function
-from ..block import BlockNode
-from ..errors import SimTranslationError
+from angr.utils.constants import is_alignment_mask
+from angr.analyses import AnalysesHub
+from angr.knowledge_plugins import Function
+from angr.block import BlockNode
+from angr.errors import SimTranslationError
 from .analysis import Analysis
 import contextlib
 
@@ -179,7 +179,13 @@ class FrozenStackPointerTrackerState:
 
     __slots__ = "regs", "memory", "is_tracking_memory", "resilient"
 
-    def __init__(self, regs, memory, is_tracking_memory, resilient):
+    def __init__(
+        self,
+        regs,
+        memory,
+        is_tracking_memory,
+        resilient,
+    ):
         self.regs = regs
         self.memory = memory
         self.is_tracking_memory = is_tracking_memory
@@ -193,8 +199,10 @@ class FrozenStackPointerTrackerState:
             return hash((FrozenStackPointerTrackerState, self.regs, self.memory, self.is_tracking_memory))
         return hash((FrozenStackPointerTrackerState, self.regs, self.is_tracking_memory))
 
-    def merge(self, other):
-        return self.unfreeze().merge(other.unfreeze()).freeze()
+    def merge(
+        self, other, addr: int, reg_merge_cache: dict[tuple[int, int], Any], mem_merge_cache: dict[tuple[int, int], Any]
+    ):
+        return self.unfreeze().merge(other.unfreeze(), addr, reg_merge_cache, mem_merge_cache).freeze()
 
     def __eq__(self, other):
         if type(other) is FrozenStackPointerTrackerState or isinstance(other, FrozenStackPointerTrackerState):
@@ -278,16 +286,18 @@ class StackPointerTrackerState:
             return hash((StackPointerTrackerState, self.regs, self.memory, self.is_tracking_memory))
         return hash((StackPointerTrackerState, self.regs, self.is_tracking_memory))
 
-    def merge(self, other):
+    def merge(
+        self, other, addr: int, reg_merge_cache: dict[tuple[int, int], Any], mem_merge_cache: dict[tuple[int, int], Any]
+    ):
         return StackPointerTrackerState(
-            regs=_dict_merge(self.regs, other.regs, self.resilient),
-            memory=_dict_merge(self.memory, other.memory, self.resilient),
+            regs=_dict_merge(self.regs, other.regs, self.resilient, addr, reg_merge_cache),
+            memory=_dict_merge(self.memory, other.memory, self.resilient, addr, mem_merge_cache),
             is_tracking_memory=self.is_tracking_memory and other.is_tracking_memory,
             resilient=self.resilient or other.resilient,
         )
 
 
-def _dict_merge(d1, d2, resilient: bool):
+def _dict_merge(d1, d2, resilient: bool, addr: int, merge_cache: dict[tuple[int, int], Any]):
     all_keys = set(d1.keys()) | set(d2.keys())
     merged = {}
     for k in all_keys:
@@ -299,7 +309,12 @@ def _dict_merge(d1, d2, resilient: bool):
             merged[k] = d1[k]
         else:  # d1[k] != d2[k]
             if resilient and isinstance(d1[k], OffsetVal) and isinstance(d2[k], OffsetVal):
-                merged[k] = min(d1[k], d2[k])
+                if (addr, k) in merge_cache:
+                    merged[k] = merge_cache[(addr, k)]
+                else:
+                    v = min(d1[k], d2[k])
+                    merge_cache[(addr, k)] = v
+                    merged[k] = v
             else:
                 merged[k] = TOP
     return merged
@@ -350,6 +365,9 @@ class StackPointerTracker(Analysis, ForwardAnalysis):
         self._reg_value_at_block_start = defaultdict(dict)
         self.cross_insn_opt = cross_insn_opt
         self._resilient = resilient
+        # in resilience mode, cache previously merged values to ensure we reach a fixed point
+        self._reg_merge_cache = {}
+        self._mem_merge_cache = {}
 
         if initial_reg_values:
             self._reg_value_at_block_start[func.addr if func is not None else block.addr] = initial_reg_values
@@ -492,7 +510,7 @@ class StackPointerTracker(Analysis, ForwardAnalysis):
     def _set_state(self, addr, new_val, pre_or_post):
         previous_val = self._state_for(addr, pre_or_post)
         if previous_val is not None:
-            new_val = previous_val.merge(new_val)
+            new_val = previous_val.merge(new_val, addr, self._reg_merge_cache, self._mem_merge_cache)
         if addr not in self.states:
             self.states[addr] = {}
         self.states[addr][pre_or_post] = new_val
@@ -808,7 +826,7 @@ class StackPointerTracker(Analysis, ForwardAnalysis):
     def _merge_states(self, node, *states: StackPointerTrackerState):
         merged_state = states[0]
         for other in states[1:]:
-            merged_state = merged_state.merge(other)
+            merged_state = merged_state.merge(other, node.addr, self._reg_merge_cache, self._mem_merge_cache)
         return merged_state, merged_state == states[0]
 
     def _find_callees(self, node) -> list[Function]:

angr/analyses/static_hooker.py

@@ -3,8 +3,8 @@ import logging
 
 from . import Analysis
 
-from .. import SIM_LIBRARIES
-from ..errors import AngrValueError
+from angr import SIM_LIBRARIES
+from angr.errors import AngrValueError
 
 l = logging.getLogger(name=__name__)
 

angr/analyses/typehoon/__init__.py

@@ -1,2 +1,5 @@
 from __future__ import annotations
+
 from .typehoon import Typehoon
+
+__all__ = ("Typehoon",)

angr/analyses/typehoon/lifter.py

@@ -1,7 +1,7 @@
 from __future__ import annotations
 from typing import TYPE_CHECKING
 
-from ...sim_type import (
+from angr.sim_type import (
     SimType,
     SimTypeChar,
     SimTypeShort,

angr/analyses/typehoon/translator.py

@@ -1,18 +1,23 @@
+# pylint:disable=unused-argument,no-self-use
 from __future__ import annotations
 from itertools import count
 
-from ... import sim_type
-from ...sim_type import SimType
+from angr import sim_type
+from angr.sim_type import SimType
 from . import typeconsts
 from .typeconsts import TypeConstant
 
 
 class SimTypeTempRef(sim_type.SimType):
+    """
+    Represents a temporary reference to another type. TypeVariableReference is translated to SimTypeTempRef.
+    """
+
     def __init__(self, typevar):
         super().__init__()
         self.typevar = typevar
 
-    def c_repr(self):
+    def c_repr(self, **kwargs):
         return "<SimTypeTempRef>"
 
 
@@ -141,7 +146,10 @@ class TypeTranslator:
         return sim_type.SimTypeLongLong(signed=False).with_arch(self.arch)
 
     def _translate_Int128(self, tc):  # pylint:disable=unused-argument
-        return sim_type.SimTypeNum(128, signed=False).with_arch(self.arch)
+        return sim_type.SimTypeInt128(signed=False).with_arch(self.arch)
+
+    def _translate_Int256(self, tc):  # pylint:disable=unused-argument
+        return sim_type.SimTypeInt256(signed=False).with_arch(self.arch)
 
     def _translate_TypeVariableReference(self, tc):
         if tc.typevar in self.translated:
@@ -176,6 +184,12 @@ class TypeTranslator:
     # SimType handlers
     #
 
+    def _translate_SimTypeInt128(self, st: sim_type.SimTypeChar) -> typeconsts.Int128:
+        return typeconsts.Int128()
+
+    def _translate_SimTypeInt256(self, st: sim_type.SimTypeChar) -> typeconsts.Int256:
+        return typeconsts.Int256()
+
     def _translate_SimTypeInt(self, st: sim_type.SimTypeInt) -> typeconsts.Int32:
         return typeconsts.Int32()
 
@@ -220,6 +234,7 @@ TypeConstHandlers = {
     typeconsts.Int32: TypeTranslator._translate_Int32,
     typeconsts.Int64: TypeTranslator._translate_Int64,
     typeconsts.Int128: TypeTranslator._translate_Int128,
+    typeconsts.Int256: TypeTranslator._translate_Int256,
     typeconsts.TypeVariableReference: TypeTranslator._translate_TypeVariableReference,
 }
 
@@ -230,6 +245,8 @@ SimTypeHandlers = {
     sim_type.SimTypeLong: TypeTranslator._translate_SimTypeLong,
     sim_type.SimTypeLongLong: TypeTranslator._translate_SimTypeLongLong,
     sim_type.SimTypeChar: TypeTranslator._translate_SimTypeChar,
+    sim_type.SimTypeInt128: TypeTranslator._translate_SimTypeInt128,
+    sim_type.SimTypeInt256: TypeTranslator._translate_SimTypeInt256,
     sim_type.SimStruct: TypeTranslator._translate_SimStruct,
     sim_type.SimTypeArray: TypeTranslator._translate_SimTypeArray,
 }

angr/analyses/typehoon/typeconsts.py

@@ -100,6 +100,13 @@ class Int128(Int):
         return "int128"
 
 
+class Int256(Int):
+    SIZE = 32
+
+    def __repr__(self, memo=None):
+        return "int256"
+
+
 class FloatBase(TypeConstant):
     def __repr__(self, memo=None):
         return "floatbase"
@@ -282,6 +289,7 @@ def int_type(bits: int) -> Int | None:
         32: Int32,
         64: Int64,
         128: Int128,
+        256: Int256,
     }
     if bits in mapping:
         return mapping[bits]()

angr/analyses/typehoon/typehoon.py

@@ -2,9 +2,9 @@
 from __future__ import annotations
 from typing import TYPE_CHECKING
 
-from ...sim_type import SimStruct, SimTypePointer, SimTypeArray
-from ...errors import AngrRuntimeError
-from ..analysis import Analysis, AnalysesHub
+from angr.sim_type import SimStruct, SimTypePointer, SimTypeArray
+from angr.errors import AngrRuntimeError
+from angr.analyses.analysis import Analysis, AnalysesHub
 from .simple_solver import SimpleSolver
 from .translator import TypeTranslator
 from .typeconsts import Struct, Pointer, TypeConstant, Array, TopType

angr/analyses/variable_recovery/__init__.py

@@ -1,3 +1,9 @@
 from __future__ import annotations
+
 from .variable_recovery import VariableRecovery
 from .variable_recovery_fast import VariableRecoveryFast
+
+__all__ = (
+    "VariableRecovery",
+    "VariableRecoveryFast",
+)

angr/analyses/variable_recovery/engine_ail.py

@@ -9,11 +9,11 @@ from unique_log_filter import UniqueLogFilter
 
 from angr.procedures import SIM_LIBRARIES, SIM_TYPE_COLLECTIONS
 from angr.utils.constants import MAX_POINTSTO_BITS
-from ...calling_conventions import SimRegArg
-from ...sim_type import SimTypeFunction, dereference_simtype
-from ...engines.light import SimEngineLightAILMixin
-from ..typehoon import typeconsts, typevars
-from ..typehoon.lifter import TypeLifter
+from angr.calling_conventions import SimRegArg
+from angr.sim_type import SimTypeFunction, dereference_simtype
+from angr.engines.light import SimEngineLightAILMixin
+from angr.analyses.typehoon import typeconsts, typevars
+from angr.analyses.typehoon.lifter import TypeLifter
 from .engine_base import SimEngineVRBase, RichR
 
 if TYPE_CHECKING:

angr/analyses/variable_recovery/engine_base.py

@@ -6,13 +6,13 @@ import logging
 import ailment
 import claripy
 
-from ...storage.memory_mixins.paged_memory.pages.multi_values import MultiValues
-from ...engines.light import SimEngineLight, ArithmeticExpression
-from ...errors import SimEngineError, SimMemoryMissingError
-from ...sim_variable import SimVariable, SimStackVariable, SimRegisterVariable, SimMemoryVariable
-from ...code_location import CodeLocation
-from ..typehoon import typevars, typeconsts
-from ..typehoon.typevars import TypeVariable, DerivedTypeVariable, AddN, SubN, Load, Store
+from angr.storage.memory_mixins.paged_memory.pages.multi_values import MultiValues
+from angr.engines.light import SimEngineLight, ArithmeticExpression
+from angr.errors import SimEngineError, SimMemoryMissingError
+from angr.sim_variable import SimVariable, SimStackVariable, SimRegisterVariable, SimMemoryVariable
+from angr.code_location import CodeLocation
+from angr.analyses.typehoon import typevars, typeconsts
+from angr.analyses.typehoon.typevars import TypeVariable, DerivedTypeVariable, AddN, SubN, Load, Store
 
 if TYPE_CHECKING:
     from .variable_recovery_base import VariableRecoveryStateBase

angr/analyses/variable_recovery/engine_vex.py

@@ -6,13 +6,13 @@ import claripy
 import pyvex
 from archinfo.arch_arm import is_arm_arch
 
-from ...errors import SimMemoryMissingError
-from ...calling_conventions import SimRegArg, SimStackArg, default_cc
-from ...engines.vex.claripy.datalayer import value as claripy_value
-from ...engines.light import SimEngineLightVEXMixin
-from ...knowledge_plugins import Function
-from ...storage.memory_mixins.paged_memory.pages.multi_values import MultiValues
-from ..typehoon import typevars, typeconsts
+from angr.errors import SimMemoryMissingError
+from angr.calling_conventions import SimRegArg, SimStackArg, default_cc
+from angr.engines.vex.claripy.datalayer import value as claripy_value
+from angr.engines.light import SimEngineLightVEXMixin
+from angr.knowledge_plugins import Function
+from angr.storage.memory_mixins.paged_memory.pages.multi_values import MultiValues
+from angr.analyses.typehoon import typevars, typeconsts
 from .engine_base import SimEngineVRBase, RichR
 from .irsb_scanner import VEXIRSBScanner
 
@@ -254,10 +254,13 @@ class SimEngineVRVEX(
             typevar = typevars.DerivedTypeVariable(r0.typevar, typevars.AddN(r1.data.concrete_value))
 
         sum_ = r0.data + r1.data
+        tc = set()
+        if r0.typevar is not None and r1.typevar is not None:
+            tc.add(typevars.Subtype(r0.typevar, r1.typevar))
         return RichR(
             sum_,
             typevar=typevar,
-            type_constraints={typevars.Subtype(r0.typevar, r1.typevar)},
+            type_constraints=tc,
         )
 
     def _handle_Sub(self, expr):
@@ -501,6 +504,9 @@ class SimEngineVRVEX(
     def _handle_Clz(self, expr):
         return RichR(self.state.top(expr.result_size(self.tyenv)))
 
+    def _handle_Ctz(self, expr):
+        return RichR(self.state.top(expr.result_size(self.tyenv)))
+
     def _handle_Mull(self, expr):
         return RichR(self.state.top(expr.result_size(self.tyenv)))
 
@@ -553,15 +559,6 @@ class SimEngineVRVEX(
         _, _ = self._expr(expr.args[0]), self._expr(expr.args[1])
         return RichR(self.state.top(expr.result_size(self.tyenv)))
 
-    def _handle_Clz(self, expr):
-        arg0 = expr.args[0]
-        expr_0 = self._expr(arg0)
-        if expr_0 is None:
-            return None
-        if self.state.is_top(expr_0.data):
-            return RichR(self.state.top(expr_0.data.size()))
-        return RichR(self.state.top(expr_0.data.size()))
-
     _handle_CmpEQ_v = _handle_Cmp_v
     _handle_CmpNE_v = _handle_Cmp_v
     _handle_CmpLE_v = _handle_Cmp_v

angr/analyses/variable_recovery/variable_recovery.py

@@ -6,11 +6,11 @@ import claripy
 
 from angr.analyses import ForwardAnalysis, visitors
 from angr.analyses import AnalysesHub
-from ...errors import SimMemoryMissingError
-from ...storage.memory_mixins.paged_memory.pages.multi_values import MultiValues
-from ... import BP, BP_AFTER
-from ...sim_variable import SimRegisterVariable, SimStackVariable
-from ...code_location import CodeLocation
+from angr.errors import SimMemoryMissingError
+from angr.storage.memory_mixins.paged_memory.pages.multi_values import MultiValues
+from angr import BP, BP_AFTER
+from angr.sim_variable import SimRegisterVariable, SimStackVariable
+from angr.code_location import CodeLocation
 from .variable_recovery_base import VariableRecoveryBase, VariableRecoveryStateBase
 from .annotations import StackLocationAnnotation
 

angr/analyses/variable_recovery/variable_recovery_base.py

@@ -10,13 +10,13 @@ from claripy.annotation import Annotation
 from archinfo import Arch
 from ailment.expression import BinaryOp, StackBaseOffset
 
-from ...utils.cowdict import DefaultChainMapCOW
-from ...engines.light import SpOffset
-from ...sim_variable import SimVariable
-from ...errors import AngrRuntimeError
-from ...storage.memory_mixins import MultiValuedMemory
-from ..analysis import Analysis
-from ..typehoon.typevars import TypeVariables, TypeVariable
+from angr.utils.cowdict import DefaultChainMapCOW
+from angr.engines.light import SpOffset
+from angr.sim_variable import SimVariable
+from angr.errors import AngrRuntimeError
+from angr.storage.memory_mixins import MultiValuedMemory
+from angr.analyses.analysis import Analysis
+from angr.analyses.typehoon.typevars import TypeVariables, TypeVariable
 
 if TYPE_CHECKING:
     from angr.storage import SimMemoryObject

angr/analyses/variable_recovery/variable_recovery_fast.py

@@ -12,14 +12,14 @@ import ailment
 from ailment.expression import VirtualVariable
 
 import angr.errors
-from ...storage.memory_mixins.paged_memory.pages.multi_values import MultiValues
-from ...block import Block
-from ...errors import AngrVariableRecoveryError, SimEngineError
-from ...knowledge_plugins import Function
-from ...sim_variable import SimStackVariable, SimRegisterVariable, SimVariable, SimMemoryVariable
-from ...engines.vex.claripy.irop import vexop_to_simop
+from angr.storage.memory_mixins.paged_memory.pages.multi_values import MultiValues
+from angr.block import Block
+from angr.errors import AngrVariableRecoveryError, SimEngineError
+from angr.knowledge_plugins import Function
+from angr.sim_variable import SimStackVariable, SimRegisterVariable, SimVariable, SimMemoryVariable
+from angr.engines.vex.claripy.irop import vexop_to_simop
 from angr.analyses import ForwardAnalysis, visitors
-from ..typehoon.typevars import Equivalence, TypeVariable, TypeVariables
+from angr.analyses.typehoon.typevars import Equivalence, TypeVariable, TypeVariables
 from .variable_recovery_base import VariableRecoveryBase, VariableRecoveryStateBase
 from .engine_vex import SimEngineVRVEX
 from .engine_ail import SimEngineVRAIL

angr/analyses/veritesting.py

@@ -5,12 +5,12 @@ from functools import cmp_to_key
 
 import networkx
 
-from .. import SIM_PROCEDURES
-from .. import options as o
-from ..knowledge_base import KnowledgeBase
-from ..errors import AngrError, AngrCFGError
-from ..sim_manager import SimulationManager
-from ..utils.graph import shallow_reverse
+from angr import SIM_PROCEDURES
+from angr import options as o
+from angr.knowledge_base import KnowledgeBase
+from angr.errors import AngrError, AngrCFGError
+from angr.sim_manager import SimulationManager
+from angr.utils.graph import shallow_reverse
 from . import Analysis, CFGEmulated
 
 l = logging.getLogger(name=__name__)
@@ -624,6 +624,6 @@ from angr.analyses import AnalysesHub
 
 AnalysesHub.register_default("Veritesting", Veritesting)
 
-from ..errors import SimValueError, SimSolverModeError, SimError
-from ..sim_options import BYPASS_VERITESTING_EXCEPTIONS
+from angr.errors import SimValueError, SimSolverModeError, SimError
+from angr.sim_options import BYPASS_VERITESTING_EXCEPTIONS
 from claripy import ClaripyError

angr/analyses/vfg.py

@@ -12,10 +12,10 @@ import networkx
 from angr.utils.graph import GraphUtils
 from angr.analyses import ForwardAnalysis
 from .cfg.cfg_job_base import BlockID, FunctionKey, CFGJobBase
-from .. import sim_options
-from ..engines.procedure import ProcedureEngine
-from ..engines import SimSuccessors
-from ..errors import (
+from angr import sim_options
+from angr.engines.procedure import ProcedureEngine
+from angr.engines import SimSuccessors
+from angr.errors import (
     AngrDelayJobNotice,
     AngrSkipJobNotice,
     AngrVFGError,
@@ -26,14 +26,14 @@ from ..errors import (
     SimIRSBError,
     SimError,
 )
-from ..procedures import SIM_PROCEDURES
-from ..state_plugins.callstack import CallStack
-from ..analyses import AnalysesHub
-from ..sim_state import SimState
+from angr.procedures import SIM_PROCEDURES
+from angr.state_plugins.callstack import CallStack
+from angr.analyses import AnalysesHub
+from angr.sim_state import SimState
 from . import Analysis, CFGEmulated
 
 if TYPE_CHECKING:
-    from ..knowledge_base import KnowledgeBase
+    from angr.knowledge_base import KnowledgeBase
 
 l = logging.getLogger(name=__name__)
 
@@ -249,8 +249,8 @@ class VFGNode:
 
     def __eq__(self, o):
         return (
-            type(self) == type(o)
-            and self.key == o.key  # pylint:disable=unidiomatic-typecheck
+            type(self) is type(o)
+            and self.key == o.key
             and self.addr == o.addr
             and self.state == o.state
             and self.actions == o.actions
@@ -1508,7 +1508,7 @@ class VFG(ForwardAnalysis[SimState, VFGNode, VFGJob, BlockID], Analysis):  # pyl
                 successor_state.registers.store(arch.sp_offset, reg_sp_expr)
 
                 # Clear the return value with a TOP
-                top_si = claripy.TSI(arch.bits)
+                top_si = claripy.BVS("unnamed", arch.bits)
                 successor_state.registers.store(arch.ret_offset, top_si)
 
             if job.call_skipped:
@@ -1686,7 +1686,7 @@ class VFG(ForwardAnalysis[SimState, VFGNode, VFGJob, BlockID], Analysis):  # pyl
         reg_sp_expr = successor_state.registers.load(reg_sp_offset, size=arch.bytes, endness=arch.register_endness)
 
         reg_sp_val = successor_state.solver.min(reg_sp_expr)
-        reg_sp_si = claripy.SI(bits=successor_state.arch.bits, to_conv=reg_sp_val)
+        reg_sp_si = claripy.BVV(reg_sp_val, successor_state.arch.bits)
 
         reg_sp_val = reg_sp_val - arch.bytes  # TODO: Is it OK?
         new_stack_region_id = successor_state.memory.stack_id(successor_ip)

angr/analyses/vsa_ddg.py

@@ -5,9 +5,9 @@ from collections import defaultdict
 import networkx
 from . import Analysis, VFG
 
-from ..code_location import CodeLocation
-from ..errors import AngrDDGError
-from ..sim_variable import SimRegisterVariable, SimMemoryVariable
+from angr.code_location import CodeLocation
+from angr.errors import AngrDDGError
+from angr.sim_variable import SimRegisterVariable, SimMemoryVariable
 
 l = logging.getLogger(name=__name__)
 

angr/analyses/vtable.py

@@ -1,7 +1,7 @@
 from __future__ import annotations
 import logging
 
-from ..analyses import AnalysesHub
+from angr.analyses import AnalysesHub
 from . import Analysis, CFGFast
 
 l = logging.getLogger(name=__name__)

angr/analyses/xrefs.py

@@ -5,9 +5,9 @@ import claripy
 import pyvex
 
 from angr.analyses import visitors, ForwardAnalysis
-from ..knowledge_plugins.xrefs import XRef, XRefType
-from ..knowledge_plugins.functions.function import Function
-from ..engines.light import SimEngineLight, SimEngineLightVEXMixin
+from angr.knowledge_plugins.xrefs import XRef, XRefType
+from angr.knowledge_plugins.functions.function import Function
+from angr.engines.light import SimEngineLight, SimEngineLightVEXMixin
 from .propagator.vex_vars import VEXTmp
 from .propagator.values import Top
 from . import register_analysis, PropagatorAnalysis

angr/angrdb/__init__.py

@@ -9,3 +9,6 @@ except ImportError as err:
     ) from err
 
 from .db import AngrDB
+
+
+__all__ = ("AngrDB",)

angr/angrdb/db.py

@@ -7,8 +7,8 @@ from sqlalchemy import create_engine
 from sqlalchemy.orm import sessionmaker
 from sqlalchemy.exc import DatabaseError
 
-from ..errors import AngrCorruptDBError, AngrIncompatibleDBError, AngrDBError
-from ..project import Project
+from angr.errors import AngrCorruptDBError, AngrIncompatibleDBError, AngrDBError
+from angr.project import Project
 from .models import Base, DbInformation
 from .serializers import LoaderSerializer, KnowledgeBaseSerializer
 

angr/angrdb/serializers/__init__.py

@@ -1,3 +1,10 @@
 from __future__ import annotations
+
 from .loader import LoaderSerializer
 from .kb import KnowledgeBaseSerializer
+
+
+__all__ = (
+    "LoaderSerializer",
+    "KnowledgeBaseSerializer",
+)

angr/angrdb/serializers/cfg_model.py

@@ -1,7 +1,7 @@
 # pylint:disable=unused-import
 from __future__ import annotations
-from ..models import DbCFGModel
-from ...knowledge_plugins.cfg.cfg_model import CFGModel
+from angr.angrdb.models import DbCFGModel
+from angr.knowledge_plugins.cfg.cfg_model import CFGModel
 
 
 class CFGModelSerializer:

angr/angrdb/serializers/comments.py

@@ -1,7 +1,7 @@
 # pylint:disable=unused-import
 from __future__ import annotations
-from ..models import DbComment
-from ...knowledge_plugins.comments import Comments
+from angr.angrdb.models import DbComment
+from angr.knowledge_plugins.comments import Comments
 
 
 class CommentsSerializer:

angr/angrdb/serializers/funcs.py

@@ -1,8 +1,8 @@
 from __future__ import annotations
 from typing import TYPE_CHECKING
 
-from ...knowledge_plugins import FunctionManager, Function
-from ..models import DbFunction
+from angr.knowledge_plugins import FunctionManager, Function
+from angr.angrdb.models import DbFunction
 
 if TYPE_CHECKING:
     from angr.knowledge_base import KnowledgeBase

angr/angrdb/serializers/kb.py

@@ -1,6 +1,6 @@
 from __future__ import annotations
-from ...knowledge_base import KnowledgeBase
-from ..models import DbKnowledgeBase
+from angr.knowledge_base import KnowledgeBase
+from angr.angrdb.models import DbKnowledgeBase
 from .cfg_model import CFGModelSerializer
 from .funcs import FunctionManagerSerializer
 from .xrefs import XRefsSerializer

angr/angrdb/serializers/labels.py

@@ -1,7 +1,7 @@
 # pylint:disable=unused-import
 from __future__ import annotations
-from ..models import DbLabel
-from ...knowledge_plugins.labels import Labels
+from angr.angrdb.models import DbLabel
+from angr.knowledge_plugins.labels import Labels
 
 
 class LabelsSerializer:

angr/angrdb/serializers/loader.py

@@ -7,8 +7,8 @@ import logging
 
 import cle
 
-from ...errors import AngrCorruptDBError, AngrDBError
-from ..models import DbObject
+from angr.errors import AngrCorruptDBError, AngrDBError
+from angr.angrdb.models import DbObject
 
 
 _l = logging.getLogger(__name__)