angr 9.2.118__py3-none-win_amd64.whl → 9.2.120__py3-none-win_amd64.whl

angr/storage/memory_mixins/actions_mixin.py

@@ -1,8 +1,8 @@
 from __future__ import annotations
 import claripy
 
-from ...state_plugins.sim_action import SimActionData, SimActionObject
-from ... import sim_options as o
+from angr.state_plugins.sim_action import SimActionData, SimActionObject
+from angr import sim_options as o
 from . import MemoryMixin
 
 
@@ -46,7 +46,7 @@ class ActionsMixinHigh(MemoryMixin):
             self.state, region_type, kind, addr=addr, data=data, size=ref_size, condition=condition, fallback=fallback
         )
 
-        action.added_constraints = claripy.true
+        action.added_constraints = claripy.true()
         return action
 
     def _add_constraints(self, c, action=None, **kwargs):

angr/storage/memory_mixins/address_concretization_mixin.py

@@ -2,12 +2,12 @@ from __future__ import annotations
 import claripy
 
 from . import MemoryMixin
-from ... import sim_options as options
-from ... import concretization_strategies
-from ...sim_state_options import SimStateOptions
-from ...state_plugins.inspect import BP_BEFORE, BP_AFTER
-from ...errors import SimMergeError, SimUnsatError, SimMemoryAddressError, SimMemoryError
-from ...storage import DUMMY_SYMBOLIC_READ_VALUE
+from angr import sim_options as options
+from angr import concretization_strategies
+from angr.sim_state_options import SimStateOptions
+from angr.state_plugins.inspect import BP_BEFORE, BP_AFTER
+from angr.errors import SimMergeError, SimUnsatError, SimMemoryAddressError, SimMemoryError
+from angr.storage import DUMMY_SYMBOLIC_READ_VALUE
 
 
 class MultiwriteAnnotation(claripy.Annotation):

angr/storage/memory_mixins/bvv_conversion_mixin.py

@@ -70,4 +70,4 @@ class DataNormalizationMixin(MemoryMixin):
             return raw_to_bv()
 
 
-from ...errors import SimMemoryError
+from angr.errors import SimMemoryError

angr/storage/memory_mixins/clouseau_mixin.py

@@ -129,4 +129,4 @@ class InspectMixinHigh(MemoryMixin):
         super()._add_constraints(c, add_constraints=add_constraints, inspect=inspect, **kwargs)
 
 
-from ...state_plugins.inspect import BP_BEFORE, BP_AFTER
+from angr.state_plugins.inspect import BP_BEFORE, BP_AFTER

angr/storage/memory_mixins/convenient_mappings_mixin.py

@@ -5,8 +5,8 @@ import logging
 import claripy
 
 from angr import sim_options as options
-from ...utils.cowdict import ChainMapCOW
-from ...errors import SimMemoryError, SimMemoryMissingError
+from angr.utils.cowdict import ChainMapCOW
+from angr.errors import SimMemoryError, SimMemoryMissingError
 from . import MemoryMixin
 
 l = logging.getLogger(name=__name__)
@@ -63,7 +63,7 @@ class ConvenientMappingsMixin(MemoryMixin):
                         self._updated_mappings.remove((v, id(self._name_mapping)))
 
                 if options.REVERSE_MEMORY_HASH_MAP in self.state.options:
-                    h = old_obj.cache_key
+                    h = old_obj.hash()
                     self._mark_updated_mapping(self._hash_mapping, h)
                     self._hash_mapping[h].difference_update(range(addr, addr + size))
                     if len(self._hash_mapping[h]) == 0:
@@ -82,7 +82,7 @@ class ConvenientMappingsMixin(MemoryMixin):
 
         if options.REVERSE_MEMORY_HASH_MAP in self.state.options:
             # add the new variables to the hash->addrs mapping
-            h = data.cache_key
+            h = data.hash()
             self._mark_updated_mapping(self._hash_mapping, h)
             if h not in self._hash_mapping:
                 self._hash_mapping[h] = set()
@@ -148,7 +148,7 @@ class ConvenientMappingsMixin(MemoryMixin):
                         self._name_mapping.pop(v, None)
 
             if options.REVERSE_MEMORY_HASH_MAP in self.state.options:
-                h = hash(old_obj)
+                h = old_obj.hash()
                 self._mark_updated_mapping(self._hash_mapping, h)
                 self._hash_mapping[h].discard(actual_addr)
                 if len(self._hash_mapping[h]) == 0:
@@ -166,7 +166,7 @@ class ConvenientMappingsMixin(MemoryMixin):
 
         if options.REVERSE_MEMORY_HASH_MAP in self.state.options:
             # add the new variables to the hash->addrs mapping
-            h = hash(new_obj)
+            h = new_obj.hash()
             self._mark_updated_mapping(self._hash_mapping, h)
             if h not in self._hash_mapping:
                 self._hash_mapping[h] = set()
@@ -208,10 +208,8 @@ class ConvenientMappingsMixin(MemoryMixin):
         for e in self._hash_mapping[h]:
             try:
                 present = self.load(e, size=1)
-                if h == present.cache_key or (
-                    present.op == "Extract"
-                    and present.args[0] - present.args[1] == 7
-                    and h == present.args[2].cache_key
+                if h == present.hash() or (
+                    present.op == "Extract" and present.args[0] - present.args[1] == 7 and h == present.args[2].hash()
                 ):
                     yield e
                 else:

angr/storage/memory_mixins/default_filler_mixin.py

@@ -4,9 +4,9 @@ import logging
 import claripy
 
 from . import MemoryMixin
-from ... import sim_options as options
-from ...misc.ux import once
-from ...errors import SimMemoryMissingError
+from angr import sim_options as options
+from angr.misc.ux import once
+from angr.errors import SimMemoryMissingError
 
 l = logging.getLogger(__name__)
 

angr/storage/memory_mixins/hex_dumper_mixin.py

@@ -1,7 +1,7 @@
 from __future__ import annotations
 import string
 
-from ...errors import SimValueError
+from angr.errors import SimValueError
 from . import MemoryMixin
 import contextlib
 

angr/storage/memory_mixins/{javavm_memory/javavm_memory_mixin.py → javavm_memory_mixin.py}

@@ -5,9 +5,9 @@ import os
 
 import claripy
 
-from .... import concretization_strategies
-from ....errors import SimUnsatError, SimMemoryAddressError
-from ....engines.soot.values import (
+from angr import concretization_strategies
+from angr.errors import SimUnsatError, SimMemoryAddressError
+from angr.engines.soot.values import (
     SimSootValue_ArrayRef,
     SimSootValue_ArrayBaseRef,
     SimSootValue_InstanceFieldRef,
@@ -16,13 +16,18 @@ from ....engines.soot.values import (
     SimSootValue_StaticFieldRef,
     SimSootValue_StringRef,
 )
-from .. import MemoryMixin
+from . import MemoryMixin
 
 
 l = logging.getLogger(name=__name__)
 
 
+# pylint: disable=too-many-positional-arguments
+
+
 class JavaVmMemoryMixin(MemoryMixin):
+    """A memory mixin for JavaVM memory."""
+
     def __init__(
         self,
         memory_id="mem",
@@ -38,7 +43,7 @@ class JavaVmMemoryMixin(MemoryMixin):
 
         self._stack = [] if stack is None else stack
         # delayed import
-        from .. import KeyValueMemory
+        from . import KeyValueMemory  # pylint: disable=import-outside-toplevel
 
         self.heap = KeyValueMemory("mem") if heap is None else heap
         self.vm_static_table = KeyValueMemory("mem") if vm_static_table is None else vm_static_table
@@ -81,7 +86,7 @@ class JavaVmMemoryMixin(MemoryMixin):
         else:
             l.error("Unknown addr type %s", addr)
 
-    def load(self, addr, frame=0, none_if_missing=False):  # pylint: disable=arguments-differ
+    def load(self, addr, frame=0, none_if_missing=False):  # pylint: disable=arguments-differ,arguments-renamed
         if type(addr) is SimSootValue_Local:
             cstack = self._stack[-1 + (-1 * frame)]
             return cstack.load(addr.id, none_if_missing=none_if_missing)
@@ -118,7 +123,7 @@ class JavaVmMemoryMixin(MemoryMixin):
         return None
 
     def push_stack_frame(self):
-        from .. import KeyValueMemory
+        from . import KeyValueMemory  # pylint: disable=import-outside-toplevel
 
         self._stack.append(KeyValueMemory("mem"))
 
@@ -379,11 +384,9 @@ class JavaVmMemoryMixin(MemoryMixin):
     def merge(self, others, merge_conditions, common_ancestor=None):  # pylint: disable=unused-argument
         l.warning("Merging is not implemented for JavaVM memory!")
 
-    def widen(self, others):  # pylint: disable=unused-argument
+    def widen(self, others):  # pylint: disable=no-self-use,unused-argument
         l.warning("Widening is not implemented for JavaVM memory!")
 
-    def _find(
-        self, addr, what, max_search=None, max_symbolic_bytes=None, default=None
-    ):  # pylint: disable=unused-argument
+    # pylint: disable=no-self-use,unused-argument
+    def _find(self, addr, what, max_search=None, max_symbolic_bytes=None, default=None):
         l.warning("Find is not implemented for JavaVM memory!")
-        return

angr/storage/memory_mixins/{keyvalue_memory/keyvalue_memory_mixin.py → keyvalue_memory_mixin.py}

@@ -1,8 +1,11 @@
 from __future__ import annotations
-from .. import MemoryMixin
+
+from . import MemoryMixin
 
 
 class TypedVariable:
+    """TypedVariable is a simple class that holds a value and a type."""
+
     __slots__ = (
         "type",
         "value",
@@ -14,18 +17,20 @@ class TypedVariable:
 
 
 class KeyValueMemoryMixin(MemoryMixin):
+    """KeyValueMemoryMixin is a mixin that provides a simple key-value store for memory."""
+
     def __init__(self, *args, **kwargs):
         super().__init__(*args, **kwargs)
 
         self._store = {}
 
-    def load(self, key, none_if_missing=False, **kwargs):
-        if none_if_missing and key not in self._store:
+    def load(self, addr, size=None, none_if_missing=False, **kwargs):  # pylint: disable=unused-argument
+        if none_if_missing and addr not in self._store:
             return None
-        return self._store[key].value
+        return self._store[addr].value
 
-    def store(self, key, data, type_=None, **kwargs):
-        self._store[key] = TypedVariable(type_, data)
+    def store(self, addr, data, type_=None, **kwargs):
+        self._store[addr] = TypedVariable(type_, data)
 
     @MemoryMixin.memo
     def copy(self, memo):

angr/storage/memory_mixins/multi_value_merger_mixin.py

@@ -41,16 +41,16 @@ class MultiValueMergerMixin(MemoryMixin):
                 ret_val = self._top_func(merged_size * self.state.arch.byte_width)
             else:
                 # strip annotations from each value and see how many raw values there are in total
-                # We have to use cache_key to determine uniqueness here, because if __hash__ collides,
+                # We have to use hash manually to determine uniqueness here, because if __hash__ collides,
                 # python implicitly calls __eq__ to determine if the two objects are actually the same
                 # and that just results in a new AST for a BV. Python then tries to convert that AST to a bool
                 # which fails with the safeguard in claripy.ast.bool.Bool.__bool__.
-                stripped_values_set = {v.clear_annotations().cache_key for v in values_set}
-                if len(stripped_values_set) > 1:
+                stripped_values_dict = {v.hash(): v for v in values_set}
+                if len(stripped_values_dict) > 1:
                     ret_val = self._top_func(merged_size * self.state.arch.byte_width)
                 else:
-                    # Get the AST back from the cache_key
-                    ret_val = next(iter(stripped_values_set)).ast
+                    # Get the AST back from the hash dict
+                    ret_val = stripped_values_dict[next(iter(stripped_values_dict))]
 
             # migrate annotations
             annotations = []

angr/storage/memory_mixins/name_resolution_mixin.py

@@ -15,7 +15,7 @@ class NameResolutionMixin(MemoryMixin):
 
     def _resolve_location_name(self, name, is_write=False):
         # Delayed load so SimMemory does not rely on SimEngines
-        from ...engines.vex.claripy.ccall import _get_flags
+        from angr.engines.vex.claripy.ccall import _get_flags
 
         if self.category == "reg":
             if self.state.arch.name in ("X86", "AMD64"):
@@ -64,4 +64,4 @@ class NameResolutionMixin(MemoryMixin):
         return super().load(addr, size=size, **kwargs)
 
 
-from ...errors import SimMemoryError
+from angr.errors import SimMemoryError

angr/storage/memory_mixins/paged_memory/paged_memory_mixin.py

@@ -9,7 +9,7 @@ import claripy
 
 from angr.storage.memory_mixins import MemoryMixin
 from angr.storage.memory_mixins.paged_memory.pages import PageType, ListPage, UltraPage, MVListPage
-from ....errors import SimMemoryError
+from angr.errors import SimMemoryError
 
 # yeet
 ffi = cffi.FFI()

angr/storage/memory_mixins/paged_memory/paged_memory_multivalue_mixin.py

@@ -1,5 +1,5 @@
 from __future__ import annotations
-from .. import MemoryMixin
+from angr.storage.memory_mixins import MemoryMixin
 
 
 class PagedMemoryMultiValueMixin(MemoryMixin):

angr/storage/memory_mixins/paged_memory/pages/__init__.py

@@ -30,3 +30,18 @@ PageType = typing.TypeVar("PageType", bound=PageBase)
 from .list_page import ListPage
 from .mv_list_page import MVListPage
 from .ultra_page import UltraPage
+
+
+__all__ = (
+    "CooperationBase",
+    "MemoryObjectMixin",
+    "ISPOMixin",
+    "RefcountMixin",
+    "PermissionsMixin",
+    "HistoryTrackingMixin",
+    "PageBase",
+    "PageType",
+    "ListPage",
+    "MVListPage",
+    "UltraPage",
+)

angr/storage/memory_mixins/paged_memory/pages/mv_list_page.py

@@ -5,7 +5,7 @@ from typing import Union, Any
 from collections.abc import Callable
 
 from angr.utils.dynamic_dictlist import DynamicDictList
-from .....storage.memory_object import SimMemoryObject, SimLabeledMemoryObject
+from angr.storage.memory_object import SimMemoryObject, SimLabeledMemoryObject
 from . import PageBase
 from .cooperation import MemoryObjectSetMixin
 

angr/storage/memory_mixins/paged_memory/pages/ultra_page.py

@@ -8,7 +8,7 @@ from sortedcontainers import SortedDict
 
 import claripy
 
-from .....errors import SimMemoryError
+from angr.errors import SimMemoryError
 from . import PageBase
 from .cooperation import MemoryObjectMixin, SimMemoryObject
 
@@ -464,7 +464,7 @@ class UltraPage(MemoryObjectMixin, PageBase):
             if replaced_object is not None:
                 self._replace_memory_object(mo, replaced_object, memory=memory)
 
-    def _replace_memory_object(self, old: SimMemoryObject, new_content: claripy.Bits, memory=None):
+    def _replace_memory_object(self, old: SimMemoryObject, new_content: claripy.ast.Bits, memory=None):
         """
         Replaces the memory object `old` with a new memory object containing `new_content`.
 

angr/storage/memory_mixins/paged_memory/stack_allocation_mixin.py

@@ -2,8 +2,8 @@ from __future__ import annotations
 import logging
 
 from .paged_memory_mixin import PagedMemoryMixin
-from ....errors import SimSegfaultException, SimMemoryError
-from ....sim_options import STRICT_PAGE_ACCESS
+from angr.errors import SimSegfaultException, SimMemoryError
+from angr.sim_options import STRICT_PAGE_ACCESS
 
 l = logging.getLogger(__name__)
 

angr/storage/memory_mixins/regioned_memory/__init__.py

@@ -1,7 +1,17 @@
 from __future__ import annotations
+
 from .regioned_memory_mixin import RegionedMemoryMixin
 from .region_category_mixin import RegionCategoryMixin
 from .static_find_mixin import StaticFindMixin
 from .abstract_merger_mixin import AbstractMergerMixin
 from .region_meta_mixin import MemoryRegionMetaMixin
 from .regioned_address_concretization_mixin import RegionedAddressConcretizationMixin
+
+__all__ = (
+    "RegionedMemoryMixin",
+    "RegionCategoryMixin",
+    "StaticFindMixin",
+    "AbstractMergerMixin",
+    "MemoryRegionMetaMixin",
+    "RegionedAddressConcretizationMixin",
+)

angr/storage/memory_mixins/regioned_memory/abstract_merger_mixin.py

@@ -5,7 +5,7 @@ from collections.abc import Iterable
 from typing import Any
 
 
-from .. import MemoryMixin
+from angr.storage.memory_mixins import MemoryMixin
 
 l = logging.getLogger(name=__name__)
 

angr/storage/memory_mixins/regioned_memory/region_category_mixin.py

@@ -1,5 +1,5 @@
 from __future__ import annotations
-from .. import MemoryMixin
+from angr.storage.memory_mixins import MemoryMixin
 
 
 class RegionCategoryMixin(MemoryMixin):

angr/storage/memory_mixins/regioned_memory/region_data.py

@@ -3,8 +3,8 @@ from sortedcontainers import SortedDict
 
 import claripy
 
-from ....errors import SimRegionMapError
-from ....state_plugins import SimStatePlugin
+from angr.errors import SimRegionMapError
+from angr.state_plugins import SimStatePlugin
 
 
 class AddressWrapper:

angr/storage/memory_mixins/regioned_memory/region_meta_mixin.py

@@ -2,7 +2,7 @@ from __future__ import annotations
 import copy
 from typing import Any
 
-from .. import MemoryMixin
+from angr.storage.memory_mixins import MemoryMixin
 
 
 class Segment:

angr/storage/memory_mixins/regioned_memory/regioned_address_concretization_mixin.py

@@ -3,10 +3,10 @@ from collections.abc import Generator
 
 import claripy
 
-from ....sim_options import HYBRID_SOLVER, APPROXIMATE_FIRST
-from .... import concretization_strategies
-from ....errors import SimMergeError, SimMemoryAddressError
-from .. import MemoryMixin
+from angr.sim_options import HYBRID_SOLVER, APPROXIMATE_FIRST
+from angr import concretization_strategies
+from angr.errors import SimMergeError, SimMemoryAddressError
+from angr.storage.memory_mixins import MemoryMixin
 from .abstract_address_descriptor import AbstractAddressDescriptor
 from .region_data import AddressWrapper
 

angr/storage/memory_mixins/regioned_memory/regioned_memory_mixin.py

@@ -8,20 +8,15 @@ import claripy
 from claripy.annotation import RegionAnnotation
 from claripy.ast import Bool, Bits, BV
 
-from ....sim_options import (
-    AVOID_MULTIVALUED_READS,
-    CONSERVATIVE_READ_STRATEGY,
-    KEEP_MEMORY_READS_DISCRETE,
-    CONSERVATIVE_WRITE_STRATEGY,
-)
-from ....state_plugins.sim_action_object import _raw_ast
-from ....errors import SimMemoryError, SimAbstractMemoryError
-from .. import MemoryMixin
+from angr.sim_options import AVOID_MULTIVALUED_READS, CONSERVATIVE_READ_STRATEGY, CONSERVATIVE_WRITE_STRATEGY
+from angr.state_plugins.sim_action_object import _raw_ast
+from angr.errors import SimMemoryError, SimAbstractMemoryError
+from angr.storage.memory_mixins import MemoryMixin
 from .region_data import AddressWrapper, RegionMap
 from .abstract_address_descriptor import AbstractAddressDescriptor
 
 if TYPE_CHECKING:
-    from ....sim_state import SimState
+    from angr.sim_state import SimState
 
 
 _l = logging.getLogger(name=__name__)
@@ -59,7 +54,7 @@ class RegionedMemoryMixin(MemoryMixin):
 
         if regioned_memory_cls is None:
             # delayed import
-            from .. import RegionedMemory  # pylint:disable=import-outside-toplevel
+            from angr.storage.memory_mixins import RegionedMemory  # pylint:disable=import-outside-toplevel
 
             regioned_memory_cls = RegionedMemory
 
@@ -126,13 +121,7 @@ class RegionedMemoryMixin(MemoryMixin):
                 **kwargs,
             )
 
-            if val is None:
-                if KEEP_MEMORY_READS_DISCRETE in self.state.options:
-                    val = self.state.solver.DSIS(to_conv=new_val, max_card=100000)
-                else:
-                    val = new_val
-            else:
-                val = val.union(new_val)
+            val = new_val if val is None else val.union(new_val)
 
         if val is None:
             # address_wrappers is empty - we cannot concretize the address in static mode.
@@ -358,7 +347,6 @@ class RegionedMemoryMixin(MemoryMixin):
 
         :param addr:
         :param is_write:
-        :param convert_to_valueset:
         :param target_region:
         :return:
         """

angr/storage/memory_mixins/regioned_memory/static_find_mixin.py

@@ -1,7 +1,7 @@
 from __future__ import annotations
 import claripy
 
-from ..smart_find_mixin import SmartFindMixin
+from angr.storage.memory_mixins.smart_find_mixin import SmartFindMixin
 
 
 class StaticFindMixin(SmartFindMixin):  # pylint:disable=abstract-method

angr/storage/memory_mixins/simple_interface_mixin.py

@@ -2,7 +2,7 @@ from __future__ import annotations
 import claripy
 
 from . import MemoryMixin
-from ...errors import SimMemoryError
+from angr.errors import SimMemoryError
 
 
 class SimpleInterfaceMixin(MemoryMixin):

angr/storage/memory_mixins/simplification_mixin.py

@@ -1,6 +1,6 @@
 from __future__ import annotations
 from . import MemoryMixin
-from ... import sim_options as options
+from angr import sim_options as options
 
 
 class SimplificationMixin(MemoryMixin):

angr/storage/memory_mixins/size_resolution_mixin.py

@@ -4,7 +4,7 @@ import logging
 import claripy
 
 from . import MemoryMixin
-from ...errors import SimMemoryLimitError, SimMemoryError, SimUnsatError
+from angr.errors import SimMemoryLimitError, SimMemoryError, SimUnsatError
 
 l = logging.getLogger(__name__)
 
@@ -136,7 +136,7 @@ class SizeConcretizationMixin(MemoryMixin):
             conc_sizes = [min(cs, self._max_symbolic_size) for cs in conc_sizes]
 
         if condition is None:
-            condition = claripy.true
+            condition = claripy.true()
         for conc_size in conc_sizes:
             if conc_size == 0:
                 continue

angr/storage/memory_mixins/slotted_memory.py

@@ -3,7 +3,7 @@ import claripy
 
 from . import MemoryMixin
 from .paged_memory.pages.ispo_mixin import ISPOMixin
-from ...errors import SimMergeError
+from angr.errors import SimMergeError
 
 
 class SlottedMemoryMixin(MemoryMixin):

angr/storage/memory_mixins/smart_find_mixin.py

@@ -2,7 +2,7 @@ from __future__ import annotations
 import claripy
 
 from . import MemoryMixin
-from ...errors import SimSegfaultException
+from angr.errors import SimSegfaultException
 
 
 class SmartFindMixin(MemoryMixin):
@@ -99,7 +99,7 @@ class SmartFindMixin(MemoryMixin):
         able to handle wide characters
         """
         if condition is None:
-            condition = claripy.true
+            condition = claripy.true()
         chunk = None
         chunk_progress = chunk_size
 
@@ -139,7 +139,7 @@ class SmartFindMixin(MemoryMixin):
 
     def _find_condition(self, target_addr):  # pylint:disable=unused-argument,no-self-use
         # TODO: fill this in in order to make each load have the correct condition associated with it
-        return claripy.true
+        return claripy.true()
 
     def _find_compare(self, element, target):
         comparison = element == target

angr/storage/memory_mixins/underconstrained_mixin.py

@@ -3,7 +3,7 @@ import claripy
 import logging
 
 from . import MemoryMixin
-from ... import sim_options as o
+from angr import sim_options as o
 
 l = logging.getLogger(__name__)
 

angr/storage/memory_mixins/unwrapper_mixin.py

@@ -24,4 +24,4 @@ class UnwrapperMixin(MemoryMixin):
         return super().copy_contents(_raw_ast(dst), _raw_ast(src), _raw_ast(size), _raw_ast(condition), **kwargs)
 
 
-from ...state_plugins.sim_action_object import _raw_ast
+from angr.state_plugins.sim_action_object import _raw_ast