angr 9.2.118__py3-none-manylinux2014_x86_64.whl → 9.2.120__py3-none-manylinux2014_x86_64.whl

angr/analyses/decompiler/dephication/seqnode_dephication.py

@@ -10,7 +10,7 @@ from ailment.expression import VirtualVariable, Phi
 from angr.utils.ail import is_phi_assignment
 from angr.knowledge_plugins.functions import Function
 from angr.analyses import register_analysis
-from angr.analyses.decompiler.structuring.structurer_nodes import SequenceNode
+from angr.analyses.decompiler.structuring.structurer_nodes import SequenceNode, LoopNode
 from angr.analyses.decompiler.sequence_walker import SequenceWalker
 from .dephication_base import DephicationBase
 from .rewriting_engine import SimEngineDephiRewriting
@@ -57,6 +57,8 @@ class SeqNodeRewriter(SequenceWalker):
         super().__init__(
             handlers={
                 Block: self._handle_Block,
+                # statement handlers
+                Assignment: self._handle_Assignment,
             }
         )
 
@@ -68,6 +70,9 @@ class SeqNodeRewriter(SequenceWalker):
             # nothing is changed during rewriting
             self.output = seq_node
 
+    def _handle_Assignment(self, stmt: Assignment, **kwargs) -> Assignment:  # pylint:disable=unused-argument
+        return self.engine._handle_Assignment(stmt)
+
     def _handle_Block(self, block: Block, **kwargs) -> Block | None:  # pylint:disable=unused-argument
         self.engine.out_block = None
         self.engine.process(None, block=block)
@@ -78,6 +83,19 @@ class SeqNodeRewriter(SequenceWalker):
             return out
         return None
 
+    def _handle_Loop(self, node: LoopNode, **kwargs):
+        new_loop = super()._handle_Loop(node, **kwargs)
+        changed = False
+        if new_loop is None:
+            new_loop = node
+        else:
+            changed = True
+
+        if is_phi_assignment(new_loop.initializer):
+            changed = True
+            new_loop.initializer = None
+        return new_loop if changed else None
+
 
 class SeqNodeDephication(DephicationBase):
     """

angr/analyses/decompiler/jumptable_entry_condition_rewriter.py

@@ -16,7 +16,7 @@ class JumpTableEntryConditionRewriter(SequenceWalker):
 
     def _process_expr(self, expr):
         if expr in self._jumptable_entry_conds:
-            return claripy.true
+            return claripy.true()
 
         new_args = []
         replaced = False

angr/analyses/decompiler/optimization_passes/__init__.py

@@ -1,6 +1,5 @@
 # pylint:disable=import-outside-toplevel
 from __future__ import annotations
-from typing import Optional, Union
 
 from archinfo import Arch
 
@@ -33,33 +32,33 @@ from .call_stmt_rewriter import CallStatementRewriter
 from .duplication_reverter import DuplicationReverter
 
 # order matters!
-_all_optimization_passes = [
-    (RegisterSaveAreaSimplifier, True),
-    (StackCanarySimplifier, True),
-    (WinStackCanarySimplifier, True),
-    (BasePointerSaveSimplifier, True),
-    (DivSimplifier, True),
-    (MultiSimplifier, True),
-    (ModSimplifier, True),
-    (ConstantDereferencesSimplifier, True),
-    (RetAddrSaveSimplifier, True),
-    (X86GccGetPcSimplifier, True),
-    (ITERegionConverter, True),
-    (ITEExprConverter, True),
-    (ExprOpSwapper, True),
-    (ReturnDuplicatorHigh, True),
-    (DeadblockRemover, True),
-    (SwitchDefaultCaseDuplicator, True),
-    (ConstPropOptReverter, True),
-    (DuplicationReverter, True),
-    (LoweredSwitchSimplifier, True),
-    (ReturnDuplicatorLow, True),
-    (ReturnDeduplicator, True),
-    (CodeMotionOptimization, False),
-    (CrossJumpReverter, True),
-    (FlipBooleanCmp, True),
-    (InlinedStringTransformationSimplifier, True),
-    (CallStatementRewriter, True),
+ALL_OPTIMIZATION_PASSES = [
+    RegisterSaveAreaSimplifier,
+    StackCanarySimplifier,
+    WinStackCanarySimplifier,
+    BasePointerSaveSimplifier,
+    DivSimplifier,
+    MultiSimplifier,
+    ModSimplifier,
+    ConstantDereferencesSimplifier,
+    RetAddrSaveSimplifier,
+    X86GccGetPcSimplifier,
+    ITERegionConverter,
+    ITEExprConverter,
+    ExprOpSwapper,
+    ReturnDuplicatorHigh,
+    DeadblockRemover,
+    SwitchDefaultCaseDuplicator,
+    ConstPropOptReverter,
+    DuplicationReverter,
+    LoweredSwitchSimplifier,
+    ReturnDuplicatorLow,
+    ReturnDeduplicator,
+    CodeMotionOptimization,
+    CrossJumpReverter,
+    FlipBooleanCmp,
+    InlinedStringTransformationSimplifier,
+    CallStatementRewriter,
 ]
 
 # these passes may duplicate code to remove gotos or improve the structure of the graph
@@ -78,7 +77,7 @@ def get_optimization_passes(arch, platform):
         platform = "windows"  # sigh
 
     passes = []
-    for pass_, _ in _all_optimization_passes:
+    for pass_ in ALL_OPTIMIZATION_PASSES:
         if (pass_.ARCHES is None or arch in pass_.ARCHES) and (
             pass_.PLATFORMS is None or platform is None or platform in pass_.PLATFORMS
         ):
@@ -87,28 +86,41 @@ def get_optimization_passes(arch, platform):
     return passes
 
 
-def get_default_optimization_passes(arch: Arch | str, platform: str | None, enable_opts=None, disable_opts=None):
-    if isinstance(arch, Arch):
-        arch = arch.name
-
-    if platform is not None:
-        platform = platform.lower()
-    if platform == "win32":
-        platform = "windows"  # sigh
-
-    passes = []
-    enable_opts = enable_opts or []
-    disable_opts = disable_opts or []
-    for pass_, default in _all_optimization_passes:
-        if (not default and pass_ not in enable_opts) or pass_ in disable_opts:
-            continue
-        if (pass_.ARCHES is None or arch in pass_.ARCHES) and (
-            pass_.PLATFORMS is None or platform is None or platform in pass_.PLATFORMS
-        ):
-            passes.append(pass_)
-
-    return passes
-
-
-def register_optimization_pass(opt_pass, enable_by_default: bool):
-    _all_optimization_passes.append((opt_pass, enable_by_default))
+def register_optimization_pass(opt_pass):
+    ALL_OPTIMIZATION_PASSES.append(opt_pass)
+
+
+__all__ = (
+    "OptimizationPassStage",
+    "StackCanarySimplifier",
+    "BasePointerSaveSimplifier",
+    "ExprOpSwapper",
+    "ITERegionConverter",
+    "ITEExprConverter",
+    "LoweredSwitchSimplifier",
+    "MultiSimplifier",
+    "DivSimplifier",
+    "ModSimplifier",
+    "ReturnDuplicatorLow",
+    "ReturnDuplicatorHigh",
+    "ConstantDereferencesSimplifier",
+    "RegisterSaveAreaSimplifier",
+    "RetAddrSaveSimplifier",
+    "X86GccGetPcSimplifier",
+    "FlipBooleanCmp",
+    "ReturnDeduplicator",
+    "WinStackCanarySimplifier",
+    "CrossJumpReverter",
+    "CodeMotionOptimization",
+    "SwitchDefaultCaseDuplicator",
+    "DeadblockRemover",
+    "InlinedStringTransformationSimplifier",
+    "ConstPropOptReverter",
+    "CallStatementRewriter",
+    "DuplicationReverter",
+    "ALL_OPTIMIZATION_PASSES",
+    "DUPLICATING_OPTS",
+    "CONDENSING_OPTS",
+    "get_optimization_passes",
+    "register_optimization_pass",
+)

angr/analyses/decompiler/optimization_passes/const_derefs.py

@@ -7,7 +7,7 @@ from ailment import Block, AILBlockWalker
 from ailment.expression import Load, Const, BinaryOp, UnaryOp
 from ailment.statement import Statement, Assignment, Call, ConditionalJump
 
-from ..ailgraph_walker import AILGraphWalker
+from angr.analyses.decompiler.ailgraph_walker import AILGraphWalker
 from .optimization_pass import OptimizationPass, OptimizationPassStage
 
 if TYPE_CHECKING:

angr/analyses/decompiler/optimization_passes/const_prop_reverter.py

@@ -11,9 +11,9 @@ from ailment.statement import Call, Statement, ConditionalJump, Assignment, Stor
 from ailment.expression import Convert, Register, Expression
 
 from .optimization_pass import OptimizationPass, OptimizationPassStage
-from ..structuring import SAILRStructurer, DreamStructurer
-from ....knowledge_plugins.key_definitions.atoms import MemoryLocation
-from ....knowledge_plugins.key_definitions.constants import OP_BEFORE
+from angr.analyses.decompiler.structuring import SAILRStructurer, DreamStructurer
+from angr.knowledge_plugins.key_definitions.atoms import MemoryLocation
+from angr.knowledge_plugins.key_definitions.constants import OP_BEFORE
 
 
 _l = logging.getLogger(__name__)

angr/analyses/decompiler/optimization_passes/cross_jump_reverter.py

@@ -6,7 +6,7 @@ import logging
 import inspect
 
 from .optimization_pass import OptimizationPassStage, StructuringOptimizationPass
-from ..counters import AILBlockCallCounter
+from angr.analyses.decompiler.counters import AILBlockCallCounter
 
 l = logging.getLogger(__name__)
 

angr/analyses/decompiler/optimization_passes/duplication_reverter/__init__.py

@@ -1,2 +1,5 @@
 from __future__ import annotations
+
 from .duplication_reverter import DuplicationReverter
+
+__all__ = ("DuplicationReverter",)

angr/analyses/decompiler/optimization_passes/duplication_reverter/ail_merge_graph.py

@@ -140,7 +140,7 @@ class AILMergeGraph:
         self.starts = []
         self.original_ends = []
 
-    def create_conditionless_graph(self, starting_blocks: list[Block], graph_lcs):
+    def create_conditionless_graph(self, starting_blocks: list[Block], graph_lcs) -> dict[Block, Block] | None:
         # get all the original blocks (reverted from the LCS) and their split blocks.
         # split-blocks are blocks that need to be split at some stmt index to make the two blocks
         # equal across both graphs. At a highlevel, the first block in both matching graphs either need
@@ -180,9 +180,12 @@ class AILMergeGraph:
         # we create a new graph, full of the original blocks of the base, with blocks
         # that should be split replaced.
         # this graph is only the initial merge_graph needed, where only the blocks
-        self.graph, update_blocks = self.clone_graph_replace_splits(
-            nx.subgraph(self.original_graph, self.original_blocks[merge_base]), base_to_split
-        )
+        subgraph = nx.subgraph(self.original_graph, self.original_blocks[merge_base])
+        # ensure all base blocks are within the subgraph
+        for block in base_to_split:
+            if block not in subgraph:
+                return None
+        self.graph, update_blocks = self.clone_graph_replace_splits(subgraph, base_to_split)
         self._update_all_split_refs(update_blocks)
         for update_block, new_block in update_blocks.items():
             if update_block in starting_blocks:

angr/analyses/decompiler/optimization_passes/duplication_reverter/duplication_reverter.py

@@ -22,13 +22,13 @@ from .utils import (
     correct_jump_targets,
     deepcopy_ail_anyjump,
 )
-from ..optimization_pass import StructuringOptimizationPass
-from ...block_io_finder import BlockIOFinder
-from ...block_similarity import is_similar, index_of_similar_stmts, longest_ail_subseq
-from ...utils import to_ail_supergraph, remove_labels
-from ...counters.boolean_counter import BooleanCounter
-from .....knowledge_plugins.key_definitions.atoms import MemoryLocation
-from .....utils.graph import dominates
+from angr.analyses.decompiler.optimization_passes.optimization_pass import StructuringOptimizationPass
+from angr.analyses.decompiler.block_io_finder import BlockIOFinder
+from angr.analyses.decompiler.block_similarity import is_similar, index_of_similar_stmts, longest_ail_subseq
+from angr.analyses.decompiler.utils import to_ail_supergraph, remove_labels
+from angr.analyses.decompiler.counters.boolean_counter import BooleanCounter
+from angr.knowledge_plugins.key_definitions.atoms import MemoryLocation
+from angr.utils.graph import dominates
 
 _l = logging.getLogger(name=__name__)
 
@@ -51,7 +51,7 @@ class DuplicationReverter(StructuringOptimizationPass):
             strictly_less_gotos=False,
             recover_structure_fails=True,
             must_improve_rel_quality=True,
-            max_opt_iters=30,
+            max_opt_iters=5,
             simplify_ail=True,
             require_gotos=True,
             readd_labels=True,
@@ -679,6 +679,10 @@ class DuplicationReverter(StructuringOptimizationPass):
         ail_merge_graph = AILMergeGraph(original_graph=graph)
         # some blocks in originals may update during this time (if-statements can change)
         update_blocks = ail_merge_graph.create_conditionless_graph(blocks, graph_lcs)
+        if update_blocks is None:
+            # failed to create the condition-less graph
+            self.candidate_blacklist.add(tuple(blocks))
+            raise SAILRSemanticError("Failed to create a condition-less graph, this analysis must skip it")
 
         #
         # SPECIAL CASE: the merged graph contains only 1 node and no splits
@@ -1170,9 +1174,9 @@ class DuplicationReverter(StructuringOptimizationPass):
             entry_blocks = [node for node in graph.nodes if graph.in_degree(node) == 0]
             entry_block = None if len(entry_blocks) != 1 else entry_blocks[0]
 
-            self._entry_node_cache[graph] = entry_block
             if entry_block is None:
                 return None
+            self._entry_node_cache[graph] = entry_block
 
         entry_blk = self._entry_node_cache[graph]
 

angr/analyses/decompiler/optimization_passes/duplication_reverter/similarity.py

@@ -7,7 +7,7 @@ import networkx as nx
 from ailment.block import Block
 
 from .utils import bfs_list_blocks
-from ...block_similarity import longest_ail_subseq, is_similar
+from angr.analyses.decompiler.block_similarity import longest_ail_subseq, is_similar
 
 _l = logging.getLogger(name=__name__)
 

angr/analyses/decompiler/optimization_passes/duplication_reverter/utils.py

@@ -9,7 +9,7 @@ from ailment.block import Block
 from ailment.statement import Statement, ConditionalJump, Jump
 
 from .errors import UnsupportedAILNodeError
-from ...structuring.structurer_nodes import IncompleteSwitchCaseHeadStatement
+from angr.analyses.decompiler.structuring.structurer_nodes import IncompleteSwitchCaseHeadStatement
 
 
 _l = logging.getLogger(name=__name__)

angr/analyses/decompiler/optimization_passes/engine_base.py

@@ -4,8 +4,8 @@ import logging
 
 from ailment import Expr, Stmt
 
-from ....engines.light import SimEngineLightAILMixin
-from ....engines.light import SimEngineLight
+from angr.engines.light import SimEngineLightAILMixin
+from angr.engines.light import SimEngineLight
 
 _l = logging.getLogger(name=__name__)
 

angr/analyses/decompiler/optimization_passes/expr_op_swapper.py

@@ -7,8 +7,8 @@ from ailment.block import Block as AILBlock
 from ailment.statement import Statement
 from ailment.expression import Expression, BinaryOp
 
-from ..sequence_walker import SequenceWalker
-from ..ail_simplifier import AILBlockWalker
+from angr.analyses.decompiler.sequence_walker import SequenceWalker
+from angr.analyses.decompiler.ail_simplifier import AILBlockWalker
 from .optimization_pass import SequenceOptimizationPass, OptimizationPassStage
 
 if TYPE_CHECKING:

angr/analyses/decompiler/optimization_passes/flip_boolean_cmp.py

@@ -5,9 +5,9 @@ from typing import Any
 import ailment
 from ailment.expression import Op
 
-from ..structuring.structurer_nodes import ConditionNode
-from ..utils import structured_node_is_simple_return, sequence_to_statements
-from ..sequence_walker import SequenceWalker
+from angr.analyses.decompiler.structuring.structurer_nodes import ConditionNode
+from angr.analyses.decompiler.utils import structured_node_is_simple_return, sequence_to_statements
+from angr.analyses.decompiler.sequence_walker import SequenceWalker
 from .optimization_pass import SequenceOptimizationPass, OptimizationPassStage
 
 
@@ -79,7 +79,7 @@ class FlipBooleanCmp(SequenceOptimizationPass):
 
     def __init__(self, func, flip_size=10, **kwargs):
         super().__init__(func, **kwargs)
-        self._graph = kwargs.get("graph", None)
+        self._graph = kwargs.get("graph")
         self._flip_size = flip_size
         self.analyze()
 

angr/analyses/decompiler/optimization_passes/inlined_string_transformation_simplifier.py

@@ -60,12 +60,12 @@ class InlinedStringTransformationState:
     def _get_weakref(self):
         return self
 
-    def reg_store(self, reg: Register, value: claripy.Bits) -> None:
+    def reg_store(self, reg: Register, value: claripy.ast.Bits) -> None:
         self.registers.store(
             reg.reg_offset, value, size=value.size() // self.arch.byte_width, endness=str(self.arch.register_endness)
         )
 
-    def reg_load(self, reg: Register) -> claripy.Bits | None:
+    def reg_load(self, reg: Register) -> claripy.ast.Bits | None:
         try:
             return self.registers.load(
                 reg.reg_offset, size=reg.size, endness=self.arch.register_endness, fill_missing=False
@@ -73,19 +73,19 @@ class InlinedStringTransformationState:
         except SimMemoryMissingError:
             return None
 
-    def mem_store(self, addr: int, value: claripy.Bits, endness: str) -> None:
+    def mem_store(self, addr: int, value: claripy.ast.Bits, endness: str) -> None:
         self.memory.store(addr, value, size=value.size() // self.arch.byte_width, endness=endness)
 
-    def mem_load(self, addr: int, size: int, endness) -> claripy.Bits | None:
+    def mem_load(self, addr: int, size: int, endness) -> claripy.ast.Bits | None:
         try:
             return self.memory.load(addr, size=size, endness=str(endness), fill_missing=False)
         except SimMemoryMissingError:
             return None
 
-    def vvar_store(self, vvar: VirtualVariable, value: claripy.Bits | None) -> None:
+    def vvar_store(self, vvar: VirtualVariable, value: claripy.ast.Bits | None) -> None:
         self.virtual_variables[vvar.varid] = value
 
-    def vvar_load(self, vvar: VirtualVariable) -> claripy.Bits | None:
+    def vvar_load(self, vvar: VirtualVariable) -> claripy.ast.Bits | None:
         if vvar.varid in self.virtual_variables:
             return self.virtual_variables[vvar.varid]
         return None
@@ -109,7 +109,7 @@ class InlinedStringTransformationAILEngine(SimEngineLightAILMixin):
         self.MASK = 0xFFFF_FFFF if self.arch.bits == 32 else 0xFFFF_FFFF_FFFF_FFFF
 
         state = InlinedStringTransformationState(project)
-        self.stack_accesses: defaultdict[int, list[tuple[str, CodeLocation, claripy.Bits]]] = defaultdict(list)
+        self.stack_accesses: defaultdict[int, list[tuple[str, CodeLocation, claripy.ast.Bits]]] = defaultdict(list)
         self.finished: bool = False
 
         i = 0
@@ -140,7 +140,7 @@ class InlinedStringTransformationAILEngine(SimEngineLightAILMixin):
             if v0_and_type is not None:
                 v0 = v0_and_type[0]
                 v1 = self._expr(addr.operands[1])
-                if isinstance(v1, claripy.Bits) and v1.concrete:
+                if isinstance(v1, claripy.ast.Bits) and v1.concrete:
                     return (v0 + v1.concrete_value) & self.MASK, "stack"
         return None
 
@@ -148,7 +148,7 @@ class InlinedStringTransformationAILEngine(SimEngineLightAILMixin):
         if isinstance(stmt.dst, VirtualVariable):
             if stmt.dst.was_reg:
                 val = self._expr(stmt.src)
-                if isinstance(val, claripy.Bits):
+                if isinstance(val, claripy.ast.Bits):
                     self.state.vvar_store(stmt.dst, val)
             elif stmt.dst.was_stack:
                 addr = (stmt.dst.stack_offset + self.STACK_BASE) & self.MASK
@@ -190,9 +190,9 @@ class InlinedStringTransformationAILEngine(SimEngineLightAILMixin):
         if isinstance(stmt.true_target, Const) and isinstance(stmt.false_target, Const):
             cond = self._expr(stmt.condition)
             if cond is not None:
-                if isinstance(cond, claripy.Bits) and cond.concrete_value == 1:
+                if isinstance(cond, claripy.ast.Bits) and cond.concrete_value == 1:
                     self.pc = stmt.true_target.value
-                elif isinstance(cond, claripy.Bits) and cond.concrete_value == 0:
+                elif isinstance(cond, claripy.ast.Bits) and cond.concrete_value == 0:
                     self.pc = stmt.false_target.value
 
     def _handle_Const(self, expr):
@@ -220,7 +220,7 @@ class InlinedStringTransformationAILEngine(SimEngineLightAILMixin):
         if expr.was_stack:
             addr = (expr.stack_offset + self.STACK_BASE) & self.MASK
             v = self.state.mem_load(addr, expr.size, self.arch.memory_endness)
-            if isinstance(v, claripy.Bits):
+            if isinstance(v, claripy.ast.Bits):
                 # log it
                 for i in range(expr.size):
                     byte_off = i
@@ -240,7 +240,7 @@ class InlinedStringTransformationAILEngine(SimEngineLightAILMixin):
 
     def _handle_Convert(self, expr: Convert):
         v = self._expr(expr.operand)
-        if isinstance(v, claripy.Bits):
+        if isinstance(v, claripy.ast.Bits):
             if expr.to_bits > expr.from_bits:
                 if not expr.is_signed:
                     return claripy.ZeroExt(expr.to_bits - expr.from_bits, v)
@@ -252,37 +252,37 @@ class InlinedStringTransformationAILEngine(SimEngineLightAILMixin):
 
     def _handle_CmpEQ(self, expr):
         op0, op1 = self._expr(expr.operands[0]), self._expr(expr.operands[1])
-        if isinstance(op0, claripy.Bits) and isinstance(op1, claripy.Bits) and op0.concrete and op1.concrete:
+        if isinstance(op0, claripy.ast.Bits) and isinstance(op1, claripy.ast.Bits) and op0.concrete and op1.concrete:
             return claripy.BVV(1, 1) if op0.concrete_value == op1.concrete_value else claripy.BVV(0, 1)
         return None
 
     def _handle_CmpNE(self, expr):
         op0, op1 = self._expr(expr.operands[0]), self._expr(expr.operands[1])
-        if isinstance(op0, claripy.Bits) and isinstance(op1, claripy.Bits) and op0.concrete and op1.concrete:
+        if isinstance(op0, claripy.ast.Bits) and isinstance(op1, claripy.ast.Bits) and op0.concrete and op1.concrete:
             return claripy.BVV(1, 1) if op0.concrete_value != op1.concrete_value else claripy.BVV(0, 1)
         return None
 
     def _handle_CmpLT(self, expr):
         op0, op1 = self._expr(expr.operands[0]), self._expr(expr.operands[1])
-        if isinstance(op0, claripy.Bits) and isinstance(op1, claripy.Bits) and op0.concrete and op1.concrete:
+        if isinstance(op0, claripy.ast.Bits) and isinstance(op1, claripy.ast.Bits) and op0.concrete and op1.concrete:
             return claripy.BVV(1, 1) if op0.concrete_value < op1.concrete_value else claripy.BVV(0, 1)
         return None
 
     def _handle_CmpLE(self, expr):
         op0, op1 = self._expr(expr.operands[0]), self._expr(expr.operands[1])
-        if isinstance(op0, claripy.Bits) and isinstance(op1, claripy.Bits) and op0.concrete and op1.concrete:
+        if isinstance(op0, claripy.ast.Bits) and isinstance(op1, claripy.ast.Bits) and op0.concrete and op1.concrete:
             return claripy.BVV(1, 1) if op0.concrete_value <= op1.concrete_value else claripy.BVV(0, 1)
         return None
 
     def _handle_CmpGT(self, expr):
         op0, op1 = self._expr(expr.operands[0]), self._expr(expr.operands[1])
-        if isinstance(op0, claripy.Bits) and isinstance(op1, claripy.Bits) and op0.concrete and op1.concrete:
+        if isinstance(op0, claripy.ast.Bits) and isinstance(op1, claripy.ast.Bits) and op0.concrete and op1.concrete:
             return claripy.BVV(1, 1) if op0.concrete_value > op1.concrete_value else claripy.BVV(0, 1)
         return None
 
     def _handle_CmpGE(self, expr):
         op0, op1 = self._expr(expr.operands[0]), self._expr(expr.operands[1])
-        if isinstance(op0, claripy.Bits) and isinstance(op1, claripy.Bits) and op0.concrete and op1.concrete:
+        if isinstance(op0, claripy.ast.Bits) and isinstance(op1, claripy.ast.Bits) and op0.concrete and op1.concrete:
             return claripy.BVV(1, 1) if op0.concrete_value >= op1.concrete_value else claripy.BVV(0, 1)
         return None
 

angr/analyses/decompiler/optimization_passes/ite_expr_converter.py

@@ -6,12 +6,12 @@ from typing import Any, TYPE_CHECKING
 from ailment.statement import ConditionalJump, Assignment, Statement
 from ailment.expression import Const, ITE, Expression
 
-from ....analyses import ReachingDefinitionsAnalysis
-from ....code_location import CodeLocation
-from ..region_walker import RegionWalker
-from ..ail_simplifier import AILBlockWalker
-from ..condition_processor import ConditionProcessor
-from ..structuring.structurer_nodes import EmptyBlockNotice
+from angr.analyses import ReachingDefinitionsAnalysis
+from angr.code_location import CodeLocation
+from angr.analyses.decompiler.region_walker import RegionWalker
+from angr.analyses.decompiler.ail_simplifier import AILBlockWalker
+from angr.analyses.decompiler.condition_processor import ConditionProcessor
+from angr.analyses.decompiler.structuring.structurer_nodes import EmptyBlockNotice
 from .optimization_pass import OptimizationPass, OptimizationPassStage
 
 if TYPE_CHECKING:

angr/analyses/decompiler/optimization_passes/ite_region_converter.py

@@ -7,8 +7,8 @@ from ailment.statement import Statement, Call, ConditionalJump, Assignment, Jump
 from ailment.expression import ITE, Const, VirtualVariable, Phi
 
 from angr.utils.ail import is_phi_assignment
-from ....utils.graph import subgraph_between_nodes
-from ..utils import remove_labels, to_ail_supergraph
+from angr.utils.graph import subgraph_between_nodes
+from angr.analyses.decompiler.utils import remove_labels, to_ail_supergraph
 from .optimization_pass import OptimizationPass, OptimizationPassStage
 
 

angr/analyses/decompiler/optimization_passes/lowered_switch_simplifier.py

@@ -10,10 +10,14 @@ from ailment.statement import ConditionalJump, Label, Assignment, Jump
 from ailment.expression import Expression, BinaryOp, Const, Load
 
 from angr.utils.graph import GraphUtils
-from ..utils import first_nonlabel_nonphi_statement, remove_last_statement
-from ..structuring.structurer_nodes import IncompleteSwitchCaseHeadStatement, SequenceNode, MultiNode
+from angr.analyses.decompiler.utils import first_nonlabel_nonphi_statement, remove_last_statement
+from angr.analyses.decompiler.structuring.structurer_nodes import (
+    IncompleteSwitchCaseHeadStatement,
+    SequenceNode,
+    MultiNode,
+)
 from .optimization_pass import MultipleBlocksException, StructuringOptimizationPass
-from ..region_simplifiers.switch_cluster_simplifier import SwitchClusterFinder
+from angr.analyses.decompiler.region_simplifiers.switch_cluster_simplifier import SwitchClusterFinder
 
 if TYPE_CHECKING:
     from ailment.expression import UnaryOp, Convert