angr 9.2.118__py3-none-manylinux2014_x86_64.whl → 9.2.120__py3-none-manylinux2014_x86_64.whl

angr/state_plugins/heap/heap_ptmalloc.py

@@ -3,30 +3,18 @@ import logging
 
 import claripy
 
-from ..plugin import SimStatePlugin
+from angr.state_plugins.plugin import SimStatePlugin
 from .heap_freelist import SimHeapFreelist, Chunk
 from .utils import concretize
-from ...errors import SimHeapError, SimMergeError, SimSolverError
+from angr.errors import SimHeapError, SimMergeError, SimSolverError
 
 
 l = logging.getLogger("angr.state_plugins.heap.heap_ptmalloc")
-sml = logging.getLogger("angr.state_plugins.symbolic_memory")
 
 CHUNK_FLAGS_MASK = 0x07
 CHUNK_P_MASK = 0x01
 
 
-# These are included as sometimes the heap will touch uninitialized locations, which normally causes a warning
-def silence_logger():
-    level = sml.getEffectiveLevel()
-    sml.setLevel("ERROR")
-    return level
-
-
-def unsilence_logger(level):
-    sml.setLevel(level)
-
-
 class PTChunk(Chunk):
     """
     A chunk, inspired by the implementation of chunks in ptmalloc. Provides a representation of a chunk via a view into
@@ -60,11 +48,9 @@ class PTChunk(Chunk):
         return chunk_size - 2 * self._chunk_size_t_size
 
     def _set_leading_size(self, size):
-        level = silence_logger()
         chunk_flags = (
             self.state.memory.load(self.base + self._chunk_size_t_size, self._chunk_size_t_size) & CHUNK_FLAGS_MASK
         )
-        unsilence_logger(level)
         self.state.memory.store(self.base + self._chunk_size_t_size, size | chunk_flags, size=self.state.arch.bytes)
 
     def _set_trailing_size(self, size):
@@ -98,9 +84,7 @@ class PTChunk(Chunk):
 
         :param is_free: if True, sets the previous chunk to be free; if False, sets it to be allocated
         """
-        level = silence_logger()
         size_field = self.state.memory.load(self.base + self._chunk_size_t_size, self._chunk_size_t_size)
-        unsilence_logger(level)
         if is_free:
             self.state.memory.store(
                 self.base + self._chunk_size_t_size, size_field & ~CHUNK_P_MASK, size=self.state.arch.bytes
@@ -550,9 +534,7 @@ class SimHeapPTMalloc(SimHeapFreelist):
                 return 0
             # Copy the old data over
             old_data_ptr = chunk.data_ptr()
-            level = silence_logger()
             old_data = self.state.memory.load(old_data_ptr, size=old_size - 2 * self._chunk_size_t_size)
-            unsilence_logger(level)
             self.state.memory.store(new_data_ptr, old_data)
             self.free(old_data_ptr)  # Free the old chunk
             return new_data_ptr

angr/state_plugins/heap/utils.py

@@ -1,5 +1,5 @@
 from __future__ import annotations
-from ...errors import SimSolverError
+from angr.errors import SimSolverError
 
 
 def concretize(x, solver, sym_handler):

angr/state_plugins/history.py

@@ -9,8 +9,8 @@ import claripy
 from claripy.ast.bv import BV
 
 from .plugin import SimStatePlugin
-from .. import sim_options
-from ..state_plugins.sim_action import SimActionObject
+from angr import sim_options
+from angr.state_plugins.sim_action import SimActionObject
 
 l = logging.getLogger(name=__name__)
 

angr/state_plugins/javavm_classloader.py

@@ -3,9 +3,9 @@ import logging
 
 from archinfo.arch_soot import SootAddressDescriptor, SootAddressTerminator, SootClassDescriptor
 
-from ..engines.soot.method_dispatcher import resolve_method
-from ..engines import UberEngine
-from ..sim_state import SimState
+from angr.engines.soot.method_dispatcher import resolve_method
+from angr.engines import UberEngine
+from angr.sim_state import SimState
 from .plugin import SimStatePlugin
 
 l = logging.getLogger("angr.state_plugins.javavm_classloader")

angr/state_plugins/jni_references.py

@@ -1,7 +1,7 @@
 from __future__ import annotations
 import logging
 
-from ..sim_state import SimState
+from angr.sim_state import SimState
 from .plugin import SimStatePlugin
 
 l = logging.getLogger("angr.state_plugins.jni_references")

angr/state_plugins/light_registers.py

@@ -3,9 +3,9 @@ import claripy
 import logging
 
 from .plugin import SimStatePlugin
-from ..errors import SimFastMemoryError
-from ..misc.ux import once
-from .. import sim_options as options
+from angr.errors import SimFastMemoryError
+from angr.misc.ux import once
+from angr import sim_options as options
 
 l = logging.getLogger(__name__)
 

angr/state_plugins/log.py

@@ -76,7 +76,7 @@ class SimStateLog(SimStatePlugin):
         # self.input_variables.clear()
 
 
-from ..errors import SimEventError
+from angr.errors import SimEventError
 from .sim_event import SimEvent
 from .sim_action import SimAction, SimActionConstraint
 

angr/state_plugins/plugin.py

@@ -1,10 +1,11 @@
 from __future__ import annotations
+
 from typing import cast
 
-import angr  # For type annotations; pylint: disable=unused-import
 import logging
 
-from ..misc.ux import once
+import angr
+from angr.misc.ux import once
 
 l = logging.getLogger(name=__name__)
 

angr/state_plugins/posix.py

@@ -5,8 +5,8 @@ import claripy
 
 from .plugin import SimStatePlugin
 from .filesystem import SimMount, Stat
-from ..storage.file import SimFile, SimPacketsStream, Flags, SimFileDescriptor, SimFileDescriptorDuplex
-from .. import sim_options as options
+from angr.storage.file import SimFile, SimPacketsStream, Flags, SimFileDescriptor, SimFileDescriptorDuplex
+from angr import sim_options as options
 
 l = logging.getLogger(name=__name__)
 
@@ -700,4 +700,4 @@ from angr.sim_state import SimState
 
 SimState.register_default("posix", SimSystemPosix)
 
-from ..errors import SimPosixError, SimSolverError, SimMergeError, SimMemoryError
+from angr.errors import SimPosixError, SimSolverError, SimMergeError, SimMemoryError

angr/state_plugins/preconstrainer.py

@@ -4,8 +4,8 @@ import logging
 import claripy
 
 from .plugin import SimStatePlugin
-from .. import sim_options as o
-from ..errors import AngrError
+from angr import sim_options as o
+from angr.errors import AngrError
 
 
 l = logging.getLogger(name=__name__)
@@ -55,8 +55,8 @@ class SimStatePreconstrainer(SimStatePlugin):
         """
         if not isinstance(value, claripy.ast.Base):
             value = claripy.BVV(value, len(variable))
-        elif value.op != "BVV":
-            raise ValueError("Passed a value to preconstrain that was not a BVV or a string")
+        elif value.op not in ["BVV", "FPV"]:
+            raise ValueError("Passed a value to preconstrain that was not a BVV or FPV or a string")
 
         if not variable.is_leaf():
             l.warning(
@@ -147,13 +147,13 @@ class SimStatePreconstrainer(SimStatePlugin):
         precon_cache_keys = set()
 
         for con in self.preconstraints:
-            precon_cache_keys.add(con.cache_key)
+            precon_cache_keys.add(con.hash())
 
         # if we used the replacement solver we didn't add constraints we need to remove so keep all constraints
         if o.REPLACEMENT_SOLVER in self.state.options:
             new_constraints = self.state.solver.constraints
         else:
-            new_constraints = [x for x in self.state.solver.constraints if x.cache_key not in precon_cache_keys]
+            new_constraints = [x for x in self.state.solver.constraints if x.hash() not in precon_cache_keys]
 
         if self.state.has_plugin("zen_plugin"):
             new_constraints = self.state.get_plugin("zen_plugin").filter_constraints(new_constraints)

angr/state_plugins/scratch.py

@@ -30,7 +30,7 @@ class SimStateScratch(SimStatePlugin):
 
         # information on exits *from* this state
         self.jumpkind = None
-        self.guard = claripy.true
+        self.guard = claripy.true()
         self.target = None
         self.source = None
         self.exit_stmt_idx = None
@@ -167,10 +167,10 @@ class SimStateScratch(SimStatePlugin):
 
 # pylint:disable=wrong-import-position
 from .sim_action import SimActionObject, SimActionData
-from ..errors import SimValueError, SimMissingTempError
-from .. import sim_options as o
+from angr.errors import SimValueError, SimMissingTempError
+from angr import sim_options as o
 from .inspect import BP_AFTER, BP_BEFORE
 
-from ..sim_state import SimState
+from angr.sim_state import SimState
 
 SimState.register_default("scratch", SimStateScratch)

angr/state_plugins/sim_action_object.py

@@ -9,7 +9,7 @@ import claripy
 from angr import sim_options as o
 from angr.errors import SimActionError
 from .sim_action import SimActionData, SimActionOperation
-from ..sim_state import SimState
+from angr.sim_state import SimState
 
 if typing.TYPE_CHECKING:
     from claripy.annotation import Annotation

angr/state_plugins/solver.py

@@ -95,7 +95,7 @@ def error_converter(f):
             return f(*args, **kwargs)
         except claripy.UnsatError as e:
             raise SimUnsatError("Got an unsat result") from e
-        except claripy.ClaripyFrontendError as e:
+        except claripy.ClaripyError as e:
             raise SimSolverModeError("Claripy threw an error") from e
 
     return wrapped_f
@@ -346,23 +346,19 @@ class SimSolver(SimStatePlugin):
         """
         if o.SYMBOLIC_INITIAL_VALUES in self.state.options:
             # Return a symbolic value
-            if o.ABSTRACT_MEMORY in self.state.options:
-                l.debug("Creating new top StridedInterval")
-                r = claripy.TSI(bits=bits, name=name, uninitialized=uninitialized, **kwargs)
-            else:
-                l.debug("Creating new unconstrained BV named %s", name)
-                r = self.BVS(
-                    name,
-                    bits,
-                    uninitialized=uninitialized,
-                    key=key,
-                    eternal=eternal,
-                    inspect=inspect,
-                    events=events,
-                    **kwargs,
-                )
-                if uc_alloc_depth is not None:
-                    self.state.uc_manager.set_alloc_depth(r, uc_alloc_depth)
+            l.debug("Creating new unconstrained BV named %s", name)
+            r = self.BVS(
+                name,
+                bits,
+                uninitialized=uninitialized,
+                key=key,
+                eternal=eternal,
+                inspect=inspect,
+                events=events,
+                **kwargs,
+            )
+            if uc_alloc_depth is not None:
+                self.state.uc_manager.set_alloc_depth(r, uc_alloc_depth)
 
             return r
         # Return a default value, aka. 0
@@ -416,7 +412,7 @@ class SimSolver(SimStatePlugin):
                 or min != r.args[1]
                 or max != r.args[2]
                 or stride != r.args[3]
-                or uninitialized != r.args[4]
+                or uninitialized != r.uninitialized
                 or bool(explicit_name) ^ (r.args[0] == name)
             ):
                 l.warning("Variable %s being retrieved with different settings than it was tracked with", name)

angr/state_plugins/symbolizer.py

@@ -4,11 +4,10 @@ import claripy
 import struct
 
 from .plugin import SimStatePlugin
-from ..storage.memory_mixins import PagedMemoryMixin
+from angr.storage.memory_mixins import PagedMemoryMixin
 
 
 l = logging.getLogger(name=__name__)
-l.setLevel("DEBUG")
 
 
 def _mem_write_cb(s):
@@ -286,6 +285,6 @@ class SimSymbolizer(SimStatePlugin):  # pylint:disable=abstract-method
         return sc
 
 
-from ..sim_state import SimState
+from angr.sim_state import SimState
 
 SimState.register_default("symbolizer", SimSymbolizer)

angr/state_plugins/trace_additions.py

@@ -219,7 +219,7 @@ def end_info_hook(state):
         )
         chall_resp_plugin.str_to_int_pairs.append((input_bvs, new_var))
         if pending_info.allows_negative:
-            chall_resp_plugin.allows_negative_bvs.add(input_bvs.cache_key)
+            chall_resp_plugin.allows_negative_bvs.add(input_bvs.hash())
         chall_resp_plugin.replacement_pairs.append((input_bvs, input_val))
     elif pending_info.get_type() == "IntToStr":
         # result constraint
@@ -459,11 +459,11 @@ class ChallRespInfo(angr.state_plugins.SimStatePlugin):
             base = int(int_var_name.split("_")[1], 10)
             original_len = str_var.size() // 8
             abs_max = (1 << int_var.size()) - 1
-            if str_var.cache_key in self.allows_negative_bvs:
+            if str_var.hash() in self.allows_negative_bvs:
                 abs_max = (1 << (int_var.size() - 1)) - 1
             max_val = base ** (original_len) - 1
             min_val = 0
-            if str_var.cache_key in self.allows_negative_bvs and original_len > 1:
+            if str_var.hash() in self.allows_negative_bvs and original_len > 1:
                 min_val = -(base ** (original_len - 1) - 1)
 
             max_val = min(max_val, abs_max)
@@ -569,10 +569,10 @@ def zen_hook(state, expr):
         if len(flag_args) > 1:
             zen_plugin = state.get_plugin("zen_plugin")
 
-            if expr.cache_key in zen_plugin.replacements:
+            if expr.hash() in zen_plugin.replacements:
                 # we already have the replacement
                 concrete_val = state.solver.eval(expr)
-                replacement = zen_plugin.replacements[expr.cache_key]
+                replacement = zen_plugin.replacements[expr.hash()]
                 state.preconstrainer.preconstrain(concrete_val, replacement)
                 zen_plugin.preconstraints.append(replacement == concrete_val)
             else:
@@ -603,7 +603,7 @@ def zen_hook(state, expr):
                 zen_plugin.state.preconstrainer.preconstraints.append(constraint)
                 zen_plugin.preconstraints.append(replacement == concrete_val)
 
-                zen_plugin.replacements[expr.cache_key] = replacement
+                zen_plugin.replacements[expr.hash()] = replacement
 
             return replacement
     return None
@@ -701,11 +701,11 @@ class ZenPlugin(angr.state_plugins.SimStatePlugin):
         return contained_bytes
 
     def filter_constraints(self, constraints):
-        zen_cache_keys = {x.cache_key for x in self.zen_constraints}
+        zen_cache_keys = {x.hash() for x in self.zen_constraints}
         new_cons = []
         for con in constraints:
             if (
-                con.cache_key in zen_cache_keys
+                con.hash() in zen_cache_keys
                 or not all(v.startswith(("cgc-flag", "random")) for v in con.variables)
                 or len(con.variables) == 0
             ):

angr/state_plugins/uc_manager.py

@@ -4,7 +4,7 @@ import logging
 import claripy
 
 from .plugin import SimStatePlugin
-from ..errors import SimUCManagerAllocationError
+from angr.errors import SimUCManagerAllocationError
 
 l = logging.getLogger(name=__name__)
 

angr/state_plugins/unicorn_engine.py

@@ -17,10 +17,10 @@ import pyvex
 from angr.engines.vex.claripy import ccall
 from angr.sim_state import SimState
 
-from .. import sim_options as options
-from ..engines.vex.claripy.irop import operations as irop_ops
-from ..errors import SimMemoryError, SimSegfaultError, SimUnicornError, SimUnicornUnsupport, SimValueError
-from ..misc.testing import is_testing
+from angr import sim_options as options
+from angr.engines.vex.claripy.irop import operations as irop_ops
+from angr.errors import SimMemoryError, SimSegfaultError, SimUnicornError, SimUnicornUnsupport, SimValueError
+from angr.misc.testing import is_testing
 from .plugin import SimStatePlugin
 
 l = logging.getLogger(name=__name__)

angr/state_plugins/view.py

@@ -331,7 +331,7 @@ class StructMode:
             self.__getattr__(k).store(v)
 
 
-from ..sim_type import ALL_TYPES, SimTypeFixedSizeArray, SimTypePointer
+from angr.sim_type import ALL_TYPES, SimTypeFixedSizeArray, SimTypePointer
 
 SimMemView.types = ALL_TYPES  # identity purposefully here
 

angr/storage/__init__.py

@@ -1,10 +1,16 @@
-# misc
 from __future__ import annotations
 
 DUMMY_SYMBOLIC_READ_VALUE = 0xC0DEB4BE
 
-# imports
-
 from .file import SimFile
 from .memory_object import SimMemoryObject
 from .memory_mixins import MemoryMixin, DefaultMemory
+
+
+__all__ = (
+    "DUMMY_SYMBOLIC_READ_VALUE",
+    "SimFile",
+    "SimMemoryObject",
+    "MemoryMixin",
+    "DefaultMemory",
+)

angr/storage/file.py

@@ -5,9 +5,9 @@ import itertools
 import claripy
 
 from .memory_mixins import DefaultMemory
-from ..state_plugins.plugin import SimStatePlugin
-from ..state_plugins.sim_action_object import SimActionObject
-from .. import sim_options
+from angr.state_plugins.plugin import SimStatePlugin
+from angr.state_plugins.sim_action_object import SimActionObject
+from angr import sim_options
 
 l = logging.getLogger(name=__name__)
 
@@ -209,7 +209,7 @@ class SimFile(SimFileBase, DefaultMemory):  # TODO: pick a better base class omg
             content = claripy.BVV(content.encode())
         elif content is None:
             pass
-        elif isinstance(content, claripy.Bits):
+        elif isinstance(content, claripy.ast.Bits):
             if concrete is None and not content.symbolic:
                 concrete = True
         else:
@@ -322,7 +322,7 @@ class SimFile(SimFileBase, DefaultMemory):  # TODO: pick a better base class omg
 
         data = _deps_unpack(data)[0]
         if size is None:
-            size = len(data) // self.state.arch.byte_width if isinstance(data, claripy.Bits) else len(data)
+            size = len(data) // self.state.arch.byte_width if isinstance(data, claripy.ast.Bits) else len(data)
         # \(_^^)/
         self.store(pos, data, size=size)
         new_end = _deps_unpack(pos + size)[0]  # decline to store SAO
@@ -442,7 +442,7 @@ class SimPackets(SimFileBase):
                     if type(x) is tuple
                     else (
                         (x, len(x) // 8)
-                        if isinstance(x, claripy.Bits)
+                        if isinstance(x, claripy.ast.Bits)
                         else (
                             (x.ast, len(x) // 8)
                             if isinstance(x, SimActionObject)
@@ -593,7 +593,7 @@ class SimPackets(SimFileBase):
         if type(data) is bytes:
             data = claripy.BVV(data)
         if size is None:
-            size = len(data) // self.state.arch.byte_width if isinstance(data, claripy.Bits) else len(data)
+            size = len(data) // self.state.arch.byte_width if isinstance(data, claripy.ast.Bits) else len(data)
         if type(size) is int:
             size = claripy.BVV(size, self.state.arch.bits)
 
@@ -903,7 +903,7 @@ class SimFileDescriptor(SimFileDescriptorBase):
 
         data = _deps_unpack(data)[0]
         if size is None:
-            size = len(data) // self.state.arch.byte_width if isinstance(data, claripy.Bits) else len(data)
+            size = len(data) // self.state.arch.byte_width if isinstance(data, claripy.ast.Bits) else len(data)
 
         size = self._prep_write(size)
         self._pos = self.file.write(self._pos, data, size)
@@ -911,7 +911,7 @@ class SimFileDescriptor(SimFileDescriptorBase):
 
     def seek(self, offset, whence="start"):
         if not self.file.seekable:
-            return claripy.false
+            return claripy.false()
 
         if type(offset) is int:
             offset = claripy.BVV(offset, self.state.arch.bits)
@@ -929,9 +929,9 @@ class SimFileDescriptor(SimFileDescriptorBase):
 
     def eof(self):
         if not self.file.seekable:
-            return claripy.false
+            return claripy.false()
         if not getattr(self.file, "has_end", True):
-            return claripy.false
+            return claripy.false()
         return self._pos == self.file.size
 
     def tell(self):
@@ -1034,7 +1034,7 @@ class SimFileDescriptorDuplex(SimFileDescriptorBase):
     def write_data(self, data, size=None, **kwargs):
         data = _deps_unpack(data)[0]
         if size is None:
-            size = len(data) // self.state.arch.byte_width if isinstance(data, claripy.Bits) else len(data)
+            size = len(data) // self.state.arch.byte_width if isinstance(data, claripy.ast.Bits) else len(data)
 
         size = self._prep_write(size)
         self._write_pos = self._write_file.write(self._write_pos, data, size)
@@ -1048,16 +1048,16 @@ class SimFileDescriptorDuplex(SimFileDescriptorBase):
     def eof(self):
         # the thing that makes the most sense is for this to refer to the read eof status...
         if not self._read_file.seekable:
-            return claripy.false
+            return claripy.false()
         if not getattr(self._read_file, "has_end", True):
-            return claripy.false
+            return claripy.false()
         return self._read_pos == self._read_file.size
 
     def tell(self):
         return None
 
     def seek(self, offset, whence="start"):
-        return claripy.false
+        return claripy.false()
 
     def size(self):
         return None
@@ -1209,4 +1209,4 @@ class SimPacketsSlots(SimFileBase):
         raise SimMergeError("Widening the filesystem is unsupported")
 
 
-from ..errors import SimMergeError, SimFileError, SimSolverError
+from angr.errors import SimMergeError, SimFileError, SimSolverError

angr/storage/memory_mixins/__init__.py

@@ -1,12 +1,12 @@
 # pylint:disable=abstract-method,wrong-import-position,unused-argument,missing-class-docstring,arguments-differ
 from __future__ import annotations
-from typing import Tuple, Dict, Any, Optional
+from typing import Any
 from collections.abc import Iterable
 
 import claripy
 
-from ...state_plugins.plugin import SimStatePlugin
-from ...errors import SimMemoryError
+from angr.state_plugins.plugin import SimStatePlugin
+from angr.errors import SimMemoryError
 
 
 class MemoryMixin(SimStatePlugin):
@@ -188,7 +188,19 @@ from .paged_memory.paged_memory_mixin import (
 from .paged_memory.privileged_mixin import PrivilegedPagingMixin
 from .paged_memory.stack_allocation_mixin import StackAllocationMixin
 from .paged_memory.paged_memory_multivalue_mixin import PagedMemoryMultiValueMixin
-from .paged_memory.pages import *
+from .paged_memory.pages import (
+    CooperationBase,
+    MemoryObjectMixin,
+    ISPOMixin,
+    RefcountMixin,
+    PermissionsMixin,
+    HistoryTrackingMixin,
+    PageBase,
+    PageType,
+    ListPage,
+    MVListPage,
+    UltraPage,
+)
 
 from .slotted_memory import SlottedMemoryMixin
 from .regioned_memory import (
@@ -199,8 +211,8 @@ from .regioned_memory import (
     MemoryRegionMetaMixin,
     RegionedAddressConcretizationMixin,
 )
-from .keyvalue_memory import KeyValueMemoryMixin
-from .javavm_memory import JavaVmMemoryMixin
+from .keyvalue_memory_mixin import KeyValueMemoryMixin
+from .javavm_memory_mixin import JavaVmMemoryMixin
 
 
 class DefaultMemory(
@@ -388,3 +400,73 @@ SimState.register_default("fast_memory", FastMemory)
 SimState.register_default("abs_memory", AbstractMemory)
 SimState.register_default("keyvalue_memory", KeyValueMemory)
 SimState.register_default("javavm_memory", JavaVmMemory)
+
+
+__all__ = (
+    "MemoryMixin",
+    "ActionsMixinHigh",
+    "ActionsMixinLow",
+    "AddressConcretizationMixin",
+    "DataNormalizationMixin",
+    "InspectMixinHigh",
+    "ConditionalMixin",
+    "ConvenientMappingsMixin",
+    "DefaultFillerMixin",
+    "SpecialFillerMixin",
+    "ExplicitFillerMixin",
+    "DirtyAddrsMixin",
+    "HexDumperMixin",
+    "LabelMergerMixin",
+    "MultiValueMergerMixin",
+    "NameResolutionMixin",
+    "SimplificationMixin",
+    "SimpleInterfaceMixin",
+    "SizeNormalizationMixin",
+    "SizeConcretizationMixin",
+    "SmartFindMixin",
+    "SymbolicMergerMixin",
+    "TopMergerMixin",
+    "UnderconstrainedMixin",
+    "UnwrapperMixin",
+    "ClemoryBackerMixin",
+    "ConcreteBackerMixin",
+    "DictBackerMixin",
+    "PagedMemoryMixin",
+    "ListPagesMixin",
+    "UltraPagesMixin",
+    "ListPagesWithLabelsMixin",
+    "MVListPagesMixin",
+    "MVListPagesWithLabelsMixin",
+    "PrivilegedPagingMixin",
+    "StackAllocationMixin",
+    "PagedMemoryMultiValueMixin",
+    "CooperationBase",
+    "MemoryObjectMixin",
+    "ISPOMixin",
+    "RefcountMixin",
+    "PermissionsMixin",
+    "HistoryTrackingMixin",
+    "PageBase",
+    "PageType",
+    "ListPage",
+    "MVListPage",
+    "UltraPage",
+    "SlottedMemoryMixin",
+    "RegionedMemoryMixin",
+    "RegionCategoryMixin",
+    "StaticFindMixin",
+    "AbstractMergerMixin",
+    "MemoryRegionMetaMixin",
+    "RegionedAddressConcretizationMixin",
+    "KeyValueMemoryMixin",
+    "JavaVmMemoryMixin",
+    "DefaultMemory",
+    "DefaultListPagesMemory",
+    "FastMemory",
+    "AbstractMemory",
+    "RegionedMemory",
+    "LabeledMemory",
+    "MultiValuedMemory",
+    "KeyValueMemory",
+    "JavaVmMemory",
+)