angr 9.2.117__py3-none-manylinux2014_aarch64.whl → 9.2.119__py3-none-manylinux2014_aarch64.whl

angr/calling_conventions.py

@@ -1,6 +1,8 @@
 # pylint:disable=line-too-long,missing-class-docstring,no-self-use
+from __future__ import annotations
 import logging
-from typing import Optional, Union, cast
+from typing import cast
+from collections.abc import Iterable
 from collections import defaultdict
 
 import claripy
@@ -31,6 +33,7 @@ from .sim_type import (
 )
 from .state_plugins.sim_action_object import SimActionObject
 from .engines.soot.engine import SootMixin
+import contextlib
 
 l = logging.getLogger(name=__name__)
 l.addFilter(UniqueLogFilter())
@@ -47,6 +50,7 @@ class AllocHelper:
         self.base = claripy.BVS("alloc_base", ptrsize)
         self.ptr = self.base
         self.stores = {}
+        self.store_asts = {}
 
     def alloc(self, size):
         out = self.ptr
@@ -56,7 +60,7 @@ class AllocHelper:
     def dump(self, val, state, loc=None):
         if loc is None:
             loc = self.stack_loc(val, state.arch)
-        self.stores[self.ptr.cache_key] = (val, loc)
+        self.stores[self.ptr] = (val, loc)
         return self.alloc(self.calc_size(val, state.arch))
 
     def translate(self, val, base):
@@ -64,7 +68,7 @@ class AllocHelper:
             return SimStructValue(
                 val.struct, {field: self.translate(subval, base) for field, subval in val._values.items()}
             )
-        if isinstance(val, claripy.Bits):
+        if isinstance(val, claripy.ast.Bits):
             return val.replace(self.base, base)
         if type(val) is list:
             return [self.translate(subval, base) for subval in val]
@@ -73,7 +77,7 @@ class AllocHelper:
     def apply(self, state, base):
         for ptr, (val, loc) in self.stores.items():
             translated_val = self.translate(val, base)
-            translated_ptr = self.translate(ptr.ast, base)
+            translated_ptr = self.translate(ptr, base)
             loc.set_value(state, translated_val, stack_base=translated_ptr)
 
     def size(self):
@@ -85,7 +89,7 @@ class AllocHelper:
     def calc_size(cls, val, arch):
         if type(val) is SimStructValue:
             return val.struct.size // arch.byte_width
-        if isinstance(val, claripy.Bits):
+        if isinstance(val, claripy.ast.Bits):
             return len(val) // arch.byte_width
         if type(val) is list:
             # TODO real strides
@@ -96,7 +100,7 @@ class AllocHelper:
 
     @classmethod
     def stack_loc(cls, val, arch, offset=0):
-        if isinstance(val, claripy.Bits):
+        if isinstance(val, claripy.ast.Bits):
             return SimStackArg(offset, len(val) // arch.byte_width)
         if type(val) is list:
             # TODO real strides
@@ -138,10 +142,7 @@ def refine_locs_with_struct_type(
             pieces.append(locs[chunk].refine(size=use_bytes, offset=chunk_offset))
             seen_bytes += use_bytes
 
-        if len(pieces) == 1:
-            piece = pieces[0]
-        else:
-            piece = SimComboArg(pieces)
+        piece = pieces[0] if len(pieces) == 1 else SimComboArg(pieces)
         if isinstance(arg_type, SimTypeFloat):
             piece.is_fp = True
         return piece
@@ -166,7 +167,7 @@ def refine_locs_with_struct_type(
             if member.size == arg_type.size:
                 return refine_locs_with_struct_type(arch, locs, member, offset)
 
-    raise TypeError("I don't know how to lay out a %s" % arg_type)
+    raise TypeError(f"I don't know how to lay out a {arg_type}")
 
 
 class SerializableIterator:
@@ -265,7 +266,7 @@ class SimFunctionArgument:
     def refine(self, size, arch=None, offset=None, is_fp=None):
         raise NotImplementedError
 
-    def get_footprint(self) -> list[Union["SimRegArg", "SimStackArg"]]:
+    def get_footprint(self) -> Iterable[SimRegArg | SimStackArg]:
         """
         Return a list of SimRegArg and SimStackArgs that are the base components used for this location
         """
@@ -290,13 +291,18 @@ class SimRegArg(SimFunctionArgument):
         self.clear_entire_reg = clear_entire_reg
 
     def get_footprint(self):
-        yield self
+        return {self}
 
     def __repr__(self):
-        return "<%s>" % self.reg_name
+        return f"<{self.reg_name}>"
 
     def __eq__(self, other):
-        return type(other) is SimRegArg and self.reg_name == other.reg_name and self.reg_offset == other.reg_offset
+        return (
+            type(other) is SimRegArg
+            and self.reg_name == other.reg_name
+            and self.reg_offset == other.reg_offset
+            and self.size == other.size
+        )
 
     def __hash__(self):
         return hash((self.size, self.reg_name, self.reg_offset))
@@ -320,10 +326,7 @@ class SimRegArg(SimFunctionArgument):
         if offset is None:
             if arch is None:
                 raise ValueError("Need to specify either offset or arch in order to refine a register argument")
-            if arch.register_endness == "Iend_LE":
-                offset = 0
-            else:
-                offset = self.size - size
+            offset = 0 if arch.register_endness == "Iend_LE" else self.size - size
         if is_fp is None:
             is_fp = self.is_fp
         return SimRegArg(self.reg_name, size, self.reg_offset + offset, is_fp, clear_entire_reg=passed_offset_none)
@@ -341,15 +344,15 @@ class SimStackArg(SimFunctionArgument):
     :ivar bool is_fp:  Whether loads from this location should return a floating point bitvector
     """
 
-    def __init__(self, stack_offset, size, is_fp=False):
+    def __init__(self, stack_offset: int, size: int, is_fp: bool = False):
         SimFunctionArgument.__init__(self, size, is_fp)
-        self.stack_offset = stack_offset
+        self.stack_offset: int = stack_offset
 
     def get_footprint(self):
-        yield self
+        return {self}
 
     def __repr__(self):
-        return "[%#x]" % self.stack_offset
+        return f"[{self.stack_offset:#x}]"
 
     def __eq__(self, other):
         return type(other) is SimStackArg and self.stack_offset == other.stack_offset
@@ -373,10 +376,7 @@ class SimStackArg(SimFunctionArgument):
         if offset is None:
             if arch is None:
                 raise ValueError("Need to specify either offset or arch in order to refine a stack argument")
-            if arch.register_endness == "Iend_LE":
-                offset = 0
-            else:
-                offset = self.size - size
+            offset = 0 if arch.register_endness == "Iend_LE" else self.size - size
         if is_fp is None:
             is_fp = self.is_fp
         return SimStackArg(self.stack_offset + offset, size, is_fp)
@@ -392,11 +392,10 @@ class SimComboArg(SimFunctionArgument):
         self.locations = locations
 
     def get_footprint(self):
-        for x in self.locations:
-            yield from x.get_footprint()
+        return {y for x in self.locations for y in x.get_footprint()}
 
     def __repr__(self):
-        return "SimComboArg(%s)" % repr(self.locations)
+        return f"SimComboArg({self.locations!r})"
 
     def __eq__(self, other):
         return type(other) is SimComboArg and all(a == b for a, b in zip(self.locations, other.locations))
@@ -430,8 +429,21 @@ class SimStructArg(SimFunctionArgument):
         self.locs = locs
 
     def get_footprint(self):
-        for x in self.locs.values():
-            yield from x.get_footprint()
+        regs: defaultdict[str, set[SimRegArg]] = defaultdict(set)
+        others: set[SimRegArg | SimStackArg] = set()
+        for loc in self.locs.values():
+            for footloc in loc.get_footprint():
+                if isinstance(footloc, SimRegArg):
+                    regs[footloc.reg_name].add(footloc)
+                else:
+                    others.add(footloc)
+
+        for reg, locset in regs.items():
+            min_offset = min(loc.reg_offset for loc in locset)
+            max_offset = max(loc.reg_offset + loc.size for loc in locset)
+            others.add(SimRegArg(reg, max_offset - min_offset, min_offset))
+
+        return others
 
     def get_value(self, state, **kwargs):
         return SimStructValue(
@@ -449,8 +461,7 @@ class SimArrayArg(SimFunctionArgument):
         self.locs = locs
 
     def get_footprint(self):
-        for x in self.locs:
-            yield from x.get_footprint()
+        return {y for x in self.locs for y in x.get_footprint()}
 
     def get_value(self, state, **kwargs):
         return [getter.get_value(state, **kwargs) for getter in self.locs]
@@ -477,7 +488,7 @@ class SimReferenceArgument(SimFunctionArgument):
         self.main_loc = main_loc
 
     def get_footprint(self):
-        yield from self.ptr_loc.get_footprint()
+        return self.main_loc.get_footprint()
 
     def get_value(self, state, **kwargs):
         ptr_val = self.ptr_loc.get_value(state, **kwargs)
@@ -588,7 +599,7 @@ class SimCC:
         Returns an iterator of SimFunctionArguments
         """
         if self.ARG_REGS is None:
-            raise NotImplementedError()
+            raise NotImplementedError
         return SerializableListIterator([SimRegArg(reg, self.arch.bytes) for reg in self.ARG_REGS])
 
     @property
@@ -609,7 +620,7 @@ class SimCC:
         Returns an iterator of SimFunctionArguments
         """
         if self.FP_ARG_REGS is None:
-            raise NotImplementedError()
+            raise NotImplementedError
         return SerializableListIterator([SimRegArg(reg, self.arch.bytes) for reg in self.FP_ARG_REGS])
 
     def is_fp_arg(self, arg):
@@ -714,15 +725,12 @@ class SimCC:
         is_fp = isinstance(arg_type, SimTypeFloat)
         size = arg_type.size // self.arch.byte_width
         try:
-            if is_fp:
-                arg = next(session.fp_iter)
-            else:
-                arg = next(session.int_iter)
+            arg = next(session.fp_iter) if is_fp else next(session.int_iter)
         except StopIteration:
             try:
                 arg = next(session.both_iter)
-            except StopIteration:
-                raise TypeError("Accessed too many arguments - exhausted all positions?")
+            except StopIteration as err:
+                raise TypeError("Accessed too many arguments - exhausted all positions?") from err
 
         if size > arg.size:
             if isinstance(arg, SimStackArg):
@@ -781,7 +789,7 @@ class SimCC:
                 else:
                     raise TypeError("WHAT kind of floating point is this")
             else:
-                raise TypeError("Cannot guess FFI type for %s" % type(arg))
+                raise TypeError(f"Cannot guess FFI type for {type(arg)}")
 
         return result
 
@@ -951,12 +959,12 @@ class SimCC:
     def _standardize_value(arg, ty, state, alloc):
         if isinstance(arg, SimActionObject):
             return SimCC._standardize_value(arg.ast, ty, state, alloc)
-        elif isinstance(arg, PointerWrapper):
+        if isinstance(arg, PointerWrapper):
             if not isinstance(ty, (SimTypePointer, SimTypeReference)):
-                raise TypeError("Type mismatch: expected %s, got pointer-wrapper" % ty)
+                raise TypeError(f"Type mismatch: expected {ty}, got pointer-wrapper")
 
             if arg.buffer:
-                if isinstance(arg.value, claripy.Bits):
+                if isinstance(arg.value, claripy.ast.Bits):
                     real_value = arg.value.chop(state.arch.byte_width)
                 elif type(arg.value) in (bytes, str):
                     real_value = claripy.BVV(arg.value).chop(8)
@@ -973,7 +981,7 @@ class SimCC:
                     ) from None
             return alloc(real_value, state)
 
-        elif isinstance(arg, (str, bytes)):
+        if isinstance(arg, (str, bytes)):
             # sanitize the argument and request standardization again with SimTypeArray
             if type(arg) is str:
                 arg = arg.encode()
@@ -982,41 +990,39 @@ class SimCC:
                 pass
             elif isinstance(ty, SimTypeFixedSizeArray) and isinstance(ty.elem_type, SimTypeChar):
                 if len(arg) > ty.length:
-                    raise TypeError(f"String {repr(arg)} is too long for {ty}")
+                    raise TypeError(f"String {arg!r} is too long for {ty}")
                 arg = arg.ljust(ty.length, b"\0")
             elif isinstance(ty, SimTypeArray) and isinstance(ty.elem_type, SimTypeChar):
                 if ty.length is not None:
                     if len(arg) > ty.length:
-                        raise TypeError(f"String {repr(arg)} is too long for {ty}")
+                        raise TypeError(f"String {arg!r} is too long for {ty}")
                     arg = arg.ljust(ty.length, b"\0")
             elif isinstance(ty, SimTypeString):
                 if len(arg) > ty.length + 1:
-                    raise TypeError(f"String {repr(arg)} is too long for {ty}")
+                    raise TypeError(f"String {arg!r} is too long for {ty}")
                 arg = arg.ljust(ty.length + 1, b"\0")
             else:
-                raise TypeError("Type mismatch: Expected %s, got char*" % ty)
-            val = SimCC._standardize_value(list(arg), SimTypeArray(SimTypeChar(), len(arg)), state, alloc)
-            return val
+                raise TypeError(f"Type mismatch: Expected {ty}, got char*")
+            return SimCC._standardize_value(list(arg), SimTypeArray(SimTypeChar(), len(arg)), state, alloc)
 
-        elif isinstance(arg, list):
+        if isinstance(arg, list):
             if isinstance(ty, (SimTypePointer, SimTypeReference)):
                 ref = True
                 subty = ty.pts_to
             elif isinstance(ty, SimTypeArray):
                 ref = True
                 subty = ty.elem_type
-                if ty.length is not None:
-                    if len(arg) != ty.length:
-                        raise TypeError(f"Array {repr(arg)} is the wrong length for {ty}")
+                if ty.length is not None and len(arg) != ty.length:
+                    raise TypeError(f"Array {arg!r} is the wrong length for {ty}")
             else:
-                raise TypeError("Type mismatch: Expected %s, got char*" % ty)
+                raise TypeError(f"Type mismatch: Expected {ty}, got char*")
 
             val = [SimCC._standardize_value(sarg, subty, state, alloc) for sarg in arg]
             if ref:
                 val = alloc(val, state)
             return val
 
-        elif isinstance(arg, (tuple, dict, SimStructValue)):
+        if isinstance(arg, (tuple, dict, SimStructValue)):
             if not isinstance(ty, SimStruct):
                 raise TypeError(f"Type mismatch: Expected {ty}, got {type(arg)} (i.e. struct)")
             if type(arg) is not SimStructValue:
@@ -1027,24 +1033,23 @@ class SimCC:
                 ty, [SimCC._standardize_value(arg[field], ty.fields[field], state, alloc) for field in ty.fields]
             )
 
-        elif isinstance(arg, int):
+        if isinstance(arg, int):
             if isinstance(ty, SimTypeFloat):
                 return SimCC._standardize_value(float(arg), ty, state, alloc)
 
-            val = claripy.BVV(arg, ty.size)
-            return val
+            return claripy.BVV(arg, ty.size)
 
-        elif isinstance(arg, float):
+        if isinstance(arg, float):
             if isinstance(ty, SimTypeDouble):
                 sort = claripy.FSORT_DOUBLE
             elif isinstance(ty, SimTypeFloat):
                 sort = claripy.FSORT_FLOAT
             else:
-                raise TypeError("Type mismatch: expected %s, got float" % ty)
+                raise TypeError(f"Type mismatch: expected {ty}, got float")
 
             return claripy.FPV(arg, sort)
 
-        elif isinstance(arg, claripy.ast.FP):
+        if isinstance(arg, claripy.ast.FP):
             if isinstance(ty, SimTypeFloat):
                 if len(arg) != ty.size:
                     raise TypeError(f"Type mismatch: expected {ty}, got {arg.sort}")
@@ -1053,7 +1058,7 @@ class SimCC:
                 return arg.val_to_bv(ty.size, ty.signed)
             raise TypeError(f"Type mismatch: expected {ty}, got {arg.sort}")
 
-        elif isinstance(arg, claripy.ast.BV):
+        if isinstance(arg, claripy.ast.BV):
             if isinstance(ty, (SimTypeReg, SimTypeNum)):
                 if len(arg) != ty.size:
                     raise TypeError("Type mismatch: expected %s, got %d bits" % (ty, len(arg)))
@@ -1063,10 +1068,9 @@ class SimCC:
                     "It's unclear how to coerce a bitvector to %s. "
                     "Do you want .raw_to_fp or .val_to_fp, and signed or unsigned?"
                 )
-            raise TypeError("Type mismatch: expected %s, got bitvector" % ty)
+            raise TypeError(f"Type mismatch: expected {ty}, got bitvector")
 
-        else:
-            raise TypeError("I don't know how to serialize %s." % repr(arg))
+        raise TypeError(f"I don't know how to serialize {arg!r}.")
 
     def __repr__(self):
         return f"<{self.__class__.__name__}>"
@@ -1083,15 +1087,21 @@ class SimCC:
         if sp_delta != cls.STACKARG_SP_DIFF:
             return False
 
+        def _arg_ident(a: SimRegArg | SimStackArg) -> int | str:
+            if isinstance(a, SimRegArg):
+                return a.reg_name
+            return a.stack_offset
+
         sample_inst = cls(arch)
-        all_fp_args = list(sample_inst.fp_args)
-        all_int_args = list(sample_inst.int_args)
+        all_fp_args: set[int | str] = {_arg_ident(a) for a in sample_inst.fp_args}
+        all_int_args: set[int | str] = {_arg_ident(a) for a in sample_inst.int_args}
         both_iter = sample_inst.memory_args
-        some_both_args = [next(both_iter) for _ in range(len(args))]
+        some_both_args: set[int | str] = {_arg_ident(next(both_iter)) for _ in range(len(args))}
 
         new_args = []
         for arg in args:
-            if arg not in all_fp_args and arg not in all_int_args and arg not in some_both_args:
+            arg_ident = _arg_ident(arg)
+            if arg_ident not in all_fp_args and arg_ident not in all_int_args and arg_ident not in some_both_args:
                 if isinstance(arg, SimRegArg) and arg.reg_name in sample_inst.CALLER_SAVED_REGS:
                     continue
                 return False
@@ -1105,8 +1115,8 @@ class SimCC:
 
     @staticmethod
     def find_cc(
-        arch: "archinfo.Arch", args: list[SimFunctionArgument], sp_delta: int, platform: str = "Linux"
-    ) -> Optional["SimCC"]:
+        arch: archinfo.Arch, args: list[SimFunctionArgument], sp_delta: int, platform: str = "Linux"
+    ) -> SimCC | None:
         """
         Pinpoint the best-fit calling convention and return the corresponding SimCC instance, or None if no fit is
         found.
@@ -1223,12 +1233,8 @@ class SimCCCdecl(SimCC):
             byte_size = ty.size // self.arch.byte_width
             referenced_locs = [SimStackArg(offset, self.arch.bytes) for offset in range(0, byte_size, self.arch.bytes)]
             referenced_loc = refine_locs_with_struct_type(self.arch, referenced_locs, ty)
-            if perspective_returned:
-                ptr_loc = self.RETURN_VAL
-            else:
-                ptr_loc = SimStackArg(0, 4)
-            reference_loc = SimReferenceArgument(ptr_loc, referenced_loc)
-            return reference_loc
+            ptr_loc = self.RETURN_VAL if perspective_returned else SimStackArg(0, 4)
+            return SimReferenceArgument(ptr_loc, referenced_loc)
 
         return refine_locs_with_struct_type(self.arch, [self.RETURN_VAL, self.OVERFLOW_RETURN_VAL], ty)
 
@@ -1276,6 +1282,8 @@ class SimCCMicrosoftAMD64(SimCC):
 
     ArgSession = MicrosoftAMD64ArgSession
 
+    STRUCT_RETURN_THRESHOLD = 64
+
     def next_arg(self, session, arg_type):
         if isinstance(arg_type, (SimTypeArray, SimTypeFixedSizeArray)):  # hack
             arg_type = SimTypePointer(arg_type.elem_type).with_arch(self.arch)
@@ -1295,13 +1303,31 @@ class SimCCMicrosoftAMD64(SimCC):
 
         referenced_locs = [SimStackArg(offset, self.arch.bytes) for offset in range(0, byte_size, self.arch.bytes)]
         referenced_loc = refine_locs_with_struct_type(self.arch, referenced_locs, arg_type)
-        reference_loc = SimReferenceArgument(int_loc, referenced_loc)
-        return reference_loc
+        return SimReferenceArgument(int_loc, referenced_loc)
 
     def return_in_implicit_outparam(self, ty):
         if isinstance(ty, SimTypeBottom):
             return False
-        return not isinstance(ty, SimTypeFloat) and ty.size > 64
+        return not isinstance(ty, SimTypeFloat) and ty.size > self.STRUCT_RETURN_THRESHOLD
+
+    def return_val(self, ty, perspective_returned=False):
+        if ty._arch is None:
+            ty = ty.with_arch(self.arch)
+        if not isinstance(ty, SimStruct):
+            return super().return_val(ty, perspective_returned)
+
+        if ty.size > self.STRUCT_RETURN_THRESHOLD:
+            # TODO this code is duplicated a ton of places. how should it be a function?
+            byte_size = ty.size // self.arch.byte_width
+            referenced_locs = [SimStackArg(offset, self.arch.bytes) for offset in range(0, byte_size, self.arch.bytes)]
+            referenced_loc = refine_locs_with_struct_type(self.arch, referenced_locs, ty)
+            if perspective_returned:
+                ptr_loc = self.RETURN_VAL
+            else:
+                ptr_loc = self.next_arg(self.ArgSession(self), SimTypePointer(SimTypeBottom()).with_arch(self.arch))
+            return SimReferenceArgument(ptr_loc, referenced_loc)
+
+        return refine_locs_with_struct_type(self.arch, [self.RETURN_VAL], ty)
 
 
 class SimCCSyscall(SimCC):
@@ -1314,7 +1340,7 @@ class SimCCSyscall(SimCC):
 
     @staticmethod
     def syscall_num(state) -> int:
-        raise NotImplementedError()
+        raise NotImplementedError
 
     def linux_syscall_update_error_reg(self, state, expr):
         # special handling for Linux syscalls: on some architectures (mips/a3, powerpc/cr0_0) a bool indicating success
@@ -1323,10 +1349,8 @@ class SimCCSyscall(SimCC):
             return expr
         if type(expr) is int:
             expr = claripy.BVV(expr, state.arch.bits)
-        try:
+        with contextlib.suppress(AttributeError):
             expr = expr.ast
-        except AttributeError:
-            pass
         nbits = self.ERROR_REG.size * state.arch.byte_width
         error_cond = claripy.UGE(expr, self.SYSCALL_ERRNO_START)
         if state.solver.is_false(error_cond):
@@ -1485,29 +1509,24 @@ class SimCCSystemVAMD64(SimCC):
             byte_size = ty.size // self.arch.byte_width
             referenced_locs = [SimStackArg(offset, self.arch.bytes) for offset in range(0, byte_size, self.arch.bytes)]
             referenced_loc = refine_locs_with_struct_type(self.arch, referenced_locs, ty)
-            if perspective_returned:
-                ptr_loc = self.RETURN_VAL
+            ptr_loc = self.RETURN_VAL if perspective_returned else SimRegArg("rdi", 8)
+            return SimReferenceArgument(ptr_loc, referenced_loc)
+        mapped_classes = []
+        int_iter = iter([self.RETURN_VAL, self.OVERFLOW_RETURN_VAL])
+        fp_iter = iter([self.FP_RETURN_VAL, self.OVERFLOW_FP_RETURN_VAL])
+        for cls in classification:
+            if cls == "SSEUP":
+                mapped_classes.append(mapped_classes[-1].sse_extend(self.arch.bytes))
+            elif cls == "NO_CLASS":
+                raise NotImplementedError("Bug. Report to @rhelmot")
+            elif cls == "INTEGER":
+                mapped_classes.append(next(int_iter))
+            elif cls == "SSE":
+                mapped_classes.append(next(fp_iter))
             else:
-                ptr_loc = SimRegArg("rdi", 8)
-            reference_loc = SimReferenceArgument(ptr_loc, referenced_loc)
-            return reference_loc
-        else:
-            mapped_classes = []
-            int_iter = iter([self.RETURN_VAL, self.OVERFLOW_RETURN_VAL])
-            fp_iter = iter([self.FP_RETURN_VAL, self.OVERFLOW_FP_RETURN_VAL])
-            for cls in classification:
-                if cls == "SSEUP":
-                    mapped_classes.append(mapped_classes[-1].sse_extend(self.arch.bytes))
-                elif cls == "NO_CLASS":
-                    raise NotImplementedError("Bug. Report to @rhelmot")
-                elif cls == "INTEGER":
-                    mapped_classes.append(next(int_iter))
-                elif cls == "SSE":
-                    mapped_classes.append(next(fp_iter))
-                else:
-                    raise NotImplementedError("Bug. Report to @rhelmot")
+                raise NotImplementedError("Bug. Report to @rhelmot")
 
-            return refine_locs_with_struct_type(self.arch, mapped_classes, ty)
+        return refine_locs_with_struct_type(self.arch, mapped_classes, ty)
 
     def return_in_implicit_outparam(self, ty):
         if isinstance(ty, SimTypeBottom):
@@ -1519,15 +1538,12 @@ class SimCCSystemVAMD64(SimCC):
         if chunksize is None:
             chunksize = self.arch.bytes
         # treat BOT as INTEGER
-        if isinstance(ty, SimTypeBottom):
-            nchunks = 1
-        else:
-            nchunks = (ty.size // self.arch.byte_width + chunksize - 1) // chunksize
+        nchunks = 1 if isinstance(ty, SimTypeBottom) else (ty.size // self.arch.byte_width + chunksize - 1) // chunksize
         if isinstance(ty, (SimTypeInt, SimTypeChar, SimTypePointer, SimTypeNum, SimTypeBottom, SimTypeReference)):
             return ["INTEGER"] * nchunks
-        elif isinstance(ty, (SimTypeFloat,)):
+        if isinstance(ty, (SimTypeFloat,)):
             return ["SSE"] + ["SSEUP"] * (nchunks - 1)
-        elif isinstance(ty, (SimStruct, SimTypeFixedSizeArray, SimUnion)):
+        if isinstance(ty, (SimStruct, SimTypeFixedSizeArray, SimUnion)):
             if ty.size > 512:
                 return ["MEMORY"] * nchunks
             flattened = self._flatten(ty)
@@ -1551,8 +1567,7 @@ class SimCCSystemVAMD64(SimCC):
                 if result[i] == "SSEUP" and result[i - 1] not in ("SSE", "SSEUP"):
                     result[i] = "SSE"
             return result
-        else:
-            raise NotImplementedError("Ummmmm... not sure what goes here. report bug to @rhelmot")
+        raise NotImplementedError("Ummmmm... not sure what goes here. report bug to @rhelmot")
 
     def _flatten(self, ty) -> dict[int, list[SimType]] | None:
         result: dict[int, list[SimType]] = defaultdict(list)
@@ -1670,12 +1685,7 @@ class SimCCARM(SimCC):
                     raise NotImplementedError("Bug. Report to @rhelmot")
                 elif cls == "MEMORY":
                     mapped_classes.append(next(session.both_iter))
-                elif cls == "INTEGER":
-                    try:
-                        mapped_classes.append(next(session.int_iter))
-                    except StopIteration:
-                        mapped_classes.append(next(session.both_iter))
-                elif cls == "SINGLEP":
+                elif cls == "INTEGER" or cls == "SINGLEP":
                     try:
                         mapped_classes.append(next(session.int_iter))
                     except StopIteration:
@@ -1692,19 +1702,16 @@ class SimCCARM(SimCC):
         if chunksize is None:
             chunksize = self.arch.bytes
         # treat BOT as INTEGER
-        if isinstance(ty, SimTypeBottom):
-            nchunks = 1
-        else:
-            nchunks = (ty.size // self.arch.byte_width + chunksize - 1) // chunksize
+        nchunks = 1 if isinstance(ty, SimTypeBottom) else (ty.size // self.arch.byte_width + chunksize - 1) // chunksize
         if isinstance(ty, (SimTypeInt, SimTypeChar, SimTypePointer, SimTypeNum, SimTypeBottom, SimTypeReference)):
             return ["INTEGER"] * nchunks
-        elif isinstance(ty, (SimTypeFloat,)):
+        if isinstance(ty, (SimTypeFloat,)):
             if ty.size == 64:
                 return ["DOUBLEP"]
-            elif ty.size == 32:
+            if ty.size == 32:
                 return ["SINGLEP"]
             return ["NO_CLASS"]
-        elif isinstance(ty, (SimStruct, SimTypeFixedSizeArray, SimUnion)):
+        if isinstance(ty, (SimStruct, SimTypeFixedSizeArray, SimUnion)):
             flattened = self._flatten(ty)
             if flattened is None:
                 return ["MEMORY"] * nchunks
@@ -1719,8 +1726,7 @@ class SimCCARM(SimCC):
                         subclass = subresult[i * chunksize]
                         result[idx] = self._combine_classes(result[idx], subclass)
             return result
-        else:
-            raise NotImplementedError("Ummmmm... not sure what goes here. report bug to @rhelmot")
+        raise NotImplementedError("Ummmmm... not sure what goes here. report bug to @rhelmot")
 
     def _combine_classes(self, cls1, cls2):
         if cls1 == cls2:
@@ -1806,8 +1812,7 @@ class SimCCARMLinuxSyscall(SimCCSyscall):
 
         if len(svc_num) == 32 and (svc_num > 0x900000).is_true() and (svc_num < 0x90FFFF).is_true():
             return svc_num - 0x900000
-        else:
-            return state.regs.r7
+        return state.regs.r7
 
 
 class SimCCAArch64(SimCC):
@@ -1916,19 +1921,16 @@ class SimCCO32(SimCC):
         if chunksize is None:
             chunksize = self.arch.bytes
         # treat BOT as INTEGER
-        if isinstance(ty, SimTypeBottom):
-            nchunks = 1
-        else:
-            nchunks = (ty.size // self.arch.byte_width + chunksize - 1) // chunksize
+        nchunks = 1 if isinstance(ty, SimTypeBottom) else (ty.size // self.arch.byte_width + chunksize - 1) // chunksize
         if isinstance(ty, (SimTypeInt, SimTypeChar, SimTypePointer, SimTypeNum, SimTypeBottom, SimTypeReference)):
             return ["INTEGER"] * nchunks
-        elif isinstance(ty, (SimTypeFloat,)):
+        if isinstance(ty, (SimTypeFloat,)):
             if ty.size == 64:
                 return ["DOUBLEP"]
-            elif ty.size == 32:
+            if ty.size == 32:
                 return ["SINGLEP"]
             return ["NO_CLASS"]
-        elif isinstance(ty, (SimStruct, SimTypeFixedSizeArray, SimUnion)):
+        if isinstance(ty, (SimStruct, SimTypeFixedSizeArray, SimUnion)):
             flattened = self._flatten(ty)
             if flattened is None:
                 return ["MEMORY"] * nchunks
@@ -1943,8 +1945,7 @@ class SimCCO32(SimCC):
                         subclass = subresult[i * chunksize]
                         result[idx] = self._combine_classes(result[idx], subclass)
             return result
-        else:
-            raise NotImplementedError("Ummmmm... not sure what goes here. report bug to @rhelmot")
+        raise NotImplementedError("Ummmmm... not sure what goes here. report bug to @rhelmot")
 
     def _combine_classes(self, cls1, cls2):
         if cls1 == cls2:
@@ -2253,7 +2254,7 @@ ARCH_NAME_ALIASES = {
     "PPC32": ["powerpc32"],
     "PPC64": ["powerpc64"],
     "Soot": [],
-    "AVR8": [],
+    "AVR8": ["avr8"],
     "MSP": [],
     "S390X": [],
 }
@@ -2300,8 +2301,7 @@ def default_cc(  # pylint:disable=unused-argument
     if alias not in cc_map or platform not in cc_map[alias]:
         if default is not ...:
             return default
-        else:
-            return None
+        return None
     return cc_map[alias][platform]