angr 9.2.117__py3-none-manylinux2014_aarch64.whl → 9.2.119__py3-none-manylinux2014_aarch64.whl

angr/analyses/reaching_definitions/engine_ail.py

@@ -1,4 +1,5 @@
 # pylint:disable=missing-class-docstring,too-many-boolean-expressions
+from __future__ import annotations
 from itertools import chain
 from collections.abc import Iterable
 import logging
@@ -139,9 +140,8 @@ class SimEngineRDAIL(
         handler = self._expr_handlers.get(type(expr), None)
         if handler is not None:
             return handler(expr)
-        else:
-            self.l.warning("Unsupported expression type %s.", type(expr).__name__)
-            return MultiValues(self.state.top(self.arch.bits))
+        self.l.warning("Unsupported expression type %s.", type(expr).__name__)
+        return MultiValues(self.state.top(self.arch.bits))
 
     def _ail_handle_Assignment(self, stmt):
         """
@@ -466,10 +466,7 @@ class SimEngineRDAIL(
         defs: Iterable[Definition] | None = None
         for vs in value.values():
             for v in vs:
-                if defs is None:
-                    defs = self.state.extract_defs(v)
-                else:
-                    defs = chain(defs, self.state.extract_defs(v))
+                defs = self.state.extract_defs(v) if defs is None else chain(defs, self.state.extract_defs(v))
 
         if defs is None:
             # define it right away as an external dependency
@@ -658,16 +655,18 @@ class SimEngineRDAIL(
             r = MultiValues(self.state.top(bits))
         elif expr0_v is None and expr1_v is not None:
             # adding a single value to a multivalue
-            if expr0.count() == 1 and 0 in expr0:
-                if all(v.concrete or self.state.is_stack_address(v) for v in expr0[0]):
-                    vs = {v + expr1_v for v in expr0[0]}
-                    r = MultiValues(offset_to_values={0: vs})
+            if (
+                expr0.count() == 1
+                and 0 in expr0
+                and all(v.concrete or self.state.is_stack_address(v) for v in expr0[0])
+            ):
+                vs = {v + expr1_v for v in expr0[0]}
+                r = MultiValues(offset_to_values={0: vs})
         elif expr0_v is not None and expr1_v is None:
             # adding a single value to a multivalue
-            if expr1.count() == 1 and 0 in expr1:
-                if all(v.concrete for v in expr1[0]):
-                    vs = {v + expr0_v for v in expr1[0]}
-                    r = MultiValues(offset_to_values={0: vs})
+            if expr1.count() == 1 and 0 in expr1 and all(v.concrete for v in expr1[0]):
+                vs = {v + expr0_v for v in expr1[0]}
+                r = MultiValues(offset_to_values={0: vs})
         else:
             # adding two single values together
             if (expr0_v.concrete or self.state.is_stack_address(expr0_v)) and expr1_v.concrete:
@@ -691,16 +690,18 @@ class SimEngineRDAIL(
             r = MultiValues(self.state.top(bits))
         elif expr0_v is None and expr1_v is not None:
             # subtracting a single value from a multivalue
-            if expr0.count() == 1 and 0 in expr0:
-                if all(v.concrete or self.state.is_stack_address(v) for v in expr0[0]):
-                    vs = {v - expr1_v for v in expr0[0]}
-                    r = MultiValues(offset_to_values={0: vs})
+            if (
+                expr0.count() == 1
+                and 0 in expr0
+                and all(v.concrete or self.state.is_stack_address(v) for v in expr0[0])
+            ):
+                vs = {v - expr1_v for v in expr0[0]}
+                r = MultiValues(offset_to_values={0: vs})
         elif expr0_v is not None and expr1_v is None:
             # subtracting a single value from a multivalue
-            if expr1.count() == 1 and 0 in expr1:
-                if all(v.concrete for v in expr1[0]):
-                    vs = {expr0_v - v for v in expr1[0]}
-                    r = MultiValues(offset_to_values={0: vs})
+            if expr1.count() == 1 and 0 in expr1 and all(v.concrete for v in expr1[0]):
+                vs = {expr0_v - v for v in expr1[0]}
+                r = MultiValues(offset_to_values={0: vs})
         else:
             if (expr0_v.concrete or self.state.is_stack_address(expr0_v)) and expr1_v.concrete:
                 r = MultiValues(expr0_v - expr1_v)
@@ -717,8 +718,7 @@ class SimEngineRDAIL(
         self._expr(arg1)
         bits = expr.bits
 
-        r = MultiValues(self.state.top(bits))
-        return r
+        return MultiValues(self.state.top(bits))
 
     def _ail_handle_DivMod(self, expr):
         return self._ail_handle_Div(expr)
@@ -730,8 +730,7 @@ class SimEngineRDAIL(
         self._expr(arg1)
         bits = expr.bits
 
-        r = MultiValues(self.state.top(bits))
-        return r
+        return MultiValues(self.state.top(bits))
 
     _ail_handle_AddV = _ail_handle_Add
     _ail_handle_MulV = _ail_handle_Mul
@@ -743,8 +742,7 @@ class SimEngineRDAIL(
         self._expr(arg1)
         bits = expr.bits
 
-        r = MultiValues(self.state.top(bits))
-        return r
+        return MultiValues(self.state.top(bits))
 
     def _ail_handle_Mod(self, expr):
         arg0, arg1 = expr.operands
@@ -753,8 +751,7 @@ class SimEngineRDAIL(
         self._expr(arg1)
         bits = expr.bits
 
-        r = MultiValues(self.state.top(bits))
-        return r
+        return MultiValues(self.state.top(bits))
 
     def _ail_handle_Mul(self, expr: ailment.Expr.BinaryOp) -> MultiValues:
         expr0: MultiValues = self._expr(expr.operands[0])
@@ -784,22 +781,18 @@ class SimEngineRDAIL(
             r = MultiValues(self.state.top(bits))
         elif expr0_v is None and expr1_v is not None:
             # each value in expr0 >> expr1_v
-            if expr0.count() == 1 and 0 in expr0:
-                if all(v.concrete for v in expr0[0]) and expr1_v.concrete:
-                    vs = {
-                        (claripy.LShR(v, expr1_v.concrete_value) if v.concrete else self.state.top(bits))
-                        for v in expr0[0]
-                    }
-                    r = MultiValues(offset_to_values={0: vs})
+            if expr0.count() == 1 and 0 in expr0 and all(v.concrete for v in expr0[0]) and expr1_v.concrete:
+                vs = {
+                    (claripy.LShR(v, expr1_v.concrete_value) if v.concrete else self.state.top(bits)) for v in expr0[0]
+                }
+                r = MultiValues(offset_to_values={0: vs})
         elif expr0_v is not None and expr1_v is None:
             # expr0_v >> each value in expr1
-            if expr1.count() == 1 and 0 in expr1:
-                if all(v.concrete for v in expr1[0]):
-                    vs = {
-                        (claripy.LShR(expr0_v, v.concrete_value) if v.concrete else self.state.top(bits))
-                        for v in expr1[0]
-                    }
-                    r = MultiValues(offset_to_values={0: vs})
+            if expr1.count() == 1 and 0 in expr1 and all(v.concrete for v in expr1[0]):
+                vs = {
+                    (claripy.LShR(expr0_v, v.concrete_value) if v.concrete else self.state.top(bits)) for v in expr1[0]
+                }
+                r = MultiValues(offset_to_values={0: vs})
         else:
             if expr0_v.concrete and expr1_v.concrete:
                 r = MultiValues(claripy.LShR(expr0_v, expr1_v.concrete_value))
@@ -822,22 +815,18 @@ class SimEngineRDAIL(
             r = MultiValues(self.state.top(bits))
         elif expr0_v is None and expr1_v is not None:
             # each value in expr0 >> expr1_v
-            if expr0.count() == 1 and 0 in expr0:
-                if all(v.concrete for v in expr0[0]) and expr1_v.concrete:
-                    vs = {
-                        (claripy.LShR(v, expr1_v.concrete_value) if v.concrete else self.state.top(bits))
-                        for v in expr0[0]
-                    }
-                    r = MultiValues(offset_to_values={0: vs})
+            if expr0.count() == 1 and 0 in expr0 and all(v.concrete for v in expr0[0]) and expr1_v.concrete:
+                vs = {
+                    (claripy.LShR(v, expr1_v.concrete_value) if v.concrete else self.state.top(bits)) for v in expr0[0]
+                }
+                r = MultiValues(offset_to_values={0: vs})
         elif expr0_v is not None and expr1_v is None:
             # expr0_v >> each value in expr1
-            if expr1.count() == 1 and 0 in expr1:
-                if all(v.concrete for v in expr1[0]):
-                    vs = {
-                        (claripy.LShR(expr0_v, v.concrete_value) if v.concrete else self.state.top(bits))
-                        for v in expr1[0]
-                    }
-                    r = MultiValues(offset_to_values={0: vs})
+            if expr1.count() == 1 and 0 in expr1 and all(v.concrete for v in expr1[0]):
+                vs = {
+                    (claripy.LShR(expr0_v, v.concrete_value) if v.concrete else self.state.top(bits)) for v in expr1[0]
+                }
+                r = MultiValues(offset_to_values={0: vs})
         else:
             if expr0_v.concrete and expr1_v.concrete:
                 r = MultiValues(expr0_v >> expr1_v.concrete_value)
@@ -860,16 +849,14 @@ class SimEngineRDAIL(
             r = MultiValues(self.state.top(bits))
         elif expr0_v is None and expr1_v is not None:
             # each value in expr0 << expr1_v
-            if expr0.count() == 1 and 0 in expr0:
-                if all(v.concrete for v in expr0[0]) and expr1_v.concrete:
-                    vs = {((v << expr1_v.concrete_value) if v.concrete else self.state.top(bits)) for v in expr0[0]}
-                    r = MultiValues(offset_to_values={0: vs})
+            if expr0.count() == 1 and 0 in expr0 and all(v.concrete for v in expr0[0]) and expr1_v.concrete:
+                vs = {((v << expr1_v.concrete_value) if v.concrete else self.state.top(bits)) for v in expr0[0]}
+                r = MultiValues(offset_to_values={0: vs})
         elif expr0_v is not None and expr1_v is None:
             # expr0_v >> each value in expr1
-            if expr1.count() == 1 and 0 in expr1:
-                if all(v.concrete for v in expr1[0]):
-                    vs = {((expr0_v << v.concrete_value) if v.concrete else self.state.top(bits)) for v in expr1[0]}
-                    r = MultiValues(offset_to_values={0: vs})
+            if expr1.count() == 1 and 0 in expr1 and all(v.concrete for v in expr1[0]):
+                vs = {((expr0_v << v.concrete_value) if v.concrete else self.state.top(bits)) for v in expr1[0]}
+                r = MultiValues(offset_to_values={0: vs})
         else:
             if expr0_v.concrete and expr1_v.concrete:
                 r = MultiValues(expr0_v << expr1_v.concrete_value)
@@ -903,21 +890,18 @@ class SimEngineRDAIL(
         expr1_v = expr1.one_value()
 
         if expr0_v is None and expr1_v is None:
-            r = MultiValues(self.state.top(bits))
-            return r
+            return MultiValues(self.state.top(bits))
 
         if expr0_v is None and expr1_v is not None:
             # expr1_v & each value in expr0
-            if expr0.count() == 1 and 0 in expr0:
-                if all(v.concrete for v in expr0[0]):
-                    vs = {v & expr1_v for v in expr0[0]}
-                    r = MultiValues(offset_to_values={0: vs})
+            if expr0.count() == 1 and 0 in expr0 and all(v.concrete for v in expr0[0]):
+                vs = {v & expr1_v for v in expr0[0]}
+                r = MultiValues(offset_to_values={0: vs})
         elif expr0_v is not None and expr1_v is None:
             # expr0_v & each value in expr1
-            if expr1.count() == 1 and 0 in expr1:
-                if all(v.concrete for v in expr1[0]):
-                    vs = {expr0_v & v for v in expr1[0]}
-                    r = MultiValues(offset_to_values={0: vs})
+            if expr1.count() == 1 and 0 in expr1 and all(v.concrete for v in expr1[0]):
+                vs = {expr0_v & v for v in expr1[0]}
+                r = MultiValues(offset_to_values={0: vs})
         else:
             # special handling for stack alignment
             if self.state.is_stack_address(expr0_v):
@@ -944,16 +928,14 @@ class SimEngineRDAIL(
             r = MultiValues(self.state.top(bits))
         elif expr0_v is None and expr1_v is not None:
             # expr1_v | each value in expr0
-            if expr0.count() == 1 and 0 in expr0:
-                if all(v.concrete for v in expr0[0]):
-                    vs = {v | expr1_v for v in expr0[0]}
-                    r = MultiValues(offset_to_values={0: vs})
+            if expr0.count() == 1 and 0 in expr0 and all(v.concrete for v in expr0[0]):
+                vs = {v | expr1_v for v in expr0[0]}
+                r = MultiValues(offset_to_values={0: vs})
         elif expr0_v is not None and expr1_v is None:
             # expr0_v | each value in expr1
-            if expr1.count() == 1 and 0 in expr1:
-                if all(v.concrete for v in expr1[0]):
-                    vs = {expr0_v | v for v in expr1[0]}
-                    r = MultiValues(offset_to_values={0: vs})
+            if expr1.count() == 1 and 0 in expr1 and all(v.concrete for v in expr1[0]):
+                vs = {expr0_v | v for v in expr1[0]}
+                r = MultiValues(offset_to_values={0: vs})
         else:
             if expr0_v.concrete and expr1_v.concrete:
                 r = MultiValues(expr0_v | expr1_v)
@@ -974,11 +956,9 @@ class SimEngineRDAIL(
         # TODO: can maybe be smarter about this. if we can determine that expr0 is never falsey, we can just return it,
         # TODO: or if it's always falsey we can return expr1 (did I get this backwards?)
         if expr0_v is None or expr1_v is None:
-            r = MultiValues(self.state.top(bits))
-            return r
+            return MultiValues(self.state.top(bits))
 
-        r = MultiValues(claripy.If(expr0_v == 0, expr0_v, expr1_v))
-        return r
+        return MultiValues(claripy.If(expr0_v == 0, expr0_v, expr1_v))
 
     def _ail_handle_LogicalOr(self, expr: ailment.Expr.BinaryOp) -> MultiValues:
         expr0: MultiValues = self._expr(expr.operands[0])
@@ -989,11 +969,9 @@ class SimEngineRDAIL(
         expr1_v = expr1.one_value()
 
         if expr0_v is None or expr1_v is None:
-            r = MultiValues(self.state.top(bits))
-            return r
+            return MultiValues(self.state.top(bits))
 
-        r = MultiValues(claripy.If(expr0_v != 0, expr0_v, expr1_v))
-        return r
+        return MultiValues(claripy.If(expr0_v != 0, expr0_v, expr1_v))
 
     def _ail_handle_LogicalXor(self, expr: ailment.Expr.BinaryOp) -> MultiValues:
         expr0: MultiValues = self._expr(expr.operands[0])
@@ -1004,11 +982,9 @@ class SimEngineRDAIL(
         expr1_v = expr1.one_value()
 
         if expr0_v is None or expr1_v is None:
-            r = MultiValues(self.state.top(bits))
-            return r
+            return MultiValues(self.state.top(bits))
 
-        r = MultiValues(claripy.If(expr0_v != 0, expr1_v, expr0_v))
-        return r
+        return MultiValues(claripy.If(expr0_v != 0, expr1_v, expr0_v))
 
     def _ail_handle_Xor(self, expr: ailment.Expr.BinaryOp) -> MultiValues:
         expr0: MultiValues = self._expr(expr.operands[0])
@@ -1023,16 +999,14 @@ class SimEngineRDAIL(
             r = MultiValues(self.state.top(bits))
         elif expr0_v is None and expr1_v is not None:
             # expr1_v ^ each value in expr0
-            if expr0.count() == 1 and 0 in expr0:
-                if all(v.concrete for v in expr0[0]):
-                    vs = {v ^ expr1_v for v in expr0[0]}
-                    r = MultiValues(offset_to_values={0: vs})
+            if expr0.count() == 1 and 0 in expr0 and all(v.concrete for v in expr0[0]):
+                vs = {v ^ expr1_v for v in expr0[0]}
+                r = MultiValues(offset_to_values={0: vs})
         elif expr0_v is not None and expr1_v is None:
             # expr0_v ^ each value in expr1
-            if expr1.count() == 1 and 0 in expr1:
-                if all(v.concrete for v in expr1[0]):
-                    vs = {expr0_v ^ v for v in expr1[0]}
-                    r = MultiValues(offset_to_values={0: vs})
+            if expr1.count() == 1 and 0 in expr1 and all(v.concrete for v in expr1[0]):
+                vs = {expr0_v ^ v for v in expr1[0]}
+                r = MultiValues(offset_to_values={0: vs})
         else:
             if expr0_v.concrete and expr1_v.concrete:
                 r = MultiValues(expr0_v ^ expr1_v)
@@ -1046,22 +1020,19 @@ class SimEngineRDAIL(
         _ = self._expr(expr.operands[0])
         _ = self._expr(expr.operands[1])
         bits = expr.bits
-        r = MultiValues(self.state.top(bits))
-        return r
+        return MultiValues(self.state.top(bits))
 
     def _ail_handle_SCarry(self, expr: ailment.Expr.BinaryOp) -> MultiValues:
         _ = self._expr(expr.operands[0])
         _ = self._expr(expr.operands[1])
         bits = expr.bits
-        r = MultiValues(self.state.top(bits))
-        return r
+        return MultiValues(self.state.top(bits))
 
     def _ail_handle_SBorrow(self, expr: ailment.Expr.BinaryOp) -> MultiValues:
         _ = self._expr(expr.operands[0])
         _ = self._expr(expr.operands[1])
         bits = expr.bits
-        r = MultiValues(self.state.top(bits))
-        return r
+        return MultiValues(self.state.top(bits))
 
     def _ail_handle_Concat(self, expr: ailment.Expr.BinaryOp) -> MultiValues:
         expr0: MultiValues = self._expr(expr.operands[0])
@@ -1076,16 +1047,14 @@ class SimEngineRDAIL(
             r = MultiValues(self.state.top(bits))
         elif expr0_v is None and expr1_v is not None:
             # concatenate expr1_v with each value in expr0
-            if expr0.count() == 1 and 0 in expr0:
-                if all(v.concrete for v in expr0[0]):
-                    vs = {claripy.Concat(v, expr1_v) for v in expr0[0]}
-                    r = MultiValues(offset_to_values={0: vs})
+            if expr0.count() == 1 and 0 in expr0 and all(v.concrete for v in expr0[0]):
+                vs = {claripy.Concat(v, expr1_v) for v in expr0[0]}
+                r = MultiValues(offset_to_values={0: vs})
         elif expr0_v is not None and expr1_v is None:
             # concatenate expr0_v with each value in expr1
-            if expr1.count() == 1 and 0 in expr1:
-                if all(v.concrete for v in expr1[0]):
-                    vs = {claripy.Concat(expr0_v, v) for v in expr1[0]}
-                    r = MultiValues(offset_to_values={0: vs})
+            if expr1.count() == 1 and 0 in expr1 and all(v.concrete for v in expr1[0]):
+                vs = {claripy.Concat(expr0_v, v) for v in expr1[0]}
+                r = MultiValues(offset_to_values={0: vs})
         else:
             if expr0_v.concrete and expr1_v.concrete:
                 r = MultiValues(claripy.Concat(expr0_v, expr1_v))
@@ -1150,8 +1119,7 @@ class SimEngineRDAIL(
             elif expr.bits == 32:
                 sort = FSORT_FLOAT
             return MultiValues(claripy.FPV(expr.value, sort))
-        else:
-            return MultiValues(claripy.BVV(expr.value, expr.bits))
+        return MultiValues(claripy.BVV(expr.value, expr.bits))
 
     def _ail_handle_StackBaseOffset(self, expr: ailment.Expr.StackBaseOffset) -> MultiValues:
         stack_addr = self.state.stack_address(expr.offset)

angr/analyses/reaching_definitions/engine_vex.py

@@ -1,5 +1,6 @@
+from __future__ import annotations
 from itertools import chain
-from typing import Optional, TYPE_CHECKING
+from typing import TYPE_CHECKING
 from collections.abc import Iterable
 import logging
 
@@ -42,8 +43,8 @@ class SimEngineRDVEX(
     def __init__(self, project, functions=None, function_handler=None):
         super().__init__()
         self.project = project
-        self.functions: Optional["FunctionManager"] = functions
-        self._function_handler: Optional["FunctionHandler"] = function_handler
+        self.functions: FunctionManager | None = functions
+        self._function_handler: FunctionHandler | None = function_handler
         self._visited_blocks = None
         self._dep_graph = None
 
@@ -513,11 +514,9 @@ class SimEngineRDVEX(
 
         if claripy.is_true(cond_v):
             return iftrue
-        elif claripy.is_false(cond_v):
+        if claripy.is_false(cond_v):
             return iffalse
-        else:
-            data = iftrue.merge(iffalse)
-            return data
+        return iftrue.merge(iffalse)
 
     #
     # Unary operation handlers
@@ -598,15 +597,13 @@ class SimEngineRDVEX(
         _, _ = self._expr(expr.args[0]), self._expr(expr.args[1])
         bits = expr.result_size(self.tyenv)
         # Need to actually implement this later
-        r = MultiValues(self.state.top(bits))
-        return r
+        return MultiValues(self.state.top(bits))
 
     def _handle_16HLto32(self, expr):
         _, _ = self._expr(expr.args[0]), self._expr(expr.args[1])
         bits = expr.result_size(self.tyenv)
         # Need to actually implement this later
-        r = MultiValues(self.state.top(bits))
-        return r
+        return MultiValues(self.state.top(bits))
 
     def _handle_Add(self, expr):
         expr0, expr1 = self._expr(expr.args[0]), self._expr(expr.args[1])
@@ -727,10 +724,7 @@ class SimEngineRDVEX(
         else:
             if expr0_v.concrete and expr1_v.concrete:
                 # dividing two single values
-                if expr1_v.concrete_value == 0:
-                    r = MultiValues(self.state.top(bits))
-                else:
-                    r = MultiValues(expr0_v / expr1_v)
+                r = MultiValues(self.state.top(bits)) if expr1_v.concrete_value == 0 else MultiValues(expr0_v / expr1_v)
 
         if r is None:
             r = MultiValues(self.state.top(bits))
@@ -741,9 +735,7 @@ class SimEngineRDVEX(
         _, _ = self._expr(expr.args[0]), self._expr(expr.args[1])
         bits = expr.result_size(self.tyenv)
 
-        r = MultiValues(self.state.top(bits))
-
-        return r
+        return MultiValues(self.state.top(bits))
 
     def _handle_And(self, expr):
         expr0, expr1 = self._expr(expr.args[0]), self._expr(expr.args[1])
@@ -854,10 +846,7 @@ class SimEngineRDVEX(
             if e1 > bits:
                 return claripy.BVV(0, bits)
 
-            if claripy.is_true(e0 >> (bits - 1) == 0):
-                head = claripy.BVV(0, bits)
-            else:
-                head = ((1 << e1) - 1) << (bits - e1)
+            head = claripy.BVV(0, bits) if claripy.is_true(e0 >> bits - 1 == 0) else (1 << e1) - 1 << bits - e1
             return head | (e0 >> e1)
 
         if expr0_v is None and expr1_v is None:
@@ -970,7 +959,7 @@ class SimEngineRDVEX(
         if e0 is not None and e1 is not None:
             if not e0.symbolic and not e1.symbolic:
                 return MultiValues(claripy.BVV(1, 1) if e0.concrete_value == e1.concrete_value else claripy.BVV(0, 1))
-            elif e0 is e1:
+            if e0 is e1:
                 return MultiValues(claripy.BVV(1, 1))
             return MultiValues(self.state.top(1))
 
@@ -986,7 +975,7 @@ class SimEngineRDVEX(
         if e0 is not None and e1 is not None:
             if not e0.symbolic and not e1.symbolic:
                 return MultiValues(claripy.BVV(1, 1) if e0.concrete_value != e1.concrete_value else claripy.BVV(0, 1))
-            elif e0 is e1:
+            if e0 is e1:
                 return MultiValues(claripy.BVV(0, 1))
         return MultiValues(self.state.top(1))
 
@@ -1000,7 +989,7 @@ class SimEngineRDVEX(
         if e0 is not None and e1 is not None:
             if not e0.symbolic and not e1.symbolic:
                 return MultiValues(claripy.BVV(1, 1) if e0.concrete_value < e1.concrete_value else claripy.BVV(0, 1))
-            elif e0 is e1:
+            if e0 is e1:
                 return MultiValues(claripy.BVV(0, 1))
         return MultiValues(self.state.top(1))
 
@@ -1014,7 +1003,7 @@ class SimEngineRDVEX(
         if e0 is not None and e1 is not None:
             if not e0.symbolic and not e1.symbolic:
                 return MultiValues(claripy.BVV(1, 1) if e0.concrete_value <= e1.concrete_value else claripy.BVV(0, 1))
-            elif e0 is e1:
+            if e0 is e1:
                 return MultiValues(claripy.BVV(0, 1))
         return MultiValues(self.state.top(1))
 
@@ -1028,7 +1017,7 @@ class SimEngineRDVEX(
         if e0 is not None and e1 is not None:
             if not e0.symbolic and not e1.symbolic:
                 return MultiValues(claripy.BVV(1, 1) if e0.concrete_value > e1.concrete_value else claripy.BVV(0, 1))
-            elif e0 is e1:
+            if e0 is e1:
                 return MultiValues(claripy.BVV(0, 1))
         return MultiValues(self.state.top(1))
 
@@ -1042,7 +1031,7 @@ class SimEngineRDVEX(
         if e0 is not None and e1 is not None:
             if not e0.symbolic and not e1.symbolic:
                 return MultiValues(claripy.BVV(1, 1) if e0.concrete_value >= e1.concrete_value else claripy.BVV(0, 1))
-            elif e0 is e1:
+            if e0 is e1:
                 return MultiValues(claripy.BVV(0, 1))
         return MultiValues(self.state.top(1))
 
@@ -1062,11 +1051,10 @@ class SimEngineRDVEX(
                 e1 = e1.concrete_value
                 if e0 < e1:
                     return MultiValues(claripy.BVV(0x8, bits))
-                elif e0 > e1:
+                if e0 > e1:
                     return MultiValues(claripy.BVV(0x4, bits))
-                else:
-                    return MultiValues(claripy.BVV(0x2, bits))
-            elif e0 is e1:
+                return MultiValues(claripy.BVV(0x2, bits))
+            if e0 is e1:
                 return MultiValues(claripy.BVV(0x2, bits))
 
         return MultiValues(self.state.top(1))