angr 9.2.116__py3-none-win_amd64.whl → 9.2.118__py3-none-win_amd64.whl

angr/state_plugins/trace_additions.py

@@ -12,6 +12,8 @@ This can happen in challenge response if all of the values in the flag page are
 before being printed.
 """
 
+from __future__ import annotations
+
 import logging
 import string
 
@@ -52,10 +54,9 @@ class FormatInfoStrToInt(FormatInfo):
         self.input_base = None
 
     def copy(self):
-        out = FormatInfoStrToInt(
+        return FormatInfoStrToInt(
             self.addr, self.func_name, self.str_arg_num, self.base, self.base_arg, self.allows_negative
         )
-        return out
 
     def compute(self, state):
         self.input_val = angr.calling_conventions.SimCCCdecl(state.arch).arg(state, self.str_arg_num)
@@ -92,10 +93,9 @@ class FormatInfoIntToStr(FormatInfo):
         self.str_dst_addr = None
 
     def copy(self):
-        out = FormatInfoIntToStr(
+        return FormatInfoIntToStr(
             self.addr, self.func_name, self.int_arg_num, self.str_dst_num, self.base, self.base_arg
         )
-        return out
 
     def compute(self, state):
         self.input_val = angr.calling_conventions.SimCCCdecl(state.arch).arg(state, self.int_arg_num)
@@ -120,8 +120,7 @@ class FormatInfoDontConstrain(FormatInfo):
         self.check_symbolic_arg = check_symbolic_arg
 
     def copy(self):
-        out = FormatInfoDontConstrain(self.addr, self.func_name, self.check_symbolic_arg)
-        return out
+        return FormatInfoDontConstrain(self.addr, self.func_name, self.check_symbolic_arg)
 
     def compute(self, state):
         pass
@@ -196,7 +195,7 @@ def end_info_hook(state):
     if pending_info.get_type() == "StrToInt":
         # mark the input
         input_val = state.mem[pending_info.input_val].string.resolved
-        result = state.solver.BVV(state.solver.eval(state.regs.eax, cast_to=bytes))
+        result = claripy.BVV(state.solver.eval(state.regs.eax, cast_to=bytes))
         real_len = chall_resp_plugin.get_real_len(
             input_val, pending_info.input_base, result, pending_info.allows_negative
         )
@@ -207,7 +206,7 @@ def end_info_hook(state):
             return
 
         # result constraint
-        new_var = state.solver.BVS(pending_info.get_type() + "_" + str(pending_info.input_base) + "_result", 32)
+        new_var = claripy.BVS(pending_info.get_type() + "_" + str(pending_info.input_base) + "_result", 32)
         constraint = new_var == result
         chall_resp_plugin.replacement_pairs.append((new_var, state.regs.eax))
         state.regs.eax = new_var
@@ -215,7 +214,7 @@ def end_info_hook(state):
         # finish marking the input
         input_val = state.memory.load(pending_info.input_val, real_len)
         l.debug("string len was %d, value was %d", real_len, state.solver.eval(result))
-        input_bvs = state.solver.BVS(
+        input_bvs = claripy.BVS(
             pending_info.get_type() + "_" + str(pending_info.input_base) + "_input", input_val.size()
         )
         chall_resp_plugin.str_to_int_pairs.append((input_bvs, new_var))
@@ -224,23 +223,19 @@ def end_info_hook(state):
         chall_resp_plugin.replacement_pairs.append((input_bvs, input_val))
     elif pending_info.get_type() == "IntToStr":
         # result constraint
-        result = state.solver.BVV(
-            state.solver.eval(state.mem[pending_info.str_dst_addr].string.resolved, cast_to=bytes)
-        )
+        result = claripy.BVV(state.solver.eval(state.mem[pending_info.str_dst_addr].string.resolved, cast_to=bytes))
         if result is None or result.size() == 0:
             l.warning("zero len string")
             chall_resp_plugin.pop_from_backup()
             return
-        new_var = state.solver.BVS(
-            pending_info.get_type() + "_" + str(pending_info.input_base) + "_result", result.size()
-        )
+        new_var = claripy.BVS(pending_info.get_type() + "_" + str(pending_info.input_base) + "_result", result.size())
         chall_resp_plugin.replacement_pairs.append((new_var, state.mem[pending_info.str_dst_addr].string.resolved))
         state.memory.store(pending_info.str_dst_addr, new_var)
         constraint = new_var == result
 
         # mark the input
         input_val = pending_info.input_val
-        input_bvs = state.solver.BVS(pending_info.get_type() + "_" + str(pending_info.input_base) + "_input", 32)
+        input_bvs = claripy.BVS(pending_info.get_type() + "_" + str(pending_info.input_base) + "_input", 32)
         chall_resp_plugin.int_to_str_pairs.append((input_bvs, new_var))
         chall_resp_plugin.replacement_pairs.append((input_bvs, input_val))
         # here we need the constraint that the input was equal to the StrToInt_input
@@ -257,7 +252,7 @@ def end_info_hook(state):
     state.solver._solver.add_replacement(new_var, result, invalidate_cache=False)
     # dont add this constraint to preconstraints or we lose real constraints
     # chall_resp_plugin.tracer.preconstraints.append(constraint)
-    chall_resp_plugin.state.preconstrainer.variable_map[list(new_var.variables)[0]] = constraint
+    chall_resp_plugin.state.preconstrainer.variable_map[next(iter(new_var.variables))] = constraint
     chall_resp_plugin.pop_from_backup()
 
 
@@ -289,7 +284,7 @@ def syscall_hook(state):
         stdin_min_stdout_reads = state.get_plugin("chall_resp_info").stdin_min_stdout_reads
         stdout_pos = state.solver.eval(state.posix.fd[1].write_pos)
         stdin_pos = state.solver.eval(state.posix.fd[0].read_pos)
-        for i in range(0, stdin_pos):
+        for i in range(stdin_pos):
             if i not in stdin_min_stdout_reads:
                 stdin_min_stdout_reads[i] = stdout_pos
 
@@ -298,8 +293,8 @@ def syscall_hook(state):
         num_bytes = state.solver.eval(state.regs.ecx)
         buf = state.solver.eval(state.regs.ebx)
         if num_bytes != 0:
-            rand_bytes = state.solver.BVS("random", num_bytes * 8)
-            concrete_val = state.solver.BVV("A" * num_bytes)
+            rand_bytes = claripy.BVS("random", num_bytes * 8)
+            concrete_val = claripy.BVV("A" * num_bytes)
             state.solver._solver.add_replacement(rand_bytes, concrete_val, invalidate_cache=False)
             state.memory.store(buf, rand_bytes)
 
@@ -460,7 +455,7 @@ class ChallRespInfo(angr.state_plugins.SimStatePlugin):
     def get_same_length_constraints(self):
         constraints = []
         for str_var, int_var in self.str_to_int_pairs:
-            int_var_name = list(int_var.variables)[0]
+            int_var_name = next(iter(int_var.variables))
             base = int(int_var_name.split("_")[1], 10)
             original_len = str_var.size() // 8
             abs_max = (1 << int_var.size()) - 1
@@ -494,26 +489,22 @@ class ChallRespInfo(angr.state_plugins.SimStatePlugin):
             for _, int_var in chall_resp_plugin.str_to_int_pairs:
                 vars_to_solve.append(int_var)
 
-            if require_same_length:
-                extra_constraints = chall_resp_plugin.get_same_length_constraints()
-            else:
-                extra_constraints = []
+            extra_constraints = chall_resp_plugin.get_same_length_constraints() if require_same_length else []
 
             solns = state.solver._solver.batch_eval(vars_to_solve, 1, extra_constraints=extra_constraints)
             if len(solns) == 0:
                 if require_same_length:
                     l.warning("could not satisfy with same length, falling back to different lengths")
                     return ChallRespInfo.atoi_dumps(state, require_same_length=False)
-                else:
-                    return state.posix.dumps(0)
+                return state.posix.dumps(0)
             solns = solns[0]
 
             # now make the real stdin
-            stdin = state.solver.eval(state.solver.BVV(solns[0], pos * 8), cast_to=bytes)
+            stdin = state.solver.eval(claripy.BVV(solns[0], pos * 8), cast_to=bytes)
 
             stdin_replacements = []
             for soln, (_, int_var) in zip(solns[1:], chall_resp_plugin.str_to_int_pairs):
-                int_var_name = list(int_var.variables)[0]
+                int_var_name = next(iter(int_var.variables))
                 indices = chall_resp_plugin.get_stdin_indices(int_var_name)
                 if len(indices) == 0:
                     continue
@@ -530,9 +521,8 @@ class ChallRespInfo(angr.state_plugins.SimStatePlugin):
 
             # filter for same start with value 0
             for i in list(stdin_replacements):
-                if any(ii[0] == i[0] and ii[2] != i[2] for ii in stdin_replacements):
-                    if int(i[2]) == 0:
-                        stdin_replacements.remove(i)
+                if any(ii[0] == i[0] and ii[2] != i[2] for ii in stdin_replacements) and int(i[2]) == 0:
+                    stdin_replacements.remove(i)
 
             # now do the replacing
             offset = 0
@@ -573,7 +563,7 @@ def zen_hook(state, expr):
     if state.has_plugin("chall_resp_info") and state.get_plugin("chall_resp_info").pending_info is not None:
         return None
 
-    if expr.op not in claripy.operations.leaf_operations and expr.op != "Concat":
+    if expr.is_leaf() and expr.op != "Concat":
         # if there is more than one symbolic argument we replace it and preconstrain it
         flag_args = ZenPlugin.get_flag_rand_args(expr)
         if len(flag_args) > 1:
@@ -597,17 +587,17 @@ def zen_hook(state, expr):
                     con = replacement == expr
                     state.add_constraints(con)
                     contained_bytes = zen_plugin.get_flag_bytes(expr)
-                    zen_plugin.byte_dict[list(replacement.variables)[0]] = contained_bytes
+                    zen_plugin.byte_dict[next(iter(replacement.variables))] = contained_bytes
                     zen_plugin.zen_constraints.append(con)
                     # saves a ton of memory to do this here rather than later
                     zen_plugin.zen_constraints.append(state.solver.simplify(con))
                 else:
                     # otherwise don't add the constraint, just replace
                     depth = 0
-                    zen_plugin.byte_dict[list(replacement.variables)[0]] = set()
+                    zen_plugin.byte_dict[next(iter(replacement.variables))] = set()
 
                 # save and replace
-                var = list(replacement.variables)[0]
+                var = next(iter(replacement.variables))
                 zen_plugin.depths[var] = depth
                 constraint = replacement == concrete_val
                 zen_plugin.state.preconstrainer.preconstraints.append(constraint)
@@ -667,18 +657,17 @@ class ZenPlugin(angr.state_plugins.SimStatePlugin):
         symbolic_args = tuple(a for a in expr.args if isinstance(a, claripy.ast.Base) and a.symbolic)
         flag_args = []
         for a in symbolic_args:
-            if any(v.startswith("cgc-flag") or v.startswith("random") for v in a.variables):
+            if any(v.startswith(("cgc-flag", "random")) for v in a.variables):
                 flag_args.append(a)
         return flag_args
 
     def get_expr_depth(self, expr):
         flag_args = self.get_flag_rand_args(expr)
         flag_arg_vars = set.union(*[set(v.variables) for v in flag_args])
-        flag_arg_vars = {v for v in flag_arg_vars if v.startswith("cgc-flag") or v.startswith("random")}
+        flag_arg_vars = {v for v in flag_arg_vars if v.startswith(("cgc-flag", "random"))}
         if len(flag_arg_vars) == 0:
             return 0
-        depth = max(self.depths.get(v, 0) for v in flag_arg_vars) + 1
-        return depth
+        return max(self.depths.get(v, 0) for v in flag_arg_vars) + 1
 
     @angr.state_plugins.SimStatePlugin.memo
     def copy(self, memo):  # pylint: disable=unused-argument
@@ -717,7 +706,7 @@ class ZenPlugin(angr.state_plugins.SimStatePlugin):
         for con in constraints:
             if (
                 con.cache_key in zen_cache_keys
-                or not all(v.startswith("cgc-flag") or v.startswith("random") for v in con.variables)
+                or not all(v.startswith(("cgc-flag", "random")) for v in con.variables)
                 or len(con.variables) == 0
             ):
                 new_cons.append(con)
@@ -728,16 +717,13 @@ class ZenPlugin(angr.state_plugins.SimStatePlugin):
         try:
             state.memory.permissions(state.solver.eval(buf))
         except angr.SimMemoryError:
-            l.warning("detected possible arbitary transmit to fd %d", fd)
+            l.warning("detected possible arbitrary transmit to fd %d", fd)
             if fd == 0 or fd == 1:
                 self.controlled_transmits.append((state.copy(), buf))
 
     @staticmethod
     def prep_tracer(state):
-        if state.has_plugin("zen_plugin"):
-            zen_plugin = state.get_plugin("zen_plugin")
-        else:
-            zen_plugin = ZenPlugin()
+        zen_plugin = state.get_plugin("zen_plugin") if state.has_plugin("zen_plugin") else ZenPlugin()
 
         state.register_plugin("zen_plugin", zen_plugin)
         state.inspect.b("reg_write", angr.BP_BEFORE, action=zen_register_write)
@@ -746,7 +732,7 @@ class ZenPlugin(angr.state_plugins.SimStatePlugin):
         # setup the byte dict
         byte_dict = zen_plugin.byte_dict
         for i, b in enumerate(state.cgc.flag_bytes):
-            var = list(b.variables)[0]
+            var = next(iter(b.variables))
             byte_dict[var] = {i}
 
         state.preconstrainer.preconstraints.extend(zen_plugin.preconstraints)

angr/state_plugins/uc_manager.py

@@ -1,12 +1,17 @@
+from __future__ import annotations
 import logging
 
-l = logging.getLogger(name=__name__)
+import claripy
 
 from .plugin import SimStatePlugin
 from ..errors import SimUCManagerAllocationError
 
+l = logging.getLogger(name=__name__)
+
 
 class SimUCManager(SimStatePlugin):
+    _uc_alloc_depth: dict[claripy.ast.Base, int]
+
     def __init__(self, man=None):
         SimStatePlugin.__init__(self)
 
@@ -30,6 +35,8 @@ class SimUCManager(SimStatePlugin):
         # The maximum allocation depth
         self._max_alloc_depth = 20
 
+        self._uc_alloc_depth = {}
+
     def assign(self, dst_addr_ast):
         """
         Assign a new region for under-constrained symbolic execution.
@@ -38,17 +45,17 @@ class SimUCManager(SimStatePlugin):
         :return: as ast of memory address that points to a new region
         """
 
-        if dst_addr_ast.uc_alloc_depth > self._max_alloc_depth:
+        dst_uc_alloc_depth = self._uc_alloc_depth[dst_addr_ast]
+        if dst_uc_alloc_depth > self._max_alloc_depth:
             raise SimUCManagerAllocationError(
-                "Current allocation depth %d is greater than the cap (%d)"
-                % (dst_addr_ast.uc_alloc_depth, self._max_alloc_depth)
+                "Current allocation depth %d is greater than the cap (%d)" % (dst_uc_alloc_depth, self._max_alloc_depth)
             )
 
         abs_addr = self._region_base + self._pos
-        ptr = self.state.solver.BVV(abs_addr, self.state.arch.bits)
+        ptr = claripy.BVV(abs_addr, self.state.arch.bits)
         self._pos += self._region_size
 
-        self._alloc_depth_map[(abs_addr - self._region_base) // self._region_size] = dst_addr_ast.uc_alloc_depth
+        self._alloc_depth_map[(abs_addr - self._region_base) // self._region_size] = dst_uc_alloc_depth
 
         l.debug("Assigned new memory region %s", ptr)
         return ptr
@@ -57,13 +64,15 @@ class SimUCManager(SimStatePlugin):
     def copy(self, memo):  # pylint: disable=unused-argument
         return SimUCManager(man=self)
 
-    def get_alloc_depth(self, addr):
-        block_pos = (addr - self._region_base) // self._region_size
+    def get_alloc_depth(self, addr: int | claripy.ast.Base) -> int | None:
+        if isinstance(addr, claripy.ast.Base):
+            return self._uc_alloc_depth.get(addr, None)
 
-        if block_pos not in self._alloc_depth_map:
-            return None
+        block_pos = (addr - self._region_base) // self._region_size
+        return self._alloc_depth_map.get(block_pos, None)
 
-        return self._alloc_depth_map[block_pos]
+    def set_alloc_depth(self, addr: claripy.ast.Base, depth: int):
+        self._uc_alloc_depth[addr] = depth
 
     def is_bounded(self, ast):
         """

angr/state_plugins/unicorn_engine.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import binascii
 import copy
 import ctypes
@@ -302,10 +303,7 @@ class Uniwrapper(unicorn.Uc if unicorn is not None else object):
         self.wrapped_mapped = set()
         self.wrapped_hooks = set()
         self.id = None
-        if thumb:
-            uc_mode = arch.uc_mode_thumb
-        else:
-            uc_mode = arch.uc_mode
+        uc_mode = arch.uc_mode_thumb if thumb else arch.uc_mode
         unicorn.Uc.__init__(self, arch.uc_arch, uc_mode)
 
     def hook_add(self, htype, callback, user_data=None, begin=1, end=0, arg1=0):
@@ -839,7 +837,7 @@ class Unicorn(SimStatePlugin):
 
     def _setup_unicorn(self):
         if self.state.arch.uc_mode is None:
-            raise SimUnicornUnsupport("unsupported architecture %r" % self.state.arch)
+            raise SimUnicornUnsupport(f"unsupported architecture {self.state.arch!r}")
 
     def set_last_block_details(self, details):
         _UC_NATIVE.set_last_block_details(self._uc_state, details["addr"], details["curr_count"], details["tot_count"])
@@ -868,9 +866,7 @@ class Unicorn(SimStatePlugin):
             )
         elif arch == "i386":
             self.uc.hook_add(unicorn.UC_HOOK_INTR, self._hook_intr_x86, None, 1, 0)
-        elif arch == "mips":
-            self.uc.hook_add(unicorn.UC_HOOK_INTR, self._hook_intr_mips, None, 1, 0)
-        elif arch == "mipsel":
+        elif arch == "mips" or arch == "mipsel":
             self.uc.hook_add(unicorn.UC_HOOK_INTR, self._hook_intr_mips, None, 1, 0)
         elif arch == "arm":
             # EDG says: Unicorn's ARM support has no concept of interrupts.
@@ -935,8 +931,7 @@ class Unicorn(SimStatePlugin):
         if sysno in self.syscall_hooks:
             self.syscall_hooks[sysno](self.state)
             return True
-        else:
-            return False
+        return False
 
     def _handle_syscall(self, uc, user_data):  # pylint:disable=unused-argument
         # unicorn does not support syscall, we should giveup emulation
@@ -956,16 +951,13 @@ class Unicorn(SimStatePlugin):
     def _symbolic_passthrough(self, d):
         if not d.symbolic:
             return d
-        elif options.UNICORN_AGGRESSIVE_CONCRETIZATION in self.state.options:
+        if options.UNICORN_AGGRESSIVE_CONCRETIZATION in self.state.options:
             return self._concretize(d)
-        elif len(d.variables & self.never_concretize) > 0:
+        if len(d.variables & self.never_concretize) > 0:
             return d
-        elif d.variables.issubset(self.always_concretize):
-            return self._concretize(d)
-        elif self.state.solver.eval(self.state.ip) in self.concretize_at:
+        if d.variables.issubset(self.always_concretize) or self.state.solver.eval(self.state.ip) in self.concretize_at:
             return self._concretize(d)
-        else:
-            return d
+        return d
 
     def _report_symbolic_blocker(self, d, from_where):
         if options.UNICORN_THRESHOLD_CONCRETIZATION in self.state.options:
@@ -1001,10 +993,9 @@ class Unicorn(SimStatePlugin):
         if len(d.annotations):
             l.debug("Blocking annotated AST.")
             return None
-        elif not d.symbolic:
+        if not d.symbolic:
             return d
-        else:
-            l.debug("Processing AST with variables %s.", d.variables)
+        l.debug("Processing AST with variables %s.", d.variables)
 
         dd = self._symbolic_passthrough(d)
 
@@ -1012,12 +1003,11 @@ class Unicorn(SimStatePlugin):
             if d.symbolic:
                 l.debug("... concretized")
             return dd
-        elif from_where == "reg" and options.UNICORN_SYM_REGS_SUPPORT in self.state.options:
+        if from_where == "reg" and options.UNICORN_SYM_REGS_SUPPORT in self.state.options:
             l.debug("... allowing symbolic register")
             return dd
-        else:
-            l.debug("... denied")
-            return None
+        l.debug("... denied")
+        return None
 
     def _hook_mem_unmapped(self, uc, access, address, size, value, user_data):  # pylint:disable=unused-argument
         """
@@ -1033,7 +1023,7 @@ class Unicorn(SimStatePlugin):
                 if pageno >= needed_pages:
                     break
                 if options.UNICORN_ZEROPAGE_GUARD in self.state.options:
-                    self.error = "accessing zero page (%#x)" % access
+                    self.error = f"accessing zero page ({access:#x})"
                     l.warning(self.error)
 
                     _UC_NATIVE.stop(self._uc_state, STOP.STOP_ZEROPAGE)
@@ -1287,9 +1277,9 @@ class Unicorn(SimStatePlugin):
 
         # Initialize list of artificial VEX registers
         artificial_regs_list = (ctypes.c_uint64(offset) for offset in self.state.arch.artificial_registers_offsets)
-        artifical_regs_count = len(self.state.arch.artificial_registers_offsets)
-        artificial_regs_array = (ctypes.c_uint64 * artifical_regs_count)(*artificial_regs_list)
-        _UC_NATIVE.set_artificial_registers(self._uc_state, artificial_regs_array, artifical_regs_count)
+        artificial_regs_count = len(self.state.arch.artificial_registers_offsets)
+        artificial_regs_array = (ctypes.c_uint64 * artificial_regs_count)(*artificial_regs_list)
+        _UC_NATIVE.set_artificial_registers(self._uc_state, artificial_regs_array, artificial_regs_count)
 
         # Initialize VEX register offset to unicorn register ID mappings and VEX register offset to name map
         vex_reg_offsets = []
@@ -1639,10 +1629,7 @@ class Unicorn(SimStatePlugin):
                         mantissa = 0
                     elif exponent == 0x7FF:  # nan or infinity
                         exponent = 0x7FFF
-                        if mantissa != 0:
-                            mantissa = 0x8000000000000000
-                        else:
-                            mantissa = 0xFFFFFFFFFFFFFFFF
+                        mantissa = 9223372036854775808 if mantissa != 0 else 18446744073709551615
 
                     if sign:
                         exponent |= 0x8000
@@ -1742,10 +1729,7 @@ class Unicorn(SimStatePlugin):
         handling symbolic exits in native interface
         """
 
-        if succ_state:
-            state = succ_state
-        else:
-            state = self.state
+        state = succ_state if succ_state else self.state
 
         # first, get the ignore list (in case of symbolic registers)
         saved_registers = []
@@ -1791,7 +1775,7 @@ class Unicorn(SimStatePlugin):
         # some architecture-specific register fixups
         if state.arch.name in {"X86", "AMD64"}:
             # update the eflags
-            state.regs.eflags = state.solver.BVV(self.uc.reg_read(self._uc_const.UC_X86_REG_EFLAGS), state.arch.bits)
+            state.regs.eflags = claripy.BVV(self.uc.reg_read(self._uc_const.UC_X86_REG_EFLAGS), state.arch.bits)
 
             # sync the fp clerical data
             status = self.uc.reg_read(unicorn.x86_const.UC_X86_REG_FPSW)
@@ -1857,7 +1841,7 @@ class Unicorn(SimStatePlugin):
 
     def _check_registers(self, report=True):
         """check if this state might be used in unicorn (has no concrete register)"""
-        for r in self.state.arch.uc_regs.keys():
+        for r in self.state.arch.uc_regs:
             v = getattr(self.state.regs, r)
             processed_v = self._process_value(v, "reg")
             if processed_v is None or processed_v.symbolic:

angr/state_plugins/view.py

@@ -1,5 +1,7 @@
-from typing import TYPE_CHECKING
+from __future__ import annotations
+
 import logging
+from typing import ClassVar, TYPE_CHECKING
 
 import claripy
 from archinfo.arch_soot import ArchSoot, SootAddressDescriptor
@@ -77,12 +79,12 @@ class SimRegNameView(SimStatePlugin):
 
         try:
             return self.state.registers.store(k, v, inspect=inspect, disable_actions=disable_actions)
-        except KeyError:
+        except KeyError as err:
             # What do we do in case we are dealing with soot? there are no register
             if isinstance(self.state.arch, ArchSoot):
                 pass
             else:
-                raise AttributeError(k)
+                raise AttributeError(k) from err
 
     def __dir__(self):
         if self.state.arch.name in ("X86", "AMD64"):
@@ -92,8 +94,8 @@ class SimRegNameView(SimStatePlugin):
                 + ["tag%d" % n for n in range(8)]
                 + ["flags", "eflags", "rflags"]
             )
-        elif is_arm_arch(self.state.arch):
-            return list(self.state.arch.registers.keys()) + ["flags"]
+        if is_arm_arch(self.state.arch):
+            return [*list(self.state.arch.registers.keys()), "flags"]
         return self.state.arch.registers.keys()
 
     @SimStatePlugin.memo
@@ -119,7 +121,7 @@ class SimMemView(SimStatePlugin):
         - You first use [array index notation] to specify the address you'd like to load from
         - If at that address is a pointer, you may access the ``deref`` property to return a SimMemView at the
           address present in memory.
-        - You then specify a type for the data by simply accesing a property of that name. For a list of supported
+        - You then specify a type for the data by simply accessing a property of that name. For a list of supported
           types, look at ``state.mem.types``.
         - You can then *refine* the type. Any type may support any refinement it likes. Right now the only refinements
           supported are that you may access any member of a struct by its member name, and you may index into a
@@ -157,9 +159,9 @@ class SimMemView(SimStatePlugin):
 
         # Make sure self._addr is always an AST
         if isinstance(self._addr, int):
-            self._addr = self.state.solver.BVV(self._addr, self.state.arch.bits)
+            self._addr = claripy.BVV(self._addr, self.state.arch.bits)
 
-    def _deeper(self, **kwargs) -> "SimMemView":
+    def _deeper(self, **kwargs) -> SimMemView:
         if "ty" not in kwargs:
             kwargs["ty"] = self._type
         if "addr" not in kwargs:
@@ -168,16 +170,15 @@ class SimMemView(SimStatePlugin):
             kwargs["state"] = self.state
         return SimMemView(**kwargs)
 
-    def __getitem__(self, k) -> "SimMemView":
+    def __getitem__(self, k) -> SimMemView:
         if isinstance(k, slice):
             if k.step is not None:
                 raise ValueError("Slices with strides are not supported")
-            elif k.start is None:
+            if k.start is None:
                 raise ValueError("Must specify start index")
-            elif k.stop is not None:
+            if k.stop is not None:
                 raise ValueError("Slices with stop index are not supported")
-            else:
-                addr = k.start
+            addr = k.start
         elif self._type is not None and self._type._can_refine_int:
             return self._type._refine(self, k)
         else:
@@ -187,7 +188,7 @@ class SimMemView(SimStatePlugin):
     def __setitem__(self, k, v):
         self.__getitem__(k).store(v)
 
-    types = {}
+    types: ClassVar[dict] = {}
     state = None
 
     def __repr__(self):
@@ -208,7 +209,7 @@ class SimMemView(SimStatePlugin):
     def __dir__(self):
         return self._type._refine_dir() if self._type else [x for x in SimMemView.types if " " not in x] + ["struct"]
 
-    struct: "StructMode"
+    struct: StructMode
 
     def __getattr__(self, k):
         if k in (
@@ -239,7 +240,7 @@ class SimMemView(SimStatePlugin):
     def __cmp__(self, other):
         raise ValueError("Trying to compare SimMemView is not what you want to do")
 
-    def with_type(self, sim_type: "SimType") -> "SimMemView":
+    def with_type(self, sim_type: SimType) -> SimMemView:
         """
         Returns a copy of the SimMemView with a type.
 
@@ -276,7 +277,7 @@ class SimMemView(SimStatePlugin):
         return self._type.extract(self.state, self._addr, True)
 
     @property
-    def deref(self) -> "SimMemView":
+    def deref(self) -> SimMemView:
         if self._addr is None:
             raise ValueError("Trying to dereference pointer without addr defined")
         ptr = self.state.memory.load(self._addr, self.state.arch.bytes, endness=self.state.arch.memory_endness)
@@ -286,14 +287,14 @@ class SimMemView(SimStatePlugin):
 
         return self._deeper(ty=self._type.pts_to if isinstance(self._type, SimTypePointer) else None, addr=ptr)
 
-    def array(self, n) -> "SimMemView":
+    def array(self, n) -> SimMemView:
         if self._addr is None:
-            raise ValueError("Trying to produce array without specifying adddress")
+            raise ValueError("Trying to produce array without specifying address")
         if self._type is None:
             raise ValueError("Trying to produce array without specifying type")
         return self._deeper(ty=SimTypeFixedSizeArray(self._type, n))
 
-    def member(self, member_name: str) -> "SimMemView":
+    def member(self, member_name: str) -> SimMemView:
         """
         If self is a struct and member_name is a member of the struct, return
         that member element. Otherwise raise an exception.

angr/storage/__init__.py

@@ -1,4 +1,5 @@
 # misc
+from __future__ import annotations
 
 DUMMY_SYMBOLIC_READ_VALUE = 0xC0DEB4BE