angr 9.2.116__py3-none-win_amd64.whl → 9.2.118__py3-none-win_amd64.whl

angr/state_plugins/libc.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 from .plugin import SimStatePlugin
 
 
@@ -1249,13 +1250,12 @@ class SimStateLibc(SimStatePlugin):
         try:
             ival = getattr(self.state.posix, val)
         except AttributeError as e:
-            raise ValueError("Invalid errno constant %s" % val) from e
+            raise ValueError(f"Invalid errno constant {val}") from e
 
         if self.state.scratch.sim_procedure.is_syscall:
             return -ival
-        else:
-            self.errno = ival
-            return -1
+        self.errno = ival
+        return -1
 
 
 from angr.sim_state import SimState

angr/state_plugins/light_registers.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import claripy
 import logging
 
@@ -18,8 +19,7 @@ class SimLightRegisters(SimStatePlugin):
 
     @SimStatePlugin.memo
     def copy(self, _memo):
-        o = type(self)(reg_map=self.reg_map, registers=dict(self.registers))
-        return o
+        return type(self)(reg_map=self.reg_map, registers=dict(self.registers))
 
     def set_state(self, state):
         super().set_state(state)
@@ -34,7 +34,7 @@ class SimLightRegisters(SimStatePlugin):
         bw = state.arch.byte_width
         for reg in state.arch.register_list:
             self.reg_map[(reg.vex_offset, reg.size)] = reg.name, None, reg.size * bw
-            for subreg_name, subreg_suboffset, subreg_size in reg.subregisters:
+            for _subreg_name, subreg_suboffset, subreg_size in reg.subregisters:
                 # endian swap gets undone here
                 if state.arch.register_endness == "Iend_BE":
                     extract_high = (reg.size - 1 - subreg_suboffset) * bw + 7
@@ -56,8 +56,7 @@ class SimLightRegisters(SimStatePlugin):
                 try:
                     if size.symbolic:
                         raise SimFastMemoryError("Can't handle symbolic register access")
-                    else:
-                        size = offset.args[0]
+                    size = offset.args[0]
                 except AttributeError:
                     raise TypeError("Invalid size argument") from None
 
@@ -65,8 +64,7 @@ class SimLightRegisters(SimStatePlugin):
                 try:
                     if offset.symbolic:
                         raise SimFastMemoryError("Can't handle symbolic register access")
-                    else:
-                        offset = offset.args[0]
+                    offset = offset.args[0]
                 except AttributeError:
                     raise TypeError("Invalid offset argument") from None
 
@@ -118,7 +116,7 @@ class SimLightRegisters(SimStatePlugin):
                 raise SimFastMemoryError("Invalid register store value") from None
 
         if type(value) is int:
-            value = self.state.solver.BVV(value, xsize)
+            value = claripy.BVV(value, xsize)
 
         if endness is not None and endness != self.state.arch.register_endness:
             # ???????
@@ -142,7 +140,7 @@ class SimLightRegisters(SimStatePlugin):
     def _fill(self, name, size):
         size_bits = size * self.state.arch.byte_width
         if options.ZERO_FILL_UNCONSTRAINED_REGISTERS in self.state.options:
-            value = self.state.solver.BVV(0, size_bits)
+            value = claripy.BVV(0, size_bits)
         else:
             if options.SYMBOL_FILL_UNCONSTRAINED_REGISTERS not in self.state.options:
                 if once("mem_fill_warning"):
@@ -164,7 +162,7 @@ class SimLightRegisters(SimStatePlugin):
                         "to suppress these messages."
                     )
                 l.warning("Filling register %s with %d unconstrained bytes", name, size)
-            return self.state.solver.Unconstrained("reg_%s" % name, size_bits, key=("reg", name), eternal=True)  # :)
+            return self.state.solver.Unconstrained(f"reg_{name}", size_bits, key=("reg", name), eternal=True)  # :)
 
         self.registers[name] = value
         return value

angr/state_plugins/log.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import logging
 
 l = logging.getLogger(name=__name__)

angr/state_plugins/loop_data.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import logging
 import copy
 from collections import defaultdict

angr/state_plugins/plugin.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 from typing import cast
 
 import angr  # For type annotations; pylint: disable=unused-import
@@ -43,7 +44,7 @@ class SimStatePlugin:
         ``SimStatePlugin.memo``
 
         The base implementation of this function constructs a new instance of the plugin's class without calling its
-        initializer. If you super-call down to it, make sure you instanciate all the fields in your copy method!
+        initializer. If you super-call down to it, make sure you instantiate all the fields in your copy method!
 
         :param memo:    A dictionary mapping object identifiers (id(obj)) to their copied instance.  Use this to avoid
                         infinite recursion and diverged copies.
@@ -63,10 +64,9 @@ class SimStatePlugin:
                 memo = {}
             if id(self) in memo:
                 return memo[id(self)]
-            else:
-                c = f(self, memo, **kwargs)
-                memo[id(self)] = c
-                return c
+            c = f(self, memo, **kwargs)
+            memo[id(self)] = c
+            return c
 
         return inner
 
@@ -98,8 +98,8 @@ class SimStatePlugin:
         ``state.solver.union(values)``.
         TODO: fish please make this less bullshit
 
-        There is a utility ``state.solver.ite_cases`` which will help with constructing arbitrarily large merged ASTs.
-        Use it like ``self.bar = self.state.solver.ite_cases(zip(conditions[1:], [o.bar for o in others]), self.bar)``
+        There is a utility ``claripy.ite_cases`` which will help with constructing arbitrarily large merged ASTs.
+        Use it like ``self.bar = claripy.ite_cases(zip(conditions[1:], [o.bar for o in others]), self.bar)``
 
         :param others: the other state plugins to merge with
         :param merge_conditions: a symbolic condition for each of the plugins
@@ -107,7 +107,7 @@ class SimStatePlugin:
         :returns: True if the state plugins are actually merged.
         :rtype: bool
         """
-        raise NotImplementedError("merge() not implement for %s" % self.__class__.__name__)
+        raise NotImplementedError(f"merge() not implement for {self.__class__.__name__}")
 
     def widen(self, others):  # pylint:disable=unused-argument
         """
@@ -120,7 +120,7 @@ class SimStatePlugin:
         :returns: True if the state plugin is actually widened.
         :rtype: bool
         """
-        raise NotImplementedError("widen() not implemented for %s" % self.__class__.__name__)
+        raise NotImplementedError(f"widen() not implemented for {self.__class__.__name__}")
 
     @classmethod
     def register_default(cls, name, xtr=None):
@@ -152,4 +152,3 @@ class SimStatePlugin:
         """
         Use this function to perform any initialization on the state at plugin-add time
         """
-        pass

angr/state_plugins/posix.py

@@ -1,5 +1,8 @@
+from __future__ import annotations
 import logging
 
+import claripy
+
 from .plugin import SimStatePlugin
 from .filesystem import SimMount, Stat
 from ..storage.file import SimFile, SimPacketsStream, Flags, SimFileDescriptor, SimFileDescriptorDuplex
@@ -14,12 +17,11 @@ class PosixDevFS(SimMount):  # this'll be mounted at /dev
     def get(self, path):  # pylint: disable=arguments-differ
         if path == ["stdin"]:
             return self.state.posix.fd.get(0, None)
-        elif path == ["stdout"]:
+        if path == ["stdout"]:
             return self.state.posix.fd.get(1, None)
-        elif path == ["stderr"]:
+        if path == ["stderr"]:
             return self.state.posix.fd.get(2, None)
-        else:
-            return None
+        return None
 
     def insert(self, path, simfile):  # pylint: disable=unused-argument, arguments-differ
         return False
@@ -48,8 +50,7 @@ class PosixProcFS(SimMount):
     def get(self, path):  # pylint: disable=arguments-differ
         if path == [b"uptime"]:
             return SimFile(b"uptime", content=b"0 0")
-        else:
-            return None
+        return None
 
     def insert(self, path, simfile):  # pylint: disable=unused-argument, arguments-differ
         return False
@@ -239,11 +240,11 @@ class SimSystemPosix(SimStatePlugin):
     def set_brk(self, new_brk):
         # arch word size is not available at init for some reason, fix that here
         if isinstance(self.brk, int):
-            self.brk = self.state.solver.BVV(self.brk, self.state.arch.bits)
+            self.brk = claripy.BVV(self.brk, self.state.arch.bits)
 
         if new_brk.symbolic:
             l.warning("Program is requesting a symbolic brk! This cannot be emulated cleanly!")
-            self.brk = self.state.solver.If(new_brk < self.brk, self.brk, new_brk)
+            self.brk = claripy.If(new_brk < self.brk, self.brk, new_brk)
 
         else:
             conc_start = self.state.solver.eval(self.brk)
@@ -299,7 +300,7 @@ class SimSystemPosix(SimStatePlugin):
                 sock_pair[1].set_state(state)
 
     def _pick_fd(self):
-        for fd in range(0, max_fds):
+        for fd in range(max_fds):
             if fd not in self.fd:
                 return fd
         raise SimPosixError("exhausted file descriptors")
@@ -328,10 +329,7 @@ class SimSystemPosix(SimStatePlugin):
             return -1
 
         # TODO: speed this up (editor's note: ...really? this is fine)
-        if preferred_fd is not None and preferred_fd not in self.fd:
-            fd = preferred_fd
-        else:
-            fd = self._pick_fd()
+        fd = preferred_fd if preferred_fd is not None and preferred_fd not in self.fd else self._pick_fd()
 
         flags = self.state.solver.eval(flags)
         create_file = (flags & Flags.O_ACCMODE) in (Flags.O_RDWR, Flags.O_WRONLY)
@@ -342,7 +340,7 @@ class SimSystemPosix(SimStatePlugin):
             if not create_file:
                 if options.ALL_FILES_EXIST not in self.state.options:
                     if options.ANY_FILE_MIGHT_EXIST in self.state.options:
-                        file_exists = self.state.solver.BoolS("file_exists_%s" % ident, explicit_name=True)
+                        file_exists = claripy.BoolS(f"file_exists_{ident}", explicit_name=True)
                     else:
                         return -1
                 else:
@@ -354,7 +352,7 @@ class SimSystemPosix(SimStatePlugin):
                     name,
                     ident=ident,
                     size=self.state.solver.BVS(
-                        "filesize_%s" % ident, self.state.arch.bits, key=("file", ident, "filesize"), eternal=True
+                        f"filesize_{ident}", self.state.arch.bits, key=("file", ident, "filesize"), eternal=True
                     ),
                     file_exists=file_exists,
                 )
@@ -368,9 +366,8 @@ class SimSystemPosix(SimStatePlugin):
         self.fd[fd] = simfd
         if self.state.solver.is_true(simfd.file_exists):
             return fd
-        else:
-            m1 = self.state.solver.BVV(-1, self.state.arch.sizeof["int"])
-            return self.state.solver.If(simfd.file_exists, fd, m1)
+        m1 = claripy.BVV(-1, self.state.arch.sizeof["int"])
+        return claripy.If(simfd.file_exists, fd, m1)
 
     def open_socket(self, ident):
         fd = self._pick_fd()
@@ -396,8 +393,8 @@ class SimSystemPosix(SimStatePlugin):
                     sockpair = sockpair[0].copy(memo), sockpair[1].copy(memo)
 
             if sockpair is None:
-                read_file = SimPacketsStream("socket %s read" % str(ident))
-                write_file = SimPacketsStream("socket %s write" % str(ident))
+                read_file = SimPacketsStream(f"socket {ident!s} read")
+                write_file = SimPacketsStream(f"socket {ident!s} write")
                 sockpair = (read_file, write_file)
 
             self.sockets[ident] = sockpair
@@ -442,10 +439,7 @@ class SimSystemPosix(SimStatePlugin):
 
         new_filename = b"/tmp/angr_implicit_%d" % self.autotmp_counter
         self.autotmp_counter += 1
-        if create_file:
-            flags = Flags.O_RDWR
-        else:
-            flags = Flags.O_RDONLY
+        flags = Flags.O_RDWR if create_file else Flags.O_RDONLY
         concr_fd = self._pick_fd()
         if not self.state.satisfiable(extra_constraints=(concr_fd == fd,)):
             l.error("Could not look up a partially constrained symbolic fd")
@@ -513,8 +507,8 @@ class SimSystemPosix(SimStatePlugin):
         else:
             if options.ALL_FILES_EXIST not in self.state.options:
                 if options.ANY_FILE_MIGHT_EXIST in self.state.options:
-                    m1 = self.state.solver.BVV(-1, self.state.arch.bits)
-                    result = self.state.solver.If(self.state.solver.BoolS("file_exists"), 0, m1)
+                    m1 = claripy.BVV(-1, self.state.arch.bits)
+                    result = claripy.If(claripy.BoolS("file_exists"), 0, m1)
                 else:
                     result = -1
             else:
@@ -536,7 +530,7 @@ class SimSystemPosix(SimStatePlugin):
                 mode = (
                     self.state.solver.BVS("st_mode", 32, key=("api", "fstat", "st_mode"))
                     if fd > 2
-                    else self.state.solver.BVV(0, 32)
+                    else claripy.BVV(0, 32)
                 )
             size = self.state.solver.BVS("st_size", 64, key=("api", "fstat", "st_size"))  # st_size
             ino = 0
@@ -544,22 +538,22 @@ class SimSystemPosix(SimStatePlugin):
         # return this weird bogus zero value to keep code paths in libc simple :\
         return (
             Stat(
-                self.state.solver.BVV(0, 64),  # st_dev
-                self.state.solver.BVV(ino, 64),  # st_ino
-                self.state.solver.BVV(0, 64),  # st_nlink
+                claripy.BVV(0, 64),  # st_dev
+                claripy.BVV(ino, 64),  # st_ino
+                claripy.BVV(0, 64),  # st_nlink
                 mode,  # st_mode
-                self.state.solver.BVV(0, 32),  # st_uid (lol root)
-                self.state.solver.BVV(0, 32),  # st_gid
-                self.state.solver.BVV(0, 64),  # st_rdev
+                claripy.BVV(0, 32),  # st_uid (lol root)
+                claripy.BVV(0, 32),  # st_gid
+                claripy.BVV(0, 64),  # st_rdev
                 size,  # st_size
-                self.state.solver.BVV(0x400, 64),  # st_blksize
-                self.state.solver.BVV(0, 64),  # st_blocks
-                self.state.solver.BVV(0, 64),  # st_atime
-                self.state.solver.BVV(0, 64),  # st_atimensec
-                self.state.solver.BVV(0, 64),  # st_mtime
-                self.state.solver.BVV(0, 64),  # st_mtimensec
-                self.state.solver.BVV(0, 64),  # st_ctime
-                self.state.solver.BVV(0, 64),  # st_ctimensec
+                claripy.BVV(0x400, 64),  # st_blksize
+                claripy.BVV(0, 64),  # st_blocks
+                claripy.BVV(0, 64),  # st_atime
+                claripy.BVV(0, 64),  # st_atimensec
+                claripy.BVV(0, 64),  # st_mtime
+                claripy.BVV(0, 64),  # st_mtimensec
+                claripy.BVV(0, 64),  # st_ctime
+                claripy.BVV(0, 64),  # st_ctimensec
             ),
             result,
         )
@@ -594,15 +588,15 @@ class SimSystemPosix(SimStatePlugin):
         :param valid_ptr: is set if the new_mask was not NULL
         """
         oldmask = self.sigmask(sigsetsize)
-        self._sigmask = self.state.solver.If(
+        self._sigmask = claripy.If(
             valid_ptr,
-            self.state.solver.If(
+            claripy.If(
                 how == self.SIG_BLOCK,
                 oldmask | new_mask,
-                self.state.solver.If(
+                claripy.If(
                     how == self.SIG_UNBLOCK,
                     oldmask & (~new_mask),
-                    self.state.solver.If(how == self.SIG_SETMASK, new_mask, oldmask),
+                    claripy.If(how == self.SIG_SETMASK, new_mask, oldmask),
                 ),
             ),
             oldmask,

angr/state_plugins/preconstrainer.py

@@ -1,4 +1,6 @@
+from __future__ import annotations
 import logging
+
 import claripy
 
 from .plugin import SimStatePlugin
@@ -52,11 +54,11 @@ class SimStatePreconstrainer(SimStatePlugin):
         :param variable:    The BVS to preconstrain.
         """
         if not isinstance(value, claripy.ast.Base):
-            value = self.state.solver.BVV(value, len(variable))
+            value = claripy.BVV(value, len(variable))
         elif value.op != "BVV":
             raise ValueError("Passed a value to preconstrain that was not a BVV or a string")
 
-        if variable.op not in claripy.operations.leaf_operations:
+        if not variable.is_leaf():
             l.warning(
                 "The variable %s to preconstrain is not a leaf AST. This may cause replacement failures in the "
                 "claripy replacement backend.",

angr/state_plugins/scratch.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import logging
 
 import claripy
@@ -75,7 +76,7 @@ class SimStateScratch(SimStatePlugin):
 
             self.statement_offset = scratch.statement_offset
 
-        # priveleges
+        # privileges
         self._priv_stack = [False]
 
     @property
@@ -109,13 +110,13 @@ class SimStateScratch(SimStatePlugin):
                 raise SimMissingTempError(
                     "VEX temp variable %d does not exist. This is usually the result of an incorrect slicing." % tmp
                 )
-        except IndexError:
-            raise SimMissingTempError("Accessing a temp that is illegal in this tyenv")
+        except IndexError as err:
+            raise SimMissingTempError("Accessing a temp that is illegal in this tyenv") from err
         self.state._inspect("tmp_read", BP_AFTER, tmp_read_expr=v)
         return v
 
     # pylint:disable=unused-argument
-    def store_tmp(self, tmp, content, reg_deps=None, tmp_deps=None, deps=None, **kwargs):
+    def store_tmp(self, tmp, content, reg_deps=frozenset(), tmp_deps=frozenset(), deps=None, **kwargs):
         """
         Stores a Claripy expression in a VEX temp value.
         If in symbolic mode, this involves adding a constraint for the tmp's symbolic variable.

angr/state_plugins/sim_action.py

@@ -1,4 +1,5 @@
 # This module contains data structures for handling memory, code, and register references.
+from __future__ import annotations
 
 import logging
 
@@ -7,6 +8,7 @@ l = logging.getLogger(name=__name__)
 _noneset = frozenset()
 
 from .sim_event import SimEvent
+import contextlib
 
 
 class SimAction(SimEvent):
@@ -34,40 +36,38 @@ class SimAction(SimEvent):
 
     def __repr__(self):
         if self.sim_procedure is not None:
-            location = "%s()" % self.sim_procedure.display_name
+            location = f"{self.sim_procedure.display_name}()"
         else:
             if self.stmt_idx is not None:
                 location = "0x%x:%d" % (self.ins_addr, self.stmt_idx)  # TODO: Revert this!
             else:
-                location = "0x%x" % self.bbl_addr
+                location = f"0x{self.bbl_addr:x}"
         return f"<{self.__class__.__name__} {location} {self._desc()}>"
 
     def _desc(self):
-        raise NotImplementedError()
+        raise NotImplementedError
 
     @staticmethod
     def _make_object(v):
         if v is None:
             return None
-        elif isinstance(v, SimActionObject):
+        if isinstance(v, SimActionObject):
             return v
-        else:
-            return SimActionObject(v, reg_deps=None, tmp_deps=None)
+        return SimActionObject(v)
 
     @staticmethod
     def _copy_object(v):
         if isinstance(v, SimActionObject):
             return v.copy()
-        else:
-            return None
+        return None
 
     @property
     def all_objects(self):
-        raise NotImplementedError()
+        raise NotImplementedError
 
     @property
     def is_symbolic(self):
-        raise NotImplementedError()
+        raise NotImplementedError
 
     @property
     def tmp_deps(self):
@@ -78,7 +78,7 @@ class SimAction(SimEvent):
         return frozenset.union(*[v.reg_deps for v in self.all_objects])
 
     def _copy_objects(self, c):
-        raise NotImplementedError()
+        raise NotImplementedError
 
     def copy(self):
         c = self._copy_event()
@@ -90,7 +90,6 @@ class SimAction(SimEvent):
         """
         Clears some low-level details (that take up memory) out of the SimAction.
         """
-        pass
 
 
 class SimActionExit(SimAction):
@@ -154,7 +153,7 @@ class SimActionConstraint(SimAction):
         c.condition = self._copy_object(self.condition)
 
     def _desc(self):
-        s = "%s" % str(self.constraint)
+        s = f"{self.constraint!s}"
         if self.condition is not None:
             s += " (cond)"
         return s
@@ -187,7 +186,7 @@ class SimActionOperation(SimAction):
         c.result = self.result
 
     def _desc(self):
-        return "operation/%s" % (self.op)
+        return f"operation/{self.op}"
 
 
 class SimActionData(SimAction):
@@ -278,10 +277,8 @@ class SimActionData(SimAction):
         def _repr(o):
             if type(o) in {bytes, str, int}:
                 return o
-            try:
+            with contextlib.suppress(AttributeError):
                 o = o.ast
-            except AttributeError:
-                pass
             if type(o) in {bytes, str, int}:
                 return o
             return o.shallow_repr()
@@ -301,10 +298,8 @@ class SimActionData(SimAction):
         def _repr(o):
             if type(o) in {bytes, str, int}:
                 return o
-            try:
+            with contextlib.suppress(AttributeError):
                 o = o.ast
-            except AttributeError:
-                pass
             if type(o) in {bytes, str, int}:
                 return o
             return o.shallow_repr()