angr 9.2.116__py3-none-manylinux2014_aarch64.whl → 9.2.118__py3-none-manylinux2014_aarch64.whl

angr/storage/memory_mixins/default_filler_mixin.py

@@ -1,5 +1,8 @@
+from __future__ import annotations
 import logging
 
+import claripy
+
 from . import MemoryMixin
 from ... import sim_options as options
 from ...misc.ux import once
@@ -15,7 +18,7 @@ class DefaultFillerMixin(MemoryMixin):
         if self.state.project and self.state.project.concrete_target:
             mem = self.state.project.concrete_target.read_memory(addr, size)
             endness = kwargs["endness"]
-            bvv = self.state.solver.BVV(mem)
+            bvv = claripy.BVV(mem)
             return bvv if endness == "Iend_BE" else bvv.reversed
 
         if fill_missing is False:
@@ -23,15 +26,18 @@ class DefaultFillerMixin(MemoryMixin):
 
         bits = size * self.state.arch.byte_width
 
-        if type(addr) is int:
-            if self.category == "mem" and options.ZERO_FILL_UNCONSTRAINED_MEMORY in self.state.options:
-                return self.state.solver.BVV(0, bits)
-            elif self.category == "reg" and options.ZERO_FILL_UNCONSTRAINED_REGISTERS in self.state.options:
-                return self.state.solver.BVV(0, bits)
+        if (
+            type(addr) is int
+            and self.category == "mem"
+            and options.ZERO_FILL_UNCONSTRAINED_MEMORY in self.state.options
+            or self.category == "reg"
+            and options.ZERO_FILL_UNCONSTRAINED_REGISTERS in self.state.options
+        ):
+            return claripy.BVV(0, bits)
 
         if self.category == "reg" and type(addr) is int and addr == self.state.arch.ip_offset:
             # short-circuit this pathological case
-            return self.state.solver.BVV(0, self.state.arch.bits)
+            return claripy.BVV(0, self.state.arch.bits)
 
         is_mem = (
             self.category == "mem"
@@ -99,14 +105,9 @@ class DefaultFillerMixin(MemoryMixin):
                     name = "reg_" + reg_str
 
         if name is None:
-            if type(addr) is int:
-                name = f"{self.id}_{addr:x}"
-            else:
-                name = self.category
-
-        r = self.state.solver.Unconstrained(name, bits, key=key, inspect=inspect, events=events)
+            name = f"{self.id}_{addr:x}" if type(addr) is int else self.category
 
-        return r
+        return self.state.solver.Unconstrained(name, bits, key=key, inspect=inspect, events=events)
 
 
 class SpecialFillerMixin(MemoryMixin):
@@ -137,8 +138,7 @@ class ExplicitFillerMixin(MemoryMixin):
     def _default_value(self, addr, size, inspect=True, events=True, **kwargs):
         if self._uninitialized_read_handler is not None:
             return self._uninitialized_read_handler(addr, size, inspect=inspect, events=events)
-        else:
-            return super()._default_value(addr, size, inspect=inspect, events=events, **kwargs)
+        return super()._default_value(addr, size, inspect=inspect, events=events, **kwargs)
 
     def copy(self, memo):
         o = super().copy(memo)

angr/storage/memory_mixins/dirty_addrs_mixin.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 from . import MemoryMixin
 
 

angr/storage/memory_mixins/hex_dumper_mixin.py

@@ -1,7 +1,9 @@
+from __future__ import annotations
 import string
 
 from ...errors import SimValueError
 from . import MemoryMixin
+import contextlib
 
 
 class HexDumperMixin(MemoryMixin):
@@ -40,10 +42,7 @@ class HexDumperMixin(MemoryMixin):
         :param disable_actions: whether or not to disable SimActions for the memory load
         :return: hex dump as a string
         """
-        if endianness == "Iend_BE":
-            end = 1
-        else:
-            end = -1
+        end = 1 if endianness == "Iend_BE" else -1
         if extra_constraints is None:
             extra_constraints = []
 
@@ -55,7 +54,7 @@ class HexDumperMixin(MemoryMixin):
         i = start
         dump_str = ""
         for line in raw_mem.chop(line_size * self.state.arch.byte_width):
-            dump = "%x:" % i
+            dump = f"{i:x}:"
             group_str = ""
             for word in line.chop(word_size * self.state.arch.byte_width):
                 word_bytes = ""
@@ -63,13 +62,11 @@ class HexDumperMixin(MemoryMixin):
                 for byte_ in word.chop(self.state.arch.byte_width)[::end]:
                     byte_value = None
                     if not self.state.solver.symbolic(byte_) or solve:
-                        try:
+                        with contextlib.suppress(SimValueError):
                             byte_value = self.state.solver.eval_one(byte_, extra_constraints=extra_constraints)
-                        except SimValueError:
-                            pass
 
                     if byte_value is not None:
-                        word_bytes += "%02x" % byte_value
+                        word_bytes += f"{byte_value:02x}"
                         if chr(byte_value) in string.printable[:-5]:
                             word_str += chr(byte_value)
                         else:

angr/storage/memory_mixins/javavm_memory/__init__.py

@@ -1 +1,2 @@
+from __future__ import annotations
 from .javavm_memory_mixin import JavaVmMemoryMixin

angr/storage/memory_mixins/javavm_memory/javavm_memory_mixin.py

@@ -1,6 +1,9 @@
-import os
+from __future__ import annotations
 import binascii
 import logging
+import os
+
+import claripy
 
 from .... import concretization_strategies
 from ....errors import SimUnsatError, SimMemoryAddressError
@@ -62,11 +65,7 @@ class JavaVmMemoryMixin(MemoryMixin):
         return binascii.hexlify(os.urandom(4))
 
     def store(self, addr, data, frame=0):  # pylint: disable=arguments-differ
-        if type(addr) is SimSootValue_Local:
-            cstack = self._stack[-1 + (-1 * frame)]
-            cstack.store(addr.id, data, type_=addr.type)
-
-        elif type(addr) is SimSootValue_ParamRef:
+        if type(addr) is SimSootValue_Local or type(addr) is SimSootValue_ParamRef:
             cstack = self._stack[-1 + (-1 * frame)]
             cstack.store(addr.id, data, type_=addr.type)
 
@@ -76,10 +75,7 @@ class JavaVmMemoryMixin(MemoryMixin):
         elif type(addr) is SimSootValue_StaticFieldRef:
             self.vm_static_table.store(addr.id, data, type_=addr.type)
 
-        elif type(addr) is SimSootValue_InstanceFieldRef:
-            self.heap.store(addr.id, data, type_=addr.type)
-
-        elif type(addr) is SimSootValue_StringRef:
+        elif type(addr) is SimSootValue_InstanceFieldRef or type(addr) is SimSootValue_StringRef:
             self.heap.store(addr.id, data, type_=addr.type)
 
         else:
@@ -90,14 +86,14 @@ class JavaVmMemoryMixin(MemoryMixin):
             cstack = self._stack[-1 + (-1 * frame)]
             return cstack.load(addr.id, none_if_missing=none_if_missing)
 
-        elif type(addr) is SimSootValue_ArrayRef:
+        if type(addr) is SimSootValue_ArrayRef:
             return self.load_array_element(addr.base, addr.index)
 
-        elif type(addr) is SimSootValue_ParamRef:
+        if type(addr) is SimSootValue_ParamRef:
             cstack = self._stack[-1 + (-1 * frame)]
             return cstack.load(addr.id, none_if_missing=none_if_missing)
 
-        elif type(addr) is SimSootValue_StaticFieldRef:
+        if type(addr) is SimSootValue_StaticFieldRef:
             value = self.vm_static_table.load(addr.id, none_if_missing=none_if_missing)
             if value is None:
                 # initialize field
@@ -106,7 +102,7 @@ class JavaVmMemoryMixin(MemoryMixin):
                 self.store(addr, value)
             return value
 
-        elif type(addr) is SimSootValue_InstanceFieldRef:
+        if type(addr) is SimSootValue_InstanceFieldRef:
             value = self.heap.load(addr.id, none_if_missing=none_if_missing)
             if value is None:
                 # initialize field
@@ -115,12 +111,11 @@ class JavaVmMemoryMixin(MemoryMixin):
                 self.store(addr, value)
             return value
 
-        elif type(addr) is SimSootValue_StringRef:
+        if type(addr) is SimSootValue_StringRef:
             return self.heap.load(addr.id, none_if_missing=none_if_missing)
 
-        else:
-            l.error("Unknown addr type %s", addr)
-            return None
+        l.error("Unknown addr type %s", addr)
+        return None
 
     def push_stack_frame(self):
         from .. import KeyValueMemory
@@ -174,7 +169,7 @@ class JavaVmMemoryMixin(MemoryMixin):
             start_idx_options = []
             for concrete_start_idx in concrete_start_idxes:
                 start_idx_options.append(concrete_start_idx == start_idx)
-                # we store elements condtioned with the start index:
+                # we store elements conditioned with the start index:
                 # => if concrete_start_idx == start_idx
                 #    then store the value
                 #    else keep the current value
@@ -188,7 +183,7 @@ class JavaVmMemoryMixin(MemoryMixin):
                     )
 
             # constraint start_idx, s.t. it evals to one of the concretized indexes
-            constraint_on_start_idx = self.state.solver.Or(*start_idx_options)
+            constraint_on_start_idx = claripy.Or(*start_idx_options)
             self.state.add_constraints(constraint_on_start_idx)
 
     def _store_array_element_on_heap(self, array, idx, value, value_type, store_condition=None):
@@ -197,7 +192,7 @@ class JavaVmMemoryMixin(MemoryMixin):
         if store_condition is not None:
             current_value = self._load_array_element_from_heap(array, idx)
             new_value = value
-            value = self.state.solver.If(store_condition, new_value, current_value)
+            value = claripy.If(store_condition, new_value, current_value)
         self.heap.store(heap_elem_id, value, value_type)
 
     #
@@ -256,11 +251,11 @@ class JavaVmMemoryMixin(MemoryMixin):
                     # => if concrete_start_idx == start_idx
                     #    then use new value
                     #    else use the current value
-                    load_values[i] = self.state.solver.If(concrete_start_idx == start_idx, value, load_values[i])
+                    load_values[i] = claripy.If(concrete_start_idx == start_idx, value, load_values[i])
                 start_idx_options.append(start_idx == concrete_start_idx)
 
             # constraint start_idx, s.t. it evals to one of the concretized indexes
-            constraint_on_start_idx = self.state.solver.Or(*start_idx_options)
+            constraint_on_start_idx = claripy.Or(*start_idx_options)
             self.state.add_constraints(constraint_on_start_idx)
 
         return load_values
@@ -297,7 +292,7 @@ class JavaVmMemoryMixin(MemoryMixin):
             if idxes:
                 return idxes
 
-        raise SimMemoryAddressError("Unable to concretize index %s" % idx)
+        raise SimMemoryAddressError(f"Unable to concretize index {idx}")
 
     def concretize_store_idx(self, idx, strategies=None):
         """
@@ -311,7 +306,7 @@ class JavaVmMemoryMixin(MemoryMixin):
         """
         if isinstance(idx, int):
             return [idx]
-        elif not self.state.solver.symbolic(idx):
+        if not self.state.solver.symbolic(idx):
             return [self.state.solver.eval(idx)]
 
         strategies = self.store_strategies if strategies is None else strategies
@@ -329,7 +324,7 @@ class JavaVmMemoryMixin(MemoryMixin):
         """
         if isinstance(idx, int):
             return [idx]
-        elif not self.state.solver.symbolic(idx):
+        if not self.state.solver.symbolic(idx):
             return [self.state.solver.eval(idx)]
 
         strategies = self.load_strategies if strategies is None else strategies
@@ -372,7 +367,7 @@ class JavaVmMemoryMixin(MemoryMixin):
 
     @MemoryMixin.memo
     def copy(self, memo):
-        o: "JavaVmMemoryMixin" = super().copy(memo)
+        o: JavaVmMemoryMixin = super().copy(memo)
         o._stack = [stack_frame.copy() for stack_frame in self._stack]
         o.heap = self.heap.copy()
         o.vm_static_table = self.vm_static_table.copy()
@@ -391,4 +386,4 @@ class JavaVmMemoryMixin(MemoryMixin):
         self, addr, what, max_search=None, max_symbolic_bytes=None, default=None
     ):  # pylint: disable=unused-argument
         l.warning("Find is not implemented for JavaVM memory!")
-        return None
+        return

angr/storage/memory_mixins/keyvalue_memory/__init__.py

@@ -1 +1,2 @@
+from __future__ import annotations
 from .keyvalue_memory_mixin import KeyValueMemoryMixin

angr/storage/memory_mixins/keyvalue_memory/keyvalue_memory_mixin.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 from .. import MemoryMixin
 
 
@@ -28,7 +29,7 @@ class KeyValueMemoryMixin(MemoryMixin):
 
     @MemoryMixin.memo
     def copy(self, memo):
-        o: "KeyValueMemoryMixin" = super().copy(memo)
+        o: KeyValueMemoryMixin = super().copy(memo)
         o._store = self._store.copy()
         return o
 

angr/storage/memory_mixins/label_merger_mixin.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 from collections.abc import Iterable
 
 from . import MemoryMixin
@@ -27,5 +28,4 @@ class LabelMergerMixin(MemoryMixin):
         return new_label
 
     def copy(self, memo=None):
-        copied = super().copy(memo)
-        return copied
+        return super().copy(memo)

angr/storage/memory_mixins/multi_value_merger_mixin.py

@@ -1,4 +1,5 @@
 # pylint:disable=missing-class-docstring
+from __future__ import annotations
 from typing import Any
 from collections.abc import Iterable, Callable
 

angr/storage/memory_mixins/name_resolution_mixin.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import claripy
 from archinfo.arch_arm import is_arm_arch
 from . import MemoryMixin
@@ -22,20 +23,19 @@ class NameResolutionMixin(MemoryMixin):
                     return (((stn_map[name] + self.load("ftop")) & 7) << 3) + self.state.arch.registers["fpu_regs"][
                         0
                     ], 8
-                elif name in tag_map:
+                if name in tag_map:
                     return ((tag_map[name] + self.load("ftop")) & 7) + self.state.arch.registers["fpu_tags"][0], 1
-                elif name in ("flags", "eflags", "rflags"):
+                if name in ("flags", "eflags", "rflags"):
                     # we tweak the state to convert the vex condition registers into the flags register
                     if not is_write:  # this work doesn't need to be done if we're just gonna overwrite it
                         self.store("cc_dep1", _get_flags(self.state))  # constraints cannot be added by this
                     self.store("cc_op", 0)  # OP_COPY
                     return self.state.arch.registers["cc_dep1"]
-            if is_arm_arch(self.state.arch):
-                if name == "flags":
-                    if not is_write:
-                        self.store("cc_dep1", _get_flags(self.state))
-                    self.store("cc_op", 0)
-                    return self.state.arch.registers["cc_dep1"]
+            if is_arm_arch(self.state.arch) and name == "flags":
+                if not is_write:
+                    self.store("cc_dep1", _get_flags(self.state))
+                self.store("cc_op", 0)
+                return self.state.arch.registers["cc_dep1"]
 
             if name == "sp" and "sp" not in self.state.arch.registers:
                 sp_reg_name = self.state.arch.register_names[self.state.arch.sp_offset]
@@ -45,10 +45,9 @@ class NameResolutionMixin(MemoryMixin):
                 return self.state.arch.registers[lr_reg_name]
 
             return self.state.arch.registers[name]
-        elif name[0] == "*":
+        if name[0] == "*":
             return self.state.registers.load(name[1:]), None
-        else:
-            raise SimMemoryError("Trying to address memory with a register name.")
+        raise SimMemoryError("Trying to address memory with a register name.")
 
     def store(self, addr, data, size=None, **kwargs):
         if isinstance(addr, str):
@@ -56,15 +55,13 @@ class NameResolutionMixin(MemoryMixin):
             if isinstance(data, claripy.ast.BV) and len(data) < named_size * self.state.arch.byte_width:
                 data = data.zero_extend(named_size * self.state.arch.byte_width - len(data))
             return super().store(named_addr, data, size=named_size if size is None else size, **kwargs)
-        else:
-            return super().store(addr, data, size=size, **kwargs)
+        return super().store(addr, data, size=size, **kwargs)
 
     def load(self, addr, size=None, **kwargs):
         if isinstance(addr, str):
             named_addr, named_size = self._resolve_location_name(addr, is_write=False)
             return super().load(named_addr, size=named_size if size is None else size, **kwargs)
-        else:
-            return super().load(addr, size=size, **kwargs)
+        return super().load(addr, size=size, **kwargs)
 
 
 from ...errors import SimMemoryError

angr/storage/memory_mixins/paged_memory/page_backer_mixins.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 from mmap import mmap
 from typing import Union
 from collections.abc import Generator
@@ -93,9 +94,9 @@ class ClemoryBackerMixin(PagedMemoryMixin):
         # initialize the page
         if isinstance(backer, (bytes, bytearray, mmap)):
             return self._data_from_bytes_backer(addr, backer, backer_start, backer_iter)
-        elif isinstance(backer, list):
+        if isinstance(backer, list):
             return self._data_from_lists_backer(addr, backer, backer_start, backer_iter)
-        raise TypeError("Unsupported backer type %s." % type(backer))
+        raise TypeError(f"Unsupported backer type {type(backer)}.")
 
     def _calc_page_starts(self, addr: int, backer_start: int, backer_length: int) -> tuple[int, int, int]:
         # lord help me. why do I keep having to write code that looks like this
@@ -118,7 +119,7 @@ class ClemoryBackerMixin(PagedMemoryMixin):
         addr: int,
         backer: bytes | bytearray,
         backer_start: int,
-        backer_iter: Generator[tuple[int, bytes | bytearray], None, None],
+        backer_iter: Generator[tuple[int, bytes | bytearray]],
     ) -> claripy.ast.BV:
         if backer_start <= addr and backer_start + len(backer) >= addr + self.page_size:
             # fast case
@@ -145,7 +146,7 @@ class ClemoryBackerMixin(PagedMemoryMixin):
         return data
 
     def _data_from_lists_backer(
-        self, addr: int, backer: list[int], backer_start: int, backer_iter: Generator[tuple[int, list[int]], None, None]
+        self, addr: int, backer: list[int], backer_start: int, backer_iter: Generator[tuple[int, list[int]]]
     ) -> claripy.ast.BV:
         page_data = [0] * self.page_size
         while backer_start < addr + self.page_size:
@@ -161,8 +162,7 @@ class ClemoryBackerMixin(PagedMemoryMixin):
             except StopIteration:
                 break
 
-        data = claripy.Concat(*map(lambda v: claripy.BVV(v, self.state.arch.byte_width), page_data))
-        return data
+        return claripy.Concat(*(claripy.BVV(v, self.state.arch.byte_width) for v in page_data))
 
     def _cle_permissions_lookup(self, addr):
         if self._cle_loader is None:

angr/storage/memory_mixins/paged_memory/paged_memory_mixin.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import cffi
 from typing import Any
 from collections.abc import Iterable
@@ -109,7 +110,7 @@ class PagedMemoryMixin(MemoryMixin):
     def _divide_addr(self, addr: int) -> tuple[int, int]:
         return divmod(addr, self.page_size)
 
-    def load(self, addr: int, size: int = None, endness=None, **kwargs):
+    def load(self, addr: int, size: int | None = None, endness=None, **kwargs):
         if endness is None:
             endness = self.endness
 
@@ -163,7 +164,7 @@ class PagedMemoryMixin(MemoryMixin):
         l.debug("%s.load(%#x, %d, %s) = %s", self.id, addr, size, endness, out)
         return out
 
-    def store(self, addr: int, data, size: int = None, endness=None, **kwargs):
+    def store(self, addr: int, data, size: int | None = None, endness=None, **kwargs):
         if endness is None:
             endness = self.endness
 
@@ -252,7 +253,7 @@ class PagedMemoryMixin(MemoryMixin):
             pageno = (pageno + 1) % max_pageno
             pageoff = 0
 
-    def merge(self, others: Iterable["PagedMemoryMixin"], merge_conditions, common_ancestor=None) -> bool:
+    def merge(self, others: Iterable[PagedMemoryMixin], merge_conditions, common_ancestor=None) -> bool:
         changed_pages_and_offsets: dict[int, set[int] | None] = {}
         for o in others:
             for changed_page, changed_offsets in self.changed_pages(o).items():
@@ -295,7 +296,7 @@ class PagedMemoryMixin(MemoryMixin):
 
         return bool(merged_bytes)
 
-    def compare(self, other: "PagedMemoryMixin") -> bool:
+    def compare(self, other: PagedMemoryMixin) -> bool:
         changed_pages_and_offsets: dict[int, set[int] | None] = dict(self.changed_pages(other))
 
         for page_no in sorted(changed_pages_and_offsets):
@@ -320,10 +321,10 @@ class PagedMemoryMixin(MemoryMixin):
         try:
             page = self._get_page(pageno, permissions is not None, allow_default=False, **kwargs)
         except SimMemoryError as e:
-            raise SimMemoryError("%#x is not mapped" % addr) from e
+            raise SimMemoryError(f"{addr:#x} is not mapped") from e
 
         if type(permissions) is int:
-            permissions = self.state.solver.BVV(permissions, 3)
+            permissions = claripy.BVV(permissions, 3)
 
         result = page.permissions
         if permissions is not None:
@@ -403,9 +404,8 @@ class PagedMemoryMixin(MemoryMixin):
         if result.op == "BVV":
             if with_bitmap:
                 return memoryview(result.args[0].to_bytes(size, "big")), memoryview(bytes(size))
-            else:
-                return memoryview(result.args[0].to_bytes(size, "big"))
-        elif result.op == "Concat":
+            return memoryview(result.args[0].to_bytes(size, "big"))
+        if result.op == "Concat":
             bytes_out = bytearray(size)
             bitmap_out = bytearray(size)
             bit_idx = 0
@@ -423,18 +423,12 @@ class PagedMemoryMixin(MemoryMixin):
                     bitmap_out[byte_idx] = 1
                     continue
 
-                if bit_idx % byte_width != 0:
-                    # if the current element has at least byte_width bits, the top `hi_chop` bits should be removed
-                    hi_chop = byte_width - (bit_idx % byte_width)
-                else:
-                    hi_chop = 0
+                # if the current element has at least byte_width bits, the top `hi_chop` bits should be removed
+                hi_chop = byte_width - bit_idx % byte_width if bit_idx % byte_width != 0 else 0
 
-                if (bit_idx + len(element)) % byte_width != 0:
-                    # if the current element does not have enough bits to extend to the next byte boundary, the
-                    # bottom `lo_chop` bits should be removed
-                    lo_chop = (bit_idx + len(element)) % byte_width
-                else:
-                    lo_chop = 0
+                # if the current element does not have enough bits to extend to the next byte boundary, the
+                # bottom `lo_chop` bits should be removed
+                lo_chop = (bit_idx + len(element)) % byte_width if (bit_idx + len(element)) % byte_width != 0 else 0
 
                 if hi_chop + lo_chop == len(element):
                     # the entire element will be removed
@@ -470,13 +464,10 @@ class PagedMemoryMixin(MemoryMixin):
                     bitmap_out[bit_idx // byte_width] = 1
             if with_bitmap:
                 return memoryview(bytes(bytes_out)), memoryview(bytes(bitmap_out))
-            else:
-                return memoryview(bytes(bytes_out))
-        else:
-            if with_bitmap:
-                return memoryview(bytes(size)), memoryview(b"\x01" * size)
-            else:
-                return memoryview(b"")
+            return memoryview(bytes(bytes_out))
+        if with_bitmap:
+            return memoryview(bytes(size)), memoryview(b"\x01" * size)
+        return memoryview(b"")
 
     def concrete_load(self, addr, size, writing=False, with_bitmap=False, **kwargs):
         pageno, offset = self._divide_addr(addr)
@@ -486,8 +477,7 @@ class PagedMemoryMixin(MemoryMixin):
         except SimMemoryError:
             if with_bitmap:
                 return memoryview(b""), memoryview(b"")
-            else:
-                return memoryview(b"")
+            return memoryview(b"")
 
         if not page.SUPPORTS_CONCRETE_LOAD:
             # the page does not support concrete_load
@@ -572,9 +562,7 @@ class PagedMemoryMixin(MemoryMixin):
 
             if (my_page is None) ^ (other_page is None):
                 changes.update(range(pageno * self.page_size, (pageno + 1) * self.page_size))
-            elif my_page is None:
-                pass
-            elif my_page is other_page:
+            elif my_page is None or my_page is other_page:
                 pass
             else:
                 changes.update(
@@ -597,9 +585,7 @@ class PagedMemoryMixin(MemoryMixin):
 
             if (my_page is None) ^ (other_page is None):
                 changes[pageno] = None
-            elif my_page is None:
-                pass
-            elif my_page is other_page:
+            elif my_page is None or my_page is other_page:
                 pass
             else:
                 changed_offsets = my_page.changed_bytes(other_page, page_addr=pageno * self.page_size)
@@ -657,7 +643,7 @@ class PagedMemoryMixin(MemoryMixin):
 
 class LabeledPagesMixin(PagedMemoryMixin):
     def load_with_labels(
-        self, addr: int, size: int = None, endness=None, **kwargs
+        self, addr: int, size: int | None = None, endness=None, **kwargs
     ) -> tuple[claripy.ast.Base, tuple[tuple[int, int, int, Any]]]:
         if endness is None:
             endness = self.endness
@@ -726,7 +712,7 @@ class MVListPagesMixin(PagedMemoryMixin):
         self.skip_missing_values_during_merging = skip_missing_values_during_merging
 
     @MemoryMixin.memo
-    def copy(self, memo) -> "MVListPagesMixin":
+    def copy(self, memo) -> MVListPagesMixin:
         r = super().copy(memo)
         r.skip_missing_values_during_merging = self.skip_missing_values_during_merging
         return r

angr/storage/memory_mixins/paged_memory/paged_memory_multivalue_mixin.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 from .. import MemoryMixin
 
 

angr/storage/memory_mixins/paged_memory/pages/__init__.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import typing
 
 from angr.storage.memory_mixins import MemoryMixin
@@ -23,8 +24,6 @@ class PageBase(HistoryTrackingMixin, RefcountMixin, CooperationBase, ISPOMixin,
     Read the docstrings for each of the constituent classes to understand the nuances of their functionalities
     """
 
-    pass
-
 
 PageType = typing.TypeVar("PageType", bound=PageBase)
 

angr/storage/memory_mixins/paged_memory/pages/cooperation.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 from typing import Any
 
 import claripy
@@ -207,13 +208,13 @@ class MemoryObjectSetMixin(CooperationBase):
             return MultiValues(offset_to_values={0: elements[0]})
 
         if endness == "Iend_LE":
-            elements = list(reversed(elements))
+            elements.reverse()
 
         mv = MultiValues()
         offset = 0
         start_offset = 0
         prev_value = ...
-        for i, value_set in enumerate(elements):
+        for value_set in elements:
             if len(value_set) == 1:
                 if prev_value is ...:
                     prev_value = next(iter(value_set))
@@ -258,7 +259,7 @@ class MemoryObjectSetMixin(CooperationBase):
                         )
                     )
 
-            sorted_offsets = list(sorted(offset_to_mos.keys()))
+            sorted_offsets = sorted(offset_to_mos.keys())
             pos = 0
             while pos < len(sorted_offsets):
                 mos = set(offset_to_mos[sorted_offsets[pos]])

angr/storage/memory_mixins/paged_memory/pages/history_tracking_mixin.py

@@ -1,4 +1,5 @@
 # pylint:disable=arguments-differ,unused-argument,no-member
+from __future__ import annotations
 
 from angr.storage.memory_mixins import MemoryMixin
 from angr.utils.segment_list import SegmentList
@@ -26,8 +27,7 @@ class HistoryTrackingMixin(RefcountMixin, MemoryMixin):
         return super().store(addr, data, **kwargs)
 
     def copy(self, memo):
-        o = super().copy(memo)
-        return o
+        return super().copy(memo)
 
     def acquire_unique(self):
         page = super().acquire_unique()
@@ -52,8 +52,8 @@ class HistoryTrackingMixin(RefcountMixin, MemoryMixin):
     def changed_bytes(self, other, **kwargs) -> set[int] | None:
         candidates: set[int] = set()
 
-        self_history_list = [self] + list(self.parents())
-        other_history_list = [other] + list(other.parents())
+        self_history_list = [self, *list(self.parents())]
+        other_history_list = [other, *list(other.parents())]
         if self_history_list and other_history_list and self_history_list[-1] is other_history_list[-1]:
             # two pages have the same root. we can get a list of candidate offsets this way