angr 9.2.116__py3-none-manylinux2014_aarch64.whl → 9.2.118__py3-none-manylinux2014_aarch64.whl

angr/engines/vex/claripy/irop.py

@@ -2,6 +2,8 @@
 This module contains symbolic implementations of VEX operations.
 """
 
+from __future__ import annotations
+
 from functools import partial
 import collections
 import itertools
@@ -50,31 +52,30 @@ def op_attrs(p):
 
     if not m:
         return None
-    else:
-        attrs = m.groupdict()
-
-        attrs["from_signed"] = attrs["from_signed_back"] if attrs["from_signed"] is None else attrs["from_signed"]
-        attrs.pop("from_signed_back", None)
-        if attrs["generic_name"] == "CmpOR":
-            assert attrs["from_type"] == "D"
-            attrs["generic_name"] = "CmpORD"
-            attrs["from_type"] = None
-
-        # fix up vector stuff
-        vector_info = attrs.pop("vector_info", None)
-        if vector_info:
-            vm = re.match(
-                r"^(?P<vector_size>\d+)?"
-                r"(?P<vector_signed>[US])?"
-                r"(?P<vector_type>[FD])?"
-                r"(?P<vector_zero>0)?"
-                r"x"
-                r"(?P<vector_count>\d+)?$",
-                vector_info,
-            )
-            attrs.update(vm.groupdict())
+    attrs = m.groupdict()
+
+    attrs["from_signed"] = attrs["from_signed_back"] if attrs["from_signed"] is None else attrs["from_signed"]
+    attrs.pop("from_signed_back", None)
+    if attrs["generic_name"] == "CmpOR":
+        assert attrs["from_type"] == "D"
+        attrs["generic_name"] = "CmpORD"
+        attrs["from_type"] = None
+
+    # fix up vector stuff
+    vector_info = attrs.pop("vector_info", None)
+    if vector_info:
+        vm = re.match(
+            r"^(?P<vector_size>\d+)?"
+            r"(?P<vector_signed>[US])?"
+            r"(?P<vector_type>[FD])?"
+            r"(?P<vector_zero>0)?"
+            r"x"
+            r"(?P<vector_count>\d+)?$",
+            vector_info,
+        )
+        attrs.update(vm.groupdict())
 
-        return attrs
+    return attrs
 
 
 all_operations = list(pyvex.irop_enums_to_ints.keys())
@@ -265,7 +266,7 @@ class SimIROp:
         for k, v in self.op_attrs.items():
             if v is not None and ("size" in k or "count" in k):
                 v = int(v)
-            setattr(self, "_%s" % k, v)
+            setattr(self, f"_{k}", v)
 
         # determine the output size
         # pylint:disable=no-member
@@ -385,8 +386,8 @@ class SimIROp:
 
         # TODO: clean up this mess
         # specifically-implemented generics
-        elif self._float and hasattr(self, "_op_fgeneric_%s" % self._generic_name):
-            calculate = getattr(self, "_op_fgeneric_%s" % self._generic_name)
+        elif self._float and hasattr(self, f"_op_fgeneric_{self._generic_name}"):
+            calculate = getattr(self, f"_op_fgeneric_{self._generic_name}")
             if self._vector_size is not None and not hasattr(calculate, "supports_vector"):
                 # NOTE: originally this branch just marked the op as unsupported but I think we can do better
                 # "marking unsupported" seems to include adding the op to the vector_operations list? why
@@ -394,8 +395,8 @@ class SimIROp:
             else:
                 self._calculate = calculate
 
-        elif not self._float and hasattr(self, "_op_generic_%s" % self._generic_name):
-            calculate = getattr(self, "_op_generic_%s" % self._generic_name)
+        elif not self._float and hasattr(self, f"_op_generic_{self._generic_name}"):
+            calculate = getattr(self, f"_op_generic_{self._generic_name}")
             if self._vector_size is not None and not hasattr(calculate, "supports_vector"):
                 # NOTE: same as above
                 self._calculate = partial(self._auto_vectorize, calculate)
@@ -408,13 +409,13 @@ class SimIROp:
 
         # if we're here and calculate is None, we don't support this
         if self._calculate is None:
-            raise UnsupportedIROpError("no calculate function identified for %s" % self.name)
+            raise UnsupportedIROpError(f"no calculate function identified for {self.name}")
 
     def __repr__(self):
-        return "<SimIROp %s>" % self.name
+        return f"<SimIROp {self.name}>"
 
     def _dbg_print_attrs(self):
-        print("Operation: %s" % self.name)
+        print(f"Operation: {self.name}")
         for k, v in self.op_attrs.items():
             if v is not None and v != "":
                 print(f"... {k}: {v}")
@@ -429,12 +430,11 @@ class SimIROp:
         try:
             if self._vector_size is None:
                 return self.extend_size(self._calculate(args))
-            else:
-                return self._calculate(args)
+            return self._calculate(args)
         except (ZeroDivisionError, claripy.ClaripyZeroDivisionError) as e:
             raise SimZeroDivisionException("divide by zero!") from e
         except (TypeError, ValueError, SimValueError, claripy.ClaripyError) as e:
-            raise SimOperationError("%s._calculate() raised exception" % self.name) from e
+            raise SimOperationError(f"{self.name}._calculate() raised exception") from e
 
     def extend_size(self, o):
         cur_size = o.size()
@@ -452,12 +452,11 @@ class SimIROp:
                 or (self._to_signed is None and self._vector_signed == "S")
             ):
                 return claripy.SignExt(ext_size, o)
-            else:
-                return claripy.ZeroExt(ext_size, o)
+            return claripy.ZeroExt(ext_size, o)
 
         # if cur_size > target_size:
         # it should never happen!
-        raise SimOperationError("output of %s is too big" % self.name)
+        raise SimOperationError(f"output of {self.name} is too big")
 
     @property
     def is_signed(self):
@@ -481,14 +480,14 @@ class SimIROp:
                     else:
                         sized_args.append(claripy.ZeroExt(self._from_size - s, a))
                 elif s > self._from_size:
-                    raise SimOperationError("operation %s received too large an argument" % self.name)
+                    raise SimOperationError(f"operation {self.name} received too large an argument")
         else:
             sized_args = args
 
         if self._generic_name in operation_map:  # bitwise/arithmetic/shift operations
             o = operation_map[self._generic_name]
         else:
-            raise SimOperationError("op_mapped called with invalid mapping, for %s" % self.name)
+            raise SimOperationError(f"op_mapped called with invalid mapping, for {self.name}")
 
         if o == "__floordiv__" and self.is_signed:
             # yikes!!!!!!!
@@ -501,9 +500,8 @@ class SimIROp:
     def _translate_rm(self, rm_num):
         if not rm_num.symbolic:
             return rm_map[rm_num.concrete_value]
-        else:
-            l.warning("symbolic rounding mode found, using default")
-            return claripy.fp.RM.default()
+        l.warning("symbolic rounding mode found, using default")
+        return claripy.fp.RM.default()
 
     NO_RM = {"Neg", "Abs"}
 
@@ -656,9 +654,7 @@ class SimIROp:
         elements = dReg.chop(vector_size)
 
         # Generate new elements
-        new_elements = map(
-            lambda i: claripy.If(vector_count - 1 - i == index, element, elements[i]), range(vector_count)
-        )
+        new_elements = (claripy.If(vector_count - 1 - i == index, element, elements[i]) for i in range(vector_count))
         return claripy.Concat(*new_elements)
 
     def _op_generic_Mull(self, args):
@@ -737,8 +733,7 @@ class SimIROp:
                     )
                 )
             return claripy.Concat(*res_comps)
-        else:
-            return claripy.If(comparison(args[0], args[1]), claripy.BVV(1, 1), claripy.BVV(0, 1))
+        return claripy.If(comparison(args[0], args[1]), claripy.BVV(1, 1), claripy.BVV(0, 1))
 
     @supports_vector
     def _op_generic_CmpEQ(self, args):
@@ -800,8 +795,7 @@ class SimIROp:
                 left = claripy.Extract((i + 1) * self._vector_size - 1, i * self._vector_size, args[0])
                 shifted.append(op(left, shift_by))
             return claripy.Concat(*shifted)
-        else:
-            raise SimOperationError("you done fucked")
+        raise SimOperationError("you done fucked")
 
     @supports_vector
     def _op_generic_ShlN(self, args):
@@ -898,14 +892,13 @@ class SimIROp:
             return claripy.Concat(
                 claripy.Extract(remainder_size - 1, 0, remainder), claripy.Extract(quotient_size - 1, 0, quotient)
             )
-        else:
-            quotient = args[0] // claripy.ZeroExt(self._from_size - self._to_size, args[1])
-            remainder = args[0] % claripy.ZeroExt(self._from_size - self._to_size, args[1])
-            quotient_size = self._to_size
-            remainder_size = self._to_size
-            return claripy.Concat(
-                claripy.Extract(remainder_size - 1, 0, remainder), claripy.Extract(quotient_size - 1, 0, quotient)
-            )
+        quotient = args[0] // claripy.ZeroExt(self._from_size - self._to_size, args[1])
+        remainder = args[0] % claripy.ZeroExt(self._from_size - self._to_size, args[1])
+        quotient_size = self._to_size
+        remainder_size = self._to_size
+        return claripy.Concat(
+            claripy.Extract(remainder_size - 1, 0, remainder), claripy.Extract(quotient_size - 1, 0, quotient)
+        )
 
     # pylint:enable=no-self-use,unused-argument
 
@@ -943,17 +936,15 @@ class SimIROp:
 
         if not self._vector_size:
             return self._compute_fp_to_int(rm, arg.raw_to_fp(), self._to_size)
-        else:
-            vector_args = arg.chop(self._vector_size)
-            return claripy.Concat(
-                *[self._compute_fp_to_int(rm, varg.raw_to_fp(), self._vector_size) for varg in vector_args]
-            )
+        vector_args = arg.chop(self._vector_size)
+        return claripy.Concat(
+            *[self._compute_fp_to_int(rm, varg.raw_to_fp(), self._vector_size) for varg in vector_args]
+        )
 
     def _compute_fp_to_int(self, rm, arg, to_size):
         if self._to_signed == "S":
             return claripy.fpToSBV(rm, arg, to_size)
-        else:
-            return claripy.fpToUBV(rm, arg, to_size)
+        return claripy.fpToUBV(rm, arg, to_size)
 
     def _op_fgeneric_Cmp(self, args):  # pylint:disable=no-self-use
         # see https://github.com/angr/vex/blob/master/pub/libvex_ir.h#L580
@@ -994,19 +985,18 @@ class SimIROp:
             chopped = [arg[(self._vector_size - 1) : 0].raw_to_fp() for arg in args]
             result = f(*chopped).raw_to_bv()
             return claripy.Concat(args[0][(args[0].length - 1) : self._vector_size], result)
-        else:
-            # I'm changing this behavior because I think this branch was never used otherwise
-            # before it only chopped the first argument but I'm going to make it chop all of them
-            result = []
-            for lane_args in self.vector_args(args):
-                if self._float:
-                    # HACK HACK HACK
-                    # this is such a weird divergence. why do the fp generics take several args and the int generics
-                    # take a list?
-                    result.append(f(*lane_args).raw_to_bv())
-                else:
-                    result.append(f(lane_args))
-            return claripy.Concat(*result)
+        # I'm changing this behavior because I think this branch was never used otherwise
+        # before it only chopped the first argument but I'm going to make it chop all of them
+        result = []
+        for lane_args in self.vector_args(args):
+            if self._float:
+                # HACK HACK HACK
+                # this is such a weird divergence. why do the fp generics take several args and the int generics
+                # take a list?
+                result.append(f(*lane_args).raw_to_bv())
+            else:
+                result.append(f(lane_args))
+        return claripy.Concat(*result)
 
     @staticmethod
     def _fgeneric_minmax(cmp_op, a, b):
@@ -1022,10 +1012,9 @@ class SimIROp:
     def _op_fgeneric_Reinterp(self, args):
         if self._to_type == "I":
             return args[0].raw_to_bv()
-        elif self._to_type == "F":
+        if self._to_type == "F":
             return args[0].raw_to_fp()
-        else:
-            raise SimOperationError("unsupport Reinterp _to_type")
+        raise SimOperationError("unsupported Reinterp _to_type")
 
     @supports_vector
     def _op_fgeneric_Round(self, args):
@@ -1043,18 +1032,17 @@ class SimIROp:
                 left = claripy.Extract((i + 1) * self._vector_size - 1, i * self._vector_size, args[0]).raw_to_fp()
                 rounded.append(claripy.fpToSBV(rm, left, self._vector_size))
             return claripy.Concat(*rounded)
-        else:
-            rm = self._translate_rm(args[0])
-            rounded_bv = claripy.fpToSBV(rm, args[1].raw_to_fp(), args[1].length)
+        rm = self._translate_rm(args[0])
+        rounded_bv = claripy.fpToSBV(rm, args[1].raw_to_fp(), args[1].length)
 
-            # if exponent is large enough, floating points are always integers.
-            fsort = claripy.fp.FSort.from_size(args[1].length)
-            mantissa_bits = fsort.mantissa - 1  # -1 since FSort has mantissa value 1 higher than the number of bits
-            exp_bits = fsort.exp
-            rounded_fp = claripy.fpToFP(claripy.fp.RM.RM_NearestTiesEven, rounded_bv, fsort)
-            exp_bv = args[1].raw_to_bv()[exp_bits + mantissa_bits - 1 : mantissa_bits]
-            exp_threshold = (2 ** (exp_bits - 1) - 1) + mantissa_bits
-            return claripy.If(exp_bv >= exp_threshold, args[1].raw_to_fp(), rounded_fp)
+        # if exponent is large enough, floating points are always integers.
+        fsort = claripy.fp.FSort.from_size(args[1].length)
+        mantissa_bits = fsort.mantissa - 1  # -1 since FSort has mantissa value 1 higher than the number of bits
+        exp_bits = fsort.exp
+        rounded_fp = claripy.fpToFP(claripy.fp.RM.RM_NearestTiesEven, rounded_bv, fsort)
+        exp_bv = args[1].raw_to_bv()[exp_bits + mantissa_bits - 1 : mantissa_bits]
+        exp_threshold = (2 ** (exp_bits - 1) - 1) + mantissa_bits
+        return claripy.If(exp_bv >= exp_threshold, args[1].raw_to_fp(), rounded_fp)
 
     def _generic_pack_saturation(self, args, src_size, dst_size, src_signed, dst_signed):
         """
@@ -1065,18 +1053,15 @@ class SimIROp:
         So far as I know plain saturating conversion should only ever have to be performed on vectors.
         """
         if src_size <= 0 or dst_size <= 0:
-            raise SimOperationError("Can't pack from or to zero or negative size: %s" % self.name)
+            raise SimOperationError(f"Can't pack from or to zero or negative size: {self.name}")
         if src_size < dst_size:
-            raise SimOperationError("Can't pack from small size into larger size: %s" % self.name)
+            raise SimOperationError(f"Can't pack from small size into larger size: {self.name}")
         result = None
 
         max_value = 2**dst_size - 1
         if dst_signed:
             max_value >>= 1
-        if not dst_signed or not src_signed:
-            min_value = 0
-        else:
-            min_value = -(2 ** (dst_size - 1))
+        min_value = 0 if not dst_signed or not src_signed else -(2 ** (dst_size - 1))
 
         gt = claripy.SGT if src_signed else claripy.UGT
         lt = claripy.SLT if src_signed else claripy.ULT
@@ -1088,10 +1073,7 @@ class SimIROp:
                     max_value,
                     claripy.If(lt(src_value, min_value), min_value, src_value[dst_size - 1 : 0]),
                 )
-                if result is None:
-                    result = dst_value
-                else:
-                    result = self._op_concat((result, dst_value))
+                result = dst_value if result is None else self._op_concat((result, dst_value))
         return result
 
     @supports_vector
@@ -1188,8 +1170,7 @@ class SimIROp:
         if self._set_size in {32, 64}:
             if self._set_size != args[1].size():
                 raise SimOperationError(f"Unexpected args[1] size {args[1].size()}")
-            v = claripy.Concat(args[0][args[0].size() - 1 : self._set_size], args[1])
-            return v
+            return claripy.Concat(args[0][args[0].size() - 1 : self._set_size], args[1])
         raise NotImplementedError(f"Unsupported set_size {self._set_size}")
 
     # def _op_Iop_Yl2xF64(self, args):

angr/engines/vex/heavy/__init__.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 from .heavy import HeavyVEXMixin
 from .inspect import SimInspectMixin
 from .actions import TrackActionsMixin

angr/engines/vex/heavy/actions.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import pyvex
 
 from .heavy import HeavyVEXMixin

angr/engines/vex/heavy/concretizers.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import math
 
 import claripy
@@ -57,13 +58,13 @@ def concretize_cmpf64(state, args):
     fp_arg0 = state.solver.eval(args[0])
     fp_arg1 = state.solver.eval(args[1])
     if fp_arg0 < fp_arg1:
-        return state.solver.BVV(1, 32)
+        return claripy.BVV(1, 32)
     if fp_arg0 > fp_arg1:
-        return state.solver.BVV(0, 32)
+        return claripy.BVV(0, 32)
     if fp_arg0 == fp_arg1:
-        return state.solver.BVV(0x40, 32)
+        return claripy.BVV(0x40, 32)
 
-    return state.solver.BVV(0x45, 32)
+    return claripy.BVV(0x45, 32)
 
 
 def concretize_divf64(state, args):
@@ -113,13 +114,13 @@ def concretize_float64_to_int64s(state, args):
 
 
 def concretize_int32s_to_float64(state, args):
-    arg = state.solver.BVV(state.solver.eval(args[0]), args[0].size())
+    arg = claripy.BVV(state.solver.eval(args[0]), args[0].size())
     return arg.val_to_fp(claripy.fp.FSort.from_size(64), signed=True, rm=fp_rm_map[0])
 
 
 def concretize_int64s_to_float64(state, args):
     rm = translate_rm(args[0])
-    arg = state.solver.BVV(state.solver.eval(args[1]), args[1].size())
+    arg = claripy.BVV(state.solver.eval(args[1]), args[1].size())
     return arg.val_to_fp(claripy.fp.FSort.from_size(64), signed=True, rm=rm)
 
 
@@ -191,10 +192,9 @@ def concretize_prem(state, args):
         quotient = math.floor((dividend / divisor) / pow(2, exp_dividend - exp_divisor - N))
         result = dividend - (divisor * quotient * pow(2, exp_dividend - exp_divisor - N))
 
-    if result == 0.0:
-        if math.copysign(1.0, dividend) < 0:
-            # According to Intel manual, if result is 0, its sign should be same as that of dividend.
-            return state.solver.FPV(-0.0, claripy.FSORT_DOUBLE)
+    if result == 0.0 and math.copysign(1.0, dividend) < 0:
+        # According to Intel manual, if result is 0, its sign should be same as that of dividend.
+        return state.solver.FPV(-0.0, claripy.FSORT_DOUBLE)
 
     return state.solver.FPV(result, claripy.FSORT_DOUBLE)
 
@@ -335,19 +335,18 @@ def concretize_yl2x(state, args):
     if arg_x == 0:
         if abs(arg_y) == math.inf:
             return state.solver.FPV(-1 * arg_y, claripy.FSORT_DOUBLE)
-        elif arg_y == 0:
+        if arg_y == 0:
             # TODO: Indicate floating-point invalid-operation exception
             return state.solver.FPV(arg_x, claripy.FSORT_DOUBLE)
-        else:
-            # TODO: Indicate floating-point zero-division exception
-            return state.solver.FPV(arg_x, claripy.FSORT_DOUBLE)
+        # TODO: Indicate floating-point zero-division exception
+        return state.solver.FPV(arg_x, claripy.FSORT_DOUBLE)
 
     if arg_x == 1:
         if abs(arg_y) == math.inf:
             # TODO: Indicate floating-point invalid-operation exception
             return state.solver.FPV(arg_x, claripy.FSORT_DOUBLE)
 
-        # TODO: How to distiguish between +0 and -0?
+        # TODO: How to distinguish between +0 and -0?
         return state.solver.FPV(0, claripy.FSORT_DOUBLE)
 
     if arg_x == math.inf:

angr/engines/vex/heavy/dirty.py

@@ -1,8 +1,9 @@
-import claripy
-
+from __future__ import annotations
 import logging
 import time
 
+import claripy
+
 from angr import sim_options as o, errors
 
 l = logging.getLogger(name=__name__)
@@ -20,16 +21,16 @@ l = logging.getLogger(name=__name__)
 # http://www.cap-lore.com/code/TB/
 def ppcg_dirtyhelper_MFTB(state):
     # TODO: This is an incorrect implementation. Fix it later!
-    return state.solver.BVV(0x200, 64), []
+    return claripy.BVV(0x200, 64), []
 
 
 def ppc32g_dirtyhelper_MFSPR_287(state):
-    return state.solver.BVV(0x200, 32), []
+    return claripy.BVV(0x200, 32), []
 
 
 def amd64g_dirtyhelper_RDTSC(state):
     if o.USE_SYSTEM_TIMES in state.options:
-        val = state.solver.BVV(int(time.process_time() * 1000000) + 12345678, 64)
+        val = claripy.BVV(int(time.process_time() * 1000000) + 12345678, 64)
     else:
         val = state.solver.BVS("RDTSC", 64, key=("hardware", "rdtsc"))
     return val, []
@@ -121,15 +122,13 @@ EmWarn_S390X_invalid_rounding = 11
 def amd64g_check_ldmxcsr(state, mxcsr):
     rmode = state.solver.LShR(mxcsr, 13) & 3
 
-    ew = state.solver.If(
+    ew = claripy.If(
         (mxcsr & 0x1F80) != 0x1F80,
-        state.solver.BVV(EmWarn_X86_sseExns, 64),
-        state.solver.If(
+        claripy.BVV(EmWarn_X86_sseExns, 64),
+        claripy.If(
             mxcsr & (1 << 15) != 0,
-            state.solver.BVV(EmWarn_X86_fz, 64),
-            state.solver.If(
-                mxcsr & (1 << 6) != 0, state.solver.BVV(EmWarn_X86_daz, 64), state.solver.BVV(EmNote_NONE, 64)
-            ),
+            claripy.BVV(EmWarn_X86_fz, 64),
+            claripy.If(mxcsr & (1 << 6) != 0, claripy.BVV(EmWarn_X86_daz, 64), claripy.BVV(EmNote_NONE, 64)),
         ),
     )
 
@@ -138,7 +137,7 @@ def amd64g_check_ldmxcsr(state, mxcsr):
 
 # see canonical implementation of this in guest_amd64_helpers.c
 def amd64g_dirtyhelper_XRSTOR_COMPONENT_1_EXCLUDING_XMMREGS(state, _, addr):
-    w32 = state.solver.BVV(
+    w32 = claripy.BVV(
         (state.mem[state.solver.eval(addr) + 12 * 2].short.concrete & 0xFFFF)
         | ((state.mem[state.solver.eval(addr) + 13 * 2].short.concrete & 0xFFFF) << 16),
         64,
@@ -348,7 +347,7 @@ def x86g_dirtyhelper_SxDT(state, addr, op):
     if not op.concrete:
         # resolved failed
         return None, []
-    elif op.concrete_value == 0:
+    if op.concrete_value == 0:
         state.memory.store(addr, state.solver.Unconstrained("SIDT", 48))
     elif op.concrete_value == 1:
         state.memory.store(addr, state.regs.gdt)
@@ -365,7 +364,7 @@ def x86g_dirtyhelper_LGDT_LIDT(state, addr, op):
     base = state.memory.load(addr + 2, 4, endness="Iend_LE")
 
     if op.concrete_value == 2:
-        state.regs.gdt = state.solver.Concat(base, limit).zero_extend(16)
+        state.regs.gdt = claripy.Concat(base, limit).zero_extend(16)
     elif op.concrete_value == 3:
         # LIDT is a nop
         pass
@@ -398,8 +397,8 @@ def x86g_dirtyhelper_loadF80le(state, addr):
     mantissa = tbyte[62:0]
 
     normalized_exponent = exponent[10:0] - 16383 + 1023
-    zero_exponent = state.solver.BVV(0, 11)
-    inf_exponent = state.solver.BVV(-1, 11)
+    zero_exponent = claripy.BVV(0, 11)
+    inf_exponent = claripy.BVV(-1, 11)
     final_exponent = claripy.If(
         exponent == 0, zero_exponent, claripy.If(exponent == -1, inf_exponent, normalized_exponent)
     )
@@ -424,8 +423,8 @@ def x86g_dirtyhelper_storeF80le(state, addr, qword):
     mantissa = qword[51:0]
 
     normalized_exponent = exponent.zero_extend(4) - 1023 + 16383
-    zero_exponent = state.solver.BVV(0, 15)
-    inf_exponent = state.solver.BVV(-1, 15)
+    zero_exponent = claripy.BVV(0, 15)
+    inf_exponent = claripy.BVV(-1, 15)
     final_exponent = claripy.If(
         exponent == 0, zero_exponent, claripy.If(exponent == -1, inf_exponent, normalized_exponent)
     )
@@ -451,7 +450,7 @@ def x86g_dirtyhelper_RDMSR(state, msr):
     except errors.SimSolverError:
         return state.solver.BVS("rdmsr_?", 64, key=("cpu", "rdmsr", "?")), []
     else:
-        return state.solver.BVS("rdmsr_%#x" % msr_conc, 64, key=("cpu", "rdmsr", msr_conc), eternal=True), []
+        return state.solver.BVS(f"rdmsr_{msr_conc:#x}", 64, key=("cpu", "rdmsr", msr_conc), eternal=True), []
 
 
 def x86g_dirtyhelper_XGETBV(state, reg):
@@ -460,7 +459,7 @@ def x86g_dirtyhelper_XGETBV(state, reg):
     except errors.SimSolverError:
         return state.solver.BVS("xgetbv_?", 64, key=("cpu", "xgetbv", "?")), []
     else:
-        return state.solver.BVS("xgetbv_%#x" % reg_conc, 64, key=("cpu", "xgetbv", reg_conc), eternal=True), []
+        return state.solver.BVS(f"xgetbv_{reg_conc:#x}", 64, key=("cpu", "xgetbv", reg_conc), eternal=True), []
 
 
 amd64g_dirtyhelper_RDMSR = x86g_dirtyhelper_RDMSR

angr/engines/vex/heavy/heavy.py

@@ -1,3 +1,4 @@
+from __future__ import annotations
 import logging
 import claripy
 import pyvex
@@ -175,7 +176,7 @@ class HeavyVEXMixin(SuccessorsMixin, ClaripyDataMixin, SimStateStorageMixin, VEX
             except errors.SimReliftException as e:
                 self.state = e.state
                 if insn_bytes is not None:
-                    raise errors.SimEngineError("You cannot pass self-modifying code as insn_bytes!!!")
+                    raise errors.SimEngineError("You cannot pass self-modifying code as insn_bytes!!!") from e
                 new_ip = self.state.scratch.ins_addr
                 if size is not None:
                     size -= new_ip - addr
@@ -203,7 +204,7 @@ class HeavyVEXMixin(SuccessorsMixin, ClaripyDataMixin, SimStateStorageMixin, VEX
                 exit_state.registers.store(
                     exit_state.arch.ret_offset, exit_state.solver.Unconstrained("fake_ret_value", exit_state.arch.bits)
                 )
-                exit_state.scratch.target = exit_state.solver.BVV(successors.addr + irsb.size, exit_state.arch.bits)
+                exit_state.scratch.target = claripy.BVV(successors.addr + irsb.size, exit_state.arch.bits)
                 exit_state.history.jumpkind = "Ijk_Ret"
                 exit_state.regs.ip = exit_state.scratch.target
                 if exit_state.arch.call_pushes_ret:
@@ -215,12 +216,8 @@ class HeavyVEXMixin(SuccessorsMixin, ClaripyDataMixin, SimStateStorageMixin, VEX
                 l.debug("%s adding postcall exit.", self)
 
                 ret_state = exit_state.copy()
-                guard = (
-                    ret_state.solver.true
-                    if o.TRUE_RET_EMULATION_GUARD in self.state.options
-                    else ret_state.solver.false
-                )
-                ret_target = ret_state.solver.BVV(successors.addr + irsb.size, ret_state.arch.bits)
+                guard = claripy.true if o.TRUE_RET_EMULATION_GUARD in self.state.options else claripy.false
+                ret_target = claripy.BVV(successors.addr + irsb.size, ret_state.arch.bits)
                 ret_state.registers.store(
                     ret_state.arch.ret_offset, ret_state.solver.Unconstrained("fake_ret_value", ret_state.arch.bits)
                 )
@@ -236,6 +233,7 @@ class HeavyVEXMixin(SuccessorsMixin, ClaripyDataMixin, SimStateStorageMixin, VEX
                 )
 
         successors.processed = True
+        return None
 
     #
     # behavior instrumenting the VEXMixin
@@ -279,18 +277,18 @@ class HeavyVEXMixin(SuccessorsMixin, ClaripyDataMixin, SimStateStorageMixin, VEX
         if o.COPY_STATES not in self.state.options:
             # very special logic to try to minimize copies
             # first, check if this branch is impossible
-            if guard.is_false():
-                cont_state = self.state
-            elif o.LAZY_SOLVES not in self.state.options and not self.state.solver.satisfiable(
-                extra_constraints=(guard,)
+            if (
+                guard.is_false()
+                or o.LAZY_SOLVES not in self.state.options
+                and not self.state.solver.satisfiable(extra_constraints=(guard,))
             ):
                 cont_state = self.state
 
             # then, check if it's impossible to continue from this branch
-            elif guard.is_true():
-                exit_state = self.state
-            elif o.LAZY_SOLVES not in self.state.options and not self.state.solver.satisfiable(
-                extra_constraints=(claripy.Not(guard),)
+            elif (
+                guard.is_true()
+                or o.LAZY_SOLVES not in self.state.options
+                and not self.state.solver.satisfiable(extra_constraints=(claripy.Not(guard),))
             ):
                 exit_state = self.state
             # one more step, when LAZY_SOLVES is enabled, ignore "bad" jumpkinds
@@ -340,7 +338,7 @@ class HeavyVEXMixin(SuccessorsMixin, ClaripyDataMixin, SimStateStorageMixin, VEX
             result = self.state.solver.simplify(result)
 
         if self.state.solver.symbolic(result) and o.CONCRETIZE in self.state.options:
-            concrete_value = self.state.solver.BVV(self.state.solver.eval(result), len(result))
+            concrete_value = claripy.BVV(self.state.solver.eval(result), len(result))
             self.state.add_constraints(result == concrete_value)
             result = concrete_value
 
@@ -348,9 +346,8 @@ class HeavyVEXMixin(SuccessorsMixin, ClaripyDataMixin, SimStateStorageMixin, VEX
 
     def _perform_vex_expr_Load(self, addr, ty, endness, **kwargs):
         result = super()._perform_vex_expr_Load(addr, ty, endness, **kwargs)
-        if o.UNINITIALIZED_ACCESS_AWARENESS in self.state.options:
-            if getattr(claripy.backends.vsa.convert(addr), "uninitialized", False):
-                raise errors.SimUninitializedAccessError("addr", addr)
+        if o.UNINITIALIZED_ACCESS_AWARENESS in self.state.options and addr.initialized:
+            raise errors.SimUninitializedAccessError("addr", addr)
         return result
 
     def _perform_vex_expr_CCall(self, func_name, ty, args, func=None):